[U-Boot-Users] [PATCH] PPC4xx: Add a non-EEPROM-driven SDRAM Initialization Function for the 405EX(r).

[Grant Erickson]

On 5/18/08 11:19 PM, Stefan Roese wrote:
>>  #if defined(CONFIG_SPD_EEPROM) &&    \
>> (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
>> defined(CONFIG_460EX) || defined(CONFIG_460GT))
>> @@ -3064,9 +3071,116 @@ static void ppc440sp_sdram_register_dump(void)
>> dcr_data = mfdcr(SDRAM_R3BAS);
>> printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
>>  }
>> -#else
>> +#else /* !defined(DEBUG) */
>>  static void ppc440sp_sdram_register_dump(void)
>>  {
>>  }
>> -#endif
>> -#endif /* CONFIG_SPD_EEPROM */
>> +#endif /* defined(DEBUG) */
>> +#elif defined(CONFIG_405EX)
>> +/*------------------------------------------------------------------------
>> ----- + * Function: initdram
>> + * Description: Configures the PPC405EX(r) DDR1/DDR2 SDRAM memory
>> + *   banks. The configuration is performed using static, compile-
>> + *  time parameters.
>> +
>> *--------------------------------------------------------------------------
> 
> Why is this block 405EX specific? This could be used on other 4xx variants
> using the same DDR2 controller, not?

The scope of my visibility is limited, so I punted on this first pass
attempt. More appropriate might have been CONFIG_DDR2_PARAMS vs.
CONFIG_DDR2_EEPROM or CONFIG_DDR2_AUTO.

> And I'm wondering if this code really should go into this
> file "44x_spd_ddr2.c". Since now a 405 variant (405EX) can use this code too
> we should probably change the name to "4xx_spd_ddr2.c". And with this new
> fixed DDR2 init code it the SPD is not really fitting anymore. So the new
> name should probably be "4xx_ddr2.c".
> 
> Comments welcome.

This controller works with both DDR and DDR2 memories, so that might be
misleading. What I'd like to see is a move away from processor-based CONFIG_
and towards feature-based CONFIG_. In that way, we can avoid ever-growing
lists like:

    #if defined(CONFIG_PPCX) || defined(CONFIG_PPCY) || defined(CONFIG_PPCZ)

However, what's needed then are convenient mnemonics for various
cores/blocks. EMAC works well enough for that block. However, DDR/DDR2/SDRAM
seem too generic. Does AMCC call this block something internally that's
leaked out? I see "Denali" used for one memory controller core, correct? Or
is that a board name?

Regards,

Grant
Principal
Nuovation System Designs, LLC

998 Alpine Terrace Suite 3
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gerickson at nuovations.com
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