[U-Boot-Users] [PATCH] mips: tolerate the MIPS 'CFG_HZ' values in the MHZ range for NAND delays

[Scott Wood]

Jason McMullan wrote:
> Rewrite the nand_wait() FL_ERASING case to handle CFG_HZ values in the
> MHZ range. This is needed for mips processors, as the timer's timebase
> ticks at CPU clock frequency.

Even though it's MIPS that needs it, it should be flagged as a NAND 
patch since that's the code it touches.

> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index 2da1d46..ac690ac 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -837,10 +837,17 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state)
>  {
>  	unsigned long	timeo;
>  
> +#if CFG_HZ > 100000
> +	if (state == FL_ERASING)
> + 		timeo = (CFG_HZ / 1000) * 400;
> +	else
> +		timeo = (CFG_HZ / 1000) * 20;
> +#else
>  	if (state == FL_ERASING)
>   		timeo = (CFG_HZ * 400) / 1000;
>  	else
>  		timeo = (CFG_HZ * 20) / 1000;
> +#endif


How about this?

if (state == FL_ERASING)
	timeo = CFG_HZ * 2 / 5;
else
	timeo = CFG_HZ / 50

If we have CFG_HZ values that are within a factor of 2 of wrapping 
around, the platform should probably do some downward scaling (or we 
should think about 64-bit timestamps)...

-Scott