[U-Boot-Users] [PATCH 1/3][MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros

[Shinya Kuribayashi]

Scott Wood wrote:
> On Wed, May 21, 2008 at 12:53:01PM +0900, Shinya Kuribayashi wrote:
>> I disagree with having this structure. Basic strategy for MIPS COUNT/
>> COMPARE handling is, let them overflow (os should I say wrap-around) as
>> they are. All we need is the Delta, not the numbers of overflows.
> 
> You *do* need the full, non-overflowing counter if you want to provide
> the 32-bit millisecond clock that u-boot wants.  Read the recent
> discussion on CFG_HZ that led to this patch.

Ok, here's my proposal. Conceptual patches for MIPS timer routines.
There might be still room for improvement, but I'd like to see something
like thease.

Just build tested. Any comments are appriciated.


  Shinya

---

[MIPS] lib_mips/time.c: Replace CP0 access functions with existing macros

We already have many pre-defined CP0 access macros in <asm/mipsregs.h>.
This patch replaces mips_{compare,count}_set and mips_count_get with
existing macros.

Signed-off-by: Shinya Kuribayashi <skuribay at ruby.dti.ne.jp>
---

 lib_mips/time.c |   35 ++++++++---------------------------
 1 files changed, 8 insertions(+), 27 deletions(-)


diff --git a/lib_mips/time.c b/lib_mips/time.c
index cd8dc72..f03f023 100644
--- a/lib_mips/time.c
+++ b/lib_mips/time.c
@@ -22,26 +22,7 @@
  */
 
 #include <common.h>
-
-
-static inline void mips_compare_set(u32 v)
-{
-	asm volatile ("mtc0 %0, $11" : : "r" (v));
-}
-
-static inline void mips_count_set(u32 v)
-{
-	asm volatile ("mtc0 %0, $9" : : "r" (v));
-}
-
-
-static inline u32 mips_count_get(void)
-{
-	u32 count;
-
-	asm volatile ("mfc0 %0, $9" : "=r" (count) :);
-	return count;
-}
+#include <asm/mipsregs.h>
 
 /*
  * timer without interrupts
@@ -49,25 +30,25 @@ static inline u32 mips_count_get(void)
 
 int timer_init(void)
 {
-	mips_compare_set(0);
-	mips_count_set(0);
+	write_32bit_cp0_register(CP0_COMPARE, 0);
+	write_32bit_cp0_register(CP0_COUNT, 0);
 
 	return 0;
 }
 
 void reset_timer(void)
 {
-	mips_count_set(0);
+	write_32bit_cp0_register(CP0_COUNT, 0);
 }
 
 ulong get_timer(ulong base)
 {
-	return mips_count_get() - base;
+	return read_32bit_cp0_register(CP0_COUNT) - base;
 }
 
 void set_timer(ulong t)
 {
-	mips_count_set(t);
+	write_32bit_cp0_register(CP0_COUNT, t);
 }
 
 void udelay (unsigned long usec)
@@ -76,7 +57,7 @@ void udelay (unsigned long usec)
 	ulong start = get_timer(0);
 
 	tmo = usec * (CFG_HZ / 1000000);
-	while ((ulong)((mips_count_get() - start)) < tmo)
+	while ((ulong)((read_32bit_cp0_register(CP0_COUNT) - start)) < tmo)
 		/*NOP*/;
 }
 
@@ -86,7 +67,7 @@ void udelay (unsigned long usec)
  */
 unsigned long long get_ticks(void)
 {
-	return mips_count_get();
+	return read_32bit_cp0_register(CP0_COUNT);
 }
 
 /*