[U-Boot-Users] [PATCH 3/8] New board SIMPC8313 support: config SIMPC8313.h

Ron Madrid ron_madrid at sbcglobal.net
Fri May 30 20:09:55 CEST 2008


New board SIMPC8313 support: config SIMPC8313.h

Signed-off-by: Ron Madrid
---
 include/configs/SIMPC8313.h |  505
+++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 505 insertions(+), 0 deletions(-)
 create mode 100644 include/configs/SIMPC8313.h

diff --git a/include/configs/SIMPC8313.h
b/include/configs/SIMPC8313.h
new file mode 100644
index 0000000..8afb149
--- /dev/null
+++ b/include/configs/SIMPC8313.h
@@ -0,0 +1,505 @@
+/*
+ * Copyright (C) Sheldon Instruments, Inc. 2008.
+ *
+ * See file CREDITS for list of people who
contributed to this
+ * project.
+ *
+ * This program is free software; you can
redistribute it and/or
+ * modify it under the terms of the GNU General
Public License as
+ * published by the Free Software Foundation; either
version 2 of
+ * the License, or (at your option) any later
version.
+ *
+ * This program is distributed in the hope that it
will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied
warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR
PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General
Public License
+ * along with this program; if not, write to the Free
Software
+ * Foundation, Inc., 59 Temple Place, Suite 330,
Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * simpc8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#undef DEBUG
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC831X		1
+#define CONFIG_MPC8313		1	/* MPC8313 specific */
+
+#define CONFIG_NAND_U_BOOT
+
+#define CONFIG_PCI
+#define CONFIG_83XX_GENERIC_PCI
+
+#ifdef PCI_66M
+#define CONFIG_83XX_CLKIN	66666666	/* in Hz */
+#define CONFIG_83XX_PCICLK	66666666	/* in Hz */
+#else
+#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
+#define CONFIG_83XX_PCICLK	33333333	/* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#ifdef PCI_66M
+#define CONFIG_SYS_CLK_FREQ	66666666
+#else
+#define CONFIG_SYS_CLK_FREQ	33333333
+#endif
+#endif
+
+/* System performance */
+#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth
(0-3) */
+#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count
(0-7) */
+
+/*#define CFG_SCCR		( SCCR_RES \
+				| SCCR_TSEC1CM_1	\
+				| SCCR_TSEC1ON		\
+				| SCCR_TSEC2ON		\
+				| SCCR_ENCCM_3		\
+				| SCCR_USBCM_3		\
+				| SCCR_PCICM		)
+*/
+#define CONFIG_BOARD_EARLY_INIT_F		/* call
board_pre_init */
+#undef  CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_EARLY_INIT_R		/* call board_init
*/
+#undef  CONFIG_BOARD_EARLY_INIT_R
+
+#define CFG_RESET_ADDRESS 	0x30000000
+
+#define CFG_IMMR		0xE0000000
+
+#undef CFG_DRAM_TEST				/* memory test, takes time */
+#define CFG_MEMTEST_START	0x00001000	/* memtest
region */
+#define CFG_MEMTEST_END		0x07F00000
+
+/*
+ * DDR Setup
+ */
+#undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR
setup*/
+
+#define CFG_DDR_BASE		0x00000000	/* DDR is system
memory*/
+#define CFG_SDRAM_BASE		CFG_DDR_BASE
+#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE
+#undef  CONFIG_DDR_2T_TIMING
+
+/*
+ * Manually set up DDR parameters
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED (512 << 20)
+
+#define CFG_DDRCDR		( DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR )
+				/* 0x73000002 TODO ODR & DRN ? */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CFG_NO_FLASH
+
+#define CFG_MONITOR_BASE	TEXT_BASE	/* start of
monitor */
+
+#define CFG_INIT_RAM_LOCK	1
+#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM
address */
+#define CFG_INIT_RAM_END	0x1000		/* End of used area
in RAM*/
+
+#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial
data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END -
CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256
kB for Mon */
+#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserved for
malloc */
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_2	/*
0x00010002 */
+
+#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
+			| (0xFF << LBCR_BMT_SHIFT) \
+			| 0xF )	/* 0x0004ff0f */
+
+#define CFG_LBC_MRTPR	0x20000000  /*TODO */  /* LB
refresh timer prescal, 266MHz/32 */
+
+/* drivers/nand/nand.c */
+#ifdef CONFIG_NAND_SPL
+#define CFG_NAND_BASE		0xFFF00000
+#else
+#define CFG_NAND_BASE		0xE2800000
+#endif
+#define CFG_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+
+#define CFG_NAND_BR_PRELIM	( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8            /* Port Size = 8 bit */ \
+				| BR_MS_FCM          /* MSEL = FCM */ \
+				| BR_V )             /* valid */
+
+#ifdef CONFIG_NAND_SP
+#define CFG_NAND_OR_PRELIM	( 0xFFFF8000	/* length 32K
*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+#define CFG_LBLAWAR0_PRELIM	0x8000000E	/* 32KB  */
+#define CFG_NAND_PAGE_SIZE	(512)		/* NAND chip page
size */
+#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip
block size */
+#define NAND_CACHE_PAGES	32
+#define CFG_NAND_BAD_BLOCK_POS	(5)		/* Bad block
marker location */
+#elif defined(CONFIG_NAND_LP)
+#define CFG_NAND_OR_PRELIM	( 0xFFFC0000	/* length
256K */ \
+				| OR_FCM_PGS \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+#define CFG_LBLAWAR0_PRELIM	0x80000011	/* 256KB  */
+#define CFG_NAND_PAGE_SIZE	(2048)		/* NAND chip page
size */
+#define CFG_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip
block size */
+#define NAND_CACHE_PAGES	64
+#define CFG_NAND_BAD_BLOCK_POS	(0)		/* Bad block
marker location */
+#else
+#error Page size of NAND not defined.
+#endif /* CONFIG_NAND_SP */
+
+#define CFG_LBLAWBAR0_PRELIM	CFG_NAND_BASE
+
+/*
+ * Swap CS0 / CS1 based upon NAND or NOR Flash Boot
mode
+ */
+#define CFG_BR0_PRELIM		CFG_NAND_BR_PRELIM
+#define CFG_OR0_PRELIM		CFG_NAND_OR_PRELIM
+
+/*
+ * NAND Boot Configuration, for board/../nand_boot.c
+ */
+#define CFG_NAND_BR0_PRELIM	CFG_NAND_BR_PRELIM
+#define CFG_NAND_OR0_PRELIM	CFG_OR0_PRELIM
+#define CFG_NAND_LBLAWBAR0_PRELIM	CFG_NAND_BASE
+#define CFG_NAND_LBLAWAR0_PRELIM	CFG_LBLAWAR0_PRELIM
+
+#undef  CFG_NAND_BOOT_QUIET		/* Enable NAND boot
status messages */
+#define CFG_NAND_BOOT_SHOW_ECC_NUM	/* Show corrected
ECC errors */
+#define CFG_NAND_RELOC		(0x10000)	/* Stage 1 load
address */
+#define CFG_NAND_FMR		((14 << FMR_CWTO_SHIFT) | \
+				(1 << FMR_AL_SHIFT))
+
+#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of
RAM U-Boot image */
+#define CFG_NAND_U_BOOT_DST	(0x01000000)	/* Load NUB
to this addr */
+#define CFG_NAND_U_BOOT_START	(CFG_NAND_U_BOOT_DST +
0x120) /* NUB start */
+/*
+ * JFFS2 configuration
+ */
+#define CONFIG_JFFS2_NAND
+#define CONFIG_JFFS2_DEV	"nand0"
+
+/* mtdparts command line support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=nand"
+#define MTDPARTS_DEFAULT
"mtdparts=nand0:1M(u-boot),3M(kernel),-(jffs2)"
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_LIBFDT
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE	8192
+
+#define OF_CPU			"PowerPC,8313 at 0"
+#define OF_SOC			"soc8313 at e0000000"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH	
"/soc8313 at e0000000/serial at 4500"
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	1
+#define CFG_NS16550_CLK		get_bus_freq(0)
+
+#define CFG_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200,
38400,115200}
+
+#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
+#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef  CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware
support*/
+#undef CONFIG_SOFT_I2C			/* I2C bit-banged */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CFG_I2C_SPEED		400000	/* I2C speed and slave
address */
+#define CFG_I2C_SLAVE		0x7F
+#define CFG_I2C_NOPROBES	{{0x69}}	/* Don't probe
these addrs */
+#define CFG_I2C_OFFSET		0x3000
+#define CFG_I2C2_OFFSET		0x3100
+
+/* TSEC */
+#define CFG_TSEC1_OFFSET	0x24000
+#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
+#define CFG_TSEC2_OFFSET	0x25000
+#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
+#define CONFIG_NET_MULTI
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CFG_PCI1_MEM_BASE	0x80000000
+#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
+#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_MMIO_BASE	0x90000000
+#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
+#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI1_IO_BASE	0x00000000
+#define CFG_PCI1_IO_PHYS	0xE2000000
+#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */
+
+/*
+ * TSEC configuration
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"TSEC0"
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_GMII		1	/* MII PHY management */
+#define TSEC1_PHY_ADDR		0x0
+#define TSEC1_FLAGS			TSEC_GIGABIT
+#define TSEC1_PHYIDX		0
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME		"TSEC1"
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_DS1337
+#define CFG_I2C_RTC_ADDR	0x68	/* at address 0x68	*/
+
+/*
+ * Environment
+ */
+#define CFG_ENV_IS_IN_NAND	1
+#define CFG_ENV_SIZE		CFG_NAND_BLOCK_SIZE
+#define CFG_ENV_OFFSET		((1024<<10) -
(CFG_NAND_BLOCK_SIZE<<1))
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial
download */
+#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate
change */
+
+#define CONFIG_CMD_NAND		/* NAND support			*/
+
+#define CONFIG_CMD_AUTOSCRIPT	/* Autoscript Support	
*/
+#define CONFIG_CMD_BDI	       	/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_ENV		/* saveenv			*/
+#define CONFIG_CMD_FPGA		/* FPGA configuration
Support	*/
+#define CONFIG_CMD_IMI		/* iminfo			*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test
*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc
base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep
etc*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot
*/
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_RUN		/* run command in env
variable	*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx	
*/
+#define CONFIG_CMD_XIMG		/* Load part of Multi Image
*/
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_JFFS2
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory */
+#define CFG_LOAD_ADDR	0x2000000	/* default load
address */
+#define CFG_PROMPT	"=> "		/* Monitor Command Prompt
*/
+
+#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
+
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
/* Print Buffer Size */
+#define CFG_MAXARGS	16		/* max number of command args
*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument
Buffer Size */
+#define CFG_HZ		1000		/* decrementer freq: 1ms ticks
*/
+
+/*
+ * For booting Linux, the board info and command line
data
+ * have to be in the first 8 MB of memory, since this
is
+ * the maximum mapped by the Linux kernel during
initialization.
+ */
+#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map
for Linux*/
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE		16384
+#define CFG_CACHELINE_SIZE	32
+
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
+
+#define CFG_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_2_5X1)
+
+#define CFG_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0XFFF00100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_NAND_LP_8BIT |\
+	HRCWH_RL_EXT_NAND |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN |\
+	HRCWH_LALE_NORMAL)
+
+/* System IO Config */
+#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2) /*
RGMII */
+#define CFG_SICRL	SICRL_USBDR /* Enable Internal USB
Phy  */
+
+#define CFG_HID0_INIT	0x000000000
+#define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+
+#define CFG_HID2 HID2_HBE
+
+/* DDR @ 0x00000000 */
+#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10 |
BATL_MEMCOHERENCE)
+#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M |
BATU_VS | BATU_VP)
+#define CFG_IBAT1L	((CFG_SDRAM_BASE + 0x10000000) |
BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT1U	((CFG_SDRAM_BASE + 0x10000000) |
BATU_BL_256M | BATU_VS | BATU_VP)
+
+/* PCI @ 0x80000000 */
+#define CFG_IBAT2L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
+#define CFG_IBAT2U	(CFG_PCI1_MEM_BASE | BATU_BL_256M
| BATU_VS | BATU_VP)
+#define CFG_IBAT3L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 |
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT3U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M
| BATU_VS | BATU_VP)
+
+/* PCI2 not supported on 8313 */
+#define CFG_IBAT4L	(0)
+#define CFG_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @
0xE2400000 */
+#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 |
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS
| BATU_VP)
+
+/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 &
FLASH @ 0xFE000000 */
+#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10 |
BATL_MEMCOHERENCE)
+#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M |
BATU_VS | BATU_VP)
+
+#define CFG_IBAT7L	(0)
+#define CFG_IBAT7U	(0)
+
+#define CFG_DBAT0L	CFG_IBAT0L
+#define CFG_DBAT0U	CFG_IBAT0U
+#define CFG_DBAT1L	CFG_IBAT1L
+#define CFG_DBAT1U	CFG_IBAT1U
+#define CFG_DBAT2L	CFG_IBAT2L
+#define CFG_DBAT2U	CFG_IBAT2U
+#define CFG_DBAT3L	CFG_IBAT3L
+#define CFG_DBAT3U	CFG_IBAT3U
+#define CFG_DBAT4L	CFG_IBAT4L
+#define CFG_DBAT4U	CFG_IBAT4U
+#define CFG_DBAT5L	CFG_IBAT5L
+#define CFG_DBAT5U	CFG_IBAT5U
+#define CFG_DBAT6L	CFG_IBAT6L
+#define CFG_DBAT6U	CFG_IBAT6U
+#define CFG_DBAT7L	CFG_IBAT7L
+#define CFG_DBAT7U	CFG_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot
from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR		00:E0:0C:00:95:01
+
+#define CONFIG_IPADDR		10.196.31.84
+#define CONFIG_SERVERIP		10.196.31.85
+
+#define CONFIG_HOSTNAME		simpc8313
+#define CONFIG_ROOTPATH		/tftpboot/10.196.31.85
+#define CONFIG_BOOTFILE		/tftpboot/uImage
+
+
+#define CONFIG_LOADADDR		500000	/* default location
for tftp and bootm */
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot
*/
+#define CONFIG_BAUDRATE		115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS						\
+	"load_uboot=tftp 100000 u-boot-nand.bin\0"				\
+	"burn_uboot=nand erase u-boot 80000; "				\
+		"nand write 100000 u-boot $filesize\0"				\
+	"update_uboot=run load_uboot;run burn_uboot\0"				\
+	"mtdids=nand0=nand0\0"							\
+
"mtdparts=mtdparts=nand0:1M(u-boot),3M(kernel),-(jffs2)\0"
	\
+	"netdev=eth1\0"								\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "				\
+		"nfsroot=${serverip}:${rootpath}\0"				\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"				\
+	"addip=setenv bootargs ${bootargs} "					\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	
\
+		":${hostname}:${netdev}:off panic=1\0"				\
+	"addtty=setenv bootargs ${bootargs}
console=ttyS0,${baudrate}\0"	\
+	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "	
	\
+		"console=ttyS0,115200\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"nand read 500000 kernel
300000;bootm 500000 - 7e0000"
+#endif	/* __CONFIG_H */
-- 
1.5.5.1






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