[U-Boot] [PATCH][for 1.3.5] 85xx: Ensure timebase is zero on secondary cores

[Kumar Gala]

The e500um says the timebase is volatile out of reset.  To ensure
TB sync works we need to make sure its zero.

Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
---
 cpu/mpc85xx/release.S |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 75676b5..2ae6057 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -37,6 +37,11 @@ __secondary_start_page:
 	li	r3,0x201
 	mtspr	SPRN_BUCSR,r3
 
+	/* Ensure TB is 0 */
+	li	r3,0
+	mttbu	r3
+	mttbl	r3
+
 	/* Enable/invalidate the I-Cache */
 	mfspr	r0,SPRN_L1CSR1
 	ori	r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
-- 
1.5.5.1