[U-Boot] [PATCH 10/11 v1] ARM: OMAP3: Add EVM board

dirk.behme at googlemail.com dirk.behme at googlemail.com
Sun Sep 14 11:54:27 CEST 2008


Subject: [PATCH 10/11 v1] ARM: OMAP3: Add EVM board

From: Dirk Behme <dirk.behme at gmail.com>

Add EVM board

Signed-off-by: Dirk Behme <dirk.behme at gmail.com>

---
 Makefile                    |    3 
 board/omap3/evm/Makefile    |   46 ++++++
 board/omap3/evm/config.mk   |   17 ++
 board/omap3/evm/evm.c       |  199 ++++++++++++++++++++++++++
 board/omap3/evm/u-boot.lds  |   63 ++++++++
 include/configs/omap3_evm.h |  327 ++++++++++++++++++++++++++++++++++++++++++++
 6 files changed, 655 insertions(+)

Index: u-boot_master/board/omap3/evm/Makefile
===================================================================
--- /dev/null
+++ u-boot_master/board/omap3/evm/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= evm.o
+
+$(LIB):	$(OBJS)
+	$(AR) crv $@ $^
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
Index: u-boot_master/board/omap3/evm/config.mk
===================================================================
--- /dev/null
+++ u-boot_master/board/omap3/evm/config.mk
@@ -0,0 +1,17 @@
+#
+# (C) Copyright 2006
+# Texas Instruments, <www.ti.com>
+#
+# Begale Board uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
+
+
Index: u-boot_master/board/omap3/evm/evm.c
===================================================================
--- /dev/null
+++ u-boot_master/board/omap3/evm/evm.c
@@ -0,0 +1,199 @@
+/*
+ * (C) Copyright 2004-2008
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *      Manikandan Pillai <mani.pillai at ti.com>
+ *
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2 at ti.com>
+ *      Syed Mohammed Khasim <khasim at ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <asm/mach-types.h>
+
+const omap3_sysinfo sysinfo = {
+	OMAP3EVM_V1,
+	OMAP3EVM_V2,
+	"35X-Family",
+	"OMAP3 EVM board",
+};
+
+static int setup_net_chip(void);
+
+/******************************************************************************
+ * Routine: board_init
+ * Description: Early hardware init.
+ *****************************************************************************/
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/******************************************************************************
+ * Routine: misc_init_r
+ * Description: Init ethernet (done here so udelay works)
+ *****************************************************************************/
+int misc_init_r(void)
+{
+
+	unsigned char byte;
+
+#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+#endif
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	return 0;
+}
+
+/******************************************************************************
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *              hardware. Many pins need to be moved from protect to primary
+ *              mode.
+ *****************************************************************************/
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT_ES2();
+}
+
+/******************************************************************************
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *              Ethernet hardware. Pin Muxing for the SMC9118 is initialized
+ *              here.
+ *****************************************************************************/
+static int setup_net_chip(void)
+{
+	int i = 0;
+
+	/* Configure GPMC registers */
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0150)) = 0x00001000;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0154)) = 0x001e1e01;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0158)) = 0x00080300;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x015C)) = 0x1c091c09;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0160)) = 0x04181f1f;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0164)) = 0x00000FCF;
+	(*(volatile int *)(OMAP34XX_GPMC_BASE + 0x0168)) = 0x00000f6c;
+
+	/* Configure PIN MUX registers */
+	/* Enable GPMC Pin Mux Registers */
+	/* Enable GPMC_CLK Pin in CONTROL_PADCONF_gpmc_ncs7 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xBC)) |= 0x00180000;
+	/* Enable CS5 Pin in CONTROL_PADCONF_gpmc_ncs5 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) |= 0x00000018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xB8)) &= 0xFFFFFFF8;
+	/* Enable offmode for nwe in CONTROL_PADCONF_GPMC_NWE register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00000F00;
+	/* En off mode for noe and ale in CONTROL_PADCONF_GPMC_NADV_ALE reg */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC0)) |= 0x0E000E00;
+	/* Enable gpmc_nbe0_cle in CONTROL_PADCONF_GPMC_NWE register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC4)) |= 0x00180000;
+
+	/* Enable gpmc_nbe1 in CONTROL_PADCONF_GPMC_NBE1 register and
+	configuring the mux mode to 0 */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) |= 0x00000018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xC8)) &= 0xFFFFFFF8;
+	/* Enable d15 in CONTROL_PADCONF_GPMC_D15 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xAC)) |= 0x00000018;
+	/* Enable d14 - d13 in CONTROL_PADCONF_GPMC_D13 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA8)) |= 0x00180018;
+	/* Enable d12 - d11 in CONTROL_PADCONF_GPMC_D11 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA4)) |= 0x00180018;
+	/* Enable d10 - d9 in CONTROL_PADCONF_GPMC_D9 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xA0)) |= 0x00180018;
+	/* Enable d8 - d7 in CONTROL_PADCONF_GPMC_D7 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x9C)) |= 0x00180018;
+	/* Enable d6 - d5 in CONTROL_PADCONF_GPMC_D5 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x98)) |= 0x00180018;
+	/* Enable d4 - d3 in CONTROL_PADCONF_GPMC_D3 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x94)) |= 0x00180018;
+	/* Enable d2 - d1 in CONTROL_PADCONF_GPMC_D1 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x90)) |= 0x00180018;
+	/* Enable d0 and a10 in CONTROL_PADCONF_GPMC_a10 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) |= 0x00180018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x8C)) &= 0xFFFFFFF8;
+	/* Enable a9 - a8 in CONTROL_PADCONF_GPMC_a8 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) |= 0x00180018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x88)) &= 0xFFF8FFF8;
+	/* Enable a7 - a6 in CONTROL_PADCONF_GPMC_a6 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) |= 0x00180018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x84)) &= 0xFFF8FFF8;
+	/* Enable a5 - a4 in CONTROL_PADCONF_GPMC_a4 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) |= 0x00180018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x80)) &= 0xFFF8FFF8;
+	/* Enable a3 - a2 in CONTROL_PADCONF_GPMC_a2 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) |= 0x00180018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x7C)) &= 0xFFF8FFF8;
+	/* Enable a1 - a0 in CONTROL_PADCONF_GPMC_a0 register */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) |= 0x00000018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x78)) &= 0xFFFFFFF8;
+
+#if defined(CPU_3430_ES1) || defined(CPU_3430_ES2)
+	/* GPIO 64 configuration in CONTROL_PADCONF_GPMC_WAIT2
+	register mux mode is 4. */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000018;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) &= 0xFFFFFFF8;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0xD0)) |= 0x00000004;
+
+	/* Configure GPIO 176 in CONTROL_PADCONF_MCSPI1_CS1
+	register for ethernet ISR mux mode is 4 */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00180000;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) &= 0xFFF8FFFF;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x1D0)) |= 0x00040000;
+
+	/* Enable Clock for GPIO 1-6 module in CM_FCLKEN_PER
+	and CM_ICLKEN_PER registers */
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5000)) |= 0x0003E800;
+	(*(volatile int *)(OMAP34XX_CTRL_BASE + 0x5010)) |= 0x0003E800;
+
+	/* Make GPIO 64 as output pin */
+	(*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x34)) &= ~(0x00000001);
+
+	/* Now send a pulse on the GPIO pin */
+	(*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001;
+	for (i = 0; i < 99 ; i++);
+	(*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) &= ~(0x00000001);
+	for (i = 0; i < 99 ; i++);
+	(*(volatile int *)(OMAP34XX_GPIO3_BASE + 0x3C)) |= 0x00000001;
+#else
+	printf("Unknown revision... \n\n");
+#endif
+	return 0;
+}
+
Index: u-boot_master/board/omap3/evm/u-boot.lds
===================================================================
--- /dev/null
+++ u-boot_master/board/omap3/evm/u-boot.lds
@@ -0,0 +1,63 @@
+/*
+ * January 2004 - Changed to support H4 device
+ * Copyright (c) 2004 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/omap3/start.o	(.text)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	.ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+	__exidx_start = .;
+	.ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+	__exidx_end = .;
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
Index: u-boot_master/include/configs/omap3_evm.h
===================================================================
--- /dev/null
+++ u-boot_master/include/configs/omap3_evm.h
@@ -0,0 +1,327 @@
+/*
+ * (C) Copyright 2006-2008
+ * Texas Instruments.
+
+ * Author :
+ * 	Manikandan Pillai <mani.pillai at ti.com>
+ * Derived from Beagle Board and 3430 SDP code by
+ *      Richard Woodruff <r-woodruff2 at ti.com>
+ *      Syed Mohammed Khasim <khasim at ti.com>
+ *
+ * Manikandan Pillai <mani.pillai at ti.com>
+ *
+ * Configuration settings for the TI OMAP3 EVM board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_EVM	1	/* working with EVM */
+#define CONFIG_DOS_PARTITION	1
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ		/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE		SZ_128K	/* Total Size Environment Sector */
+#define CFG_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CFG_GBL_DATA_SIZE	128	/* bytes reserved for initial data */
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK		(48000000)	/* 48MHz (APLL96/2) */
+
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE	(-4)
+#define CFG_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX	1
+#define CFG_NS16550_COM1	OMAP34XX_UART1
+#define CONFIG_SERIAL1		1	/* UART1 on OMAP3 EVM */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE		115200
+#define CFG_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_MMC		1
+#define CFG_MMC_BASE		0xF0000000
+#define CONFIG_DOS_PARTITION	1
+
+/* commands to include */
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_I2C          /* I2C serial bus support       */
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+
+#define CONFIG_CMD_AUTOSCRIPT	/* autoscript support		*/
+#define CONFIG_CMD_BDI		/* bdinfo			*/
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+#define CONFIG_CMD_ENV		/* saveenv			*/
+#define CONFIG_CMD_ITEST	/* Integer (and string) test	*/
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* misc functions like sleep etc*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot    */
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS          /* NFS support                  */
+
+#define CFG_NO_FLASH
+#define CFG_I2C_SPEED			100000
+#define CFG_I2C_SLAVE			1
+#define CFG_I2C_BUS			0
+#define CFG_I2C_BUS_SELECT		1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ *  Board NAND Info.
+ */
+#define CFG_NAND_ADDR NAND_BASE	/* physical address to access nand */
+#define CFG_NAND_BASE NAND_BASE	/* physical address to access nand at CS0 */
+#define CFG_NAND_WIDTH_16
+
+#define CFG_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
+#define SECTORSIZE		512
+
+#define NAND_ALLOW_ERASE_ALL
+#define ADDR_COLUMN		1
+#define ADDR_PAGE		2
+#define ADDR_COLUMN_PAGE	3
+
+#define NAND_ChipID_UNKNOWN	0x00
+#define NAND_MAX_FLOORS		1
+#define NAND_MAX_CHIPS		1
+#define NAND_NO_RB		1
+#define CFG_NAND_WP
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTCOMMAND	"onenand read 80200000 280000 400000 ; \
+				bootm 80200000"
+
+#define CONFIG_BOOTARGS	"setenv bootargs console=ttyS2,115200n8 noinitrd \
+				root=/dev/mtdblock4 rw rootfstype=jffs2"
+
+#define CONFIG_NETMASK		255.255.254.0
+#define CONFIG_IPADDR		128.247.77.90
+#define CONFIG_SERVERIP		128.247.77.158
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_AUTO_COMPLETE	1
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT		"OMAP3_EVM # "
+
+#define CFG_LONGHELP		/* undef to save memory */
+#define CFG_PROMPT		V_PROMPT
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CFG_PBSIZE		(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
+#define CFG_MAXARGS		16	/* max number of command args */
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest works on */
+#define CFG_MEMTEST_END		(OMAP34XX_SDRC_CS0+0x01F00000) /* 31MB */
+
+#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load address */
+
+/* 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define V_PVT			7
+
+#define CFG_TIMERBASE		OMAP34XX_GPT2
+#define CFG_PVT			V_PVT	/* 2^(pvt+1) */
+#define CFG_HZ			((V_SCLK)/(2 << CFG_PVT))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	SZ_128K	/* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K	/* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ	SZ_4K	/* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NOR_SIZE_SDPV2	GPMC_SIZE_128M
+#define PISMO1_NOR_SIZE		GPMC_SIZE_64M
+
+#define PISMO1_NAND_SIZE	GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE	GPMC_SIZE_128M
+#define DBG_MPDB_SIZE		GPMC_SIZE_16M
+#define PISMO2_SIZE		0
+
+#define CFG_MAX_FLASH_SECT	(520)	/* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS      2	/* max number of flash banks */
+#define CFG_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define PHYS_FLASH_SIZE_SDPV2	SZ_128M
+#define PHYS_FLASH_SIZE		SZ_32M
+
+#define CFG_FLASH_BASE		boot_flash_base
+#define PHYS_FLASH_SECT_SIZE	boot_flash_sec
+/* Dummy declaration of flash banks to get compilation right */
+#define CFG_FLASH_BANKS_LIST	{0, 0}
+
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE	/* Monitor at start of flash */
+#define CFG_ONENAND_BASE	ONENAND_MAP
+
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define ONENAND_ENV_OFFSET	0x260000	/* environment starts here  */
+#define SMNAND_ENV_OFFSET	0x260000	/* environment starts here  */
+
+#define CFG_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET	boot_flash_off
+#define CONFIG_ENV_ADDR		boot_flash_env_addr
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT	(100*CFG_HZ)	/* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT	(100*CFG_HZ)	/* Timeout for Flash Write */
+
+/* Flash banks JFFS2 should use */
+#define CFG_MAX_MTD_BANKS	(CFG_MAX_FLASH_BANKS+CFG_MAX_NAND_DEVICE)
+#define CFG_JFFS2_MEM_NAND
+#define CFG_JFFS2_FIRST_BANK	CFG_MAX_FLASH_BANKS	/* use flash_info[2] */
+#define CFG_JFFS2_NUM_BANKS	1
+
+#define ENV_IS_VARIABLE		1
+
+#ifndef __ASSEMBLY__
+extern unsigned int nand_cs_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+
+#define WRITE_NAND_COMMAND(d, adr)\
+		       __raw_writew(d, (nand_cs_base + GPMC_NAND_CMD))
+#define WRITE_NAND_ADDRESS(d, adr)\
+		       __raw_writew(d, (nand_cs_base + GPMC_NAND_ADR))
+#define WRITE_NAND(d, adr) __raw_writew(d, (nand_cs_base + GPMC_NAND_DAT))
+#define READ_NAND(adr) __raw_readw((nand_cs_base + GPMC_NAND_DAT))
+
+/* Other NAND Access APIs */
+#define NAND_WP_OFF()\
+		do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
+#define NAND_WP_ON()\
+		do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
+#define NAND_DISABLE_CE(nand)
+#define NAND_ENABLE_CE(nand)
+#define NAND_WAIT_READY(nand)	udelay(10)
+
+
+/*----------------------------------------------------------------------------
+ *  SMSC9115 Ethernet from SMSC9118 family
+ *  ----------------------------------------------------------------------------
+ */
+#if defined(CONFIG_CMD_NET)
+
+#define CONFIG_DRIVER_SMC911X
+#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_DRIVER_SMC911X_BASE	(0x2C000000)
+
+#endif  /* (CONFIG_CMD_NET) */
+
+/*
+ *  BOOTP fields
+ */
+
+
+#define CONFIG_BOOTP_SUBNETMASK		0x00000001
+#define CONFIG_BOOTP_GATEWAY		0x00000002
+#define CONFIG_BOOTP_HOSTNAME		0x00000004
+#define CONFIG_BOOTP_BOOTPATH		0x00000010
+
+#endif				/* __CONFIG_H */
Index: u-boot_master/Makefile
===================================================================
--- u-boot_master.orig/Makefile
+++ u-boot_master/Makefile
@@ -2719,6 +2719,9 @@ SMN42_config	:	unconfig
 omap3_beagle_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm omap3 beagle omap3
 
+omap3_evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm omap3 evm omap3
+
 #########################################################################
 ## XScale Systems
 #########################################################################


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