[U-Boot] [PATCH] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz

[Victor Gallardo]

>> +
>> +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
>> +/*
>> + * This is for quicker auto calibration boot up once WRDTR and CLKTR
>> + * values for the kilauea board were determined and are therefore known.
>> + *
>> + * Use these scan options for PLB bus greater than 200MHz else use
>> + * the defaults.
>> + */
>> +/* List of (SDRAM_WRDTR.[WDTR], SDRAM_CLKTR.[CLKP]) pairs to try */ 
>> +struct sdram_timing quick_scan_options[] = {
>> +	{0, 3}, {1, 1}, {1, 2}, {1, 3},
>> +	{2, 1}, {2, 2}, {2, 3}, {3, 1},
>> +	{3, 2}, {4, 1}, {-1, -1}
>> +};
>
> It's not really clear to me, why this reduced list should fix this problem
> seen on the 600MHz boards (it does - I tested successfully on my board).
> From my understanding the scan is now skipping some of the WDTR/CLKTR
> configurations. This will of course result in a quicker scan, but
> autocalibration should still work with the default full list.
>

Hi Stefan, yes you are correct, it should, but for some reason the full list causes problem. This is currently being investigated by HW team. Current work around is to reduce the WDTR/CLKTR to only those that produce a cycle delay of T2 or better.

-Victor Gallardo