[U-Boot] [PATCH 3/4] Enable NAND support for MPC8536DS board

[Jason Jin]

Define NAND support the 8536DS board. Add mem space and corresponding
law/tlb entries for it.

Signed-off-by: Jason Jin <Jason.jin at freescale.com>
---
 board/freescale/mpc8536ds/law.c |    1 +
 board/freescale/mpc8536ds/tlb.c |    4 +++
 include/configs/MPC8536DS.h     |   52 ++++++++++++++++++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 1 deletions(-)

diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index cdf5215..84b23a3 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -38,6 +38,7 @@ struct law_entry law_table[] = {
 	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CFG_NAND_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 28a9fa8..55e5702 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -66,6 +66,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256K, 1),
+
+	SET_TLB_ENTRY(1, CFG_NAND_BASE, CFG_NAND_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_16M, 1),
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 17cc934..4487a9e 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -162,8 +162,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
  *
  * Localbus non-cacheable
- * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe000_0000	0xe7ff_ffff	Promjet/free		128M non-cacheable
  * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xf000_0000	0xf0ff_ffff	NAND			16M non-cacheable
  * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
@@ -250,6 +251,55 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CFG_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
 #define CFG_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
 
+#define CFG_NAND_BASE           0xf0000000
+#define CFG_NAND_BASE_LIST	{ CFG_NAND_BASE, CFG_NAND_BASE + 0x40000, \
+				CFG_NAND_BASE + 0x80000, CFG_NAND_BASE + 0xC0000}
+#define CFG_MAX_NAND_DEVICE	4
+#define NAND_MAX_CHIPS		1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND	1
+#define CONFIG_NAND_FSL_ELBC	1
+#define CFG_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CFG_NAND_BR_PRELIM      ( CFG_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_NAND_OR_PRELIM      ( 0xFFFC0000            /* length 256K */ \
+				| OR_FCM_PGS            /*Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CFG_BR2_PRELIM          CFG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CFG_OR2_PRELIM          CFG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CFG_BR4_PRELIM          ((CFG_NAND_BASE + 0x40000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR4_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR5_PRELIM          ((CFG_NAND_BASE + 0x80000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR5_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CFG_BR6_PRELIM          ((CFG_NAND_BASE + 0xC0000)\
+				| (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+				| BR_PS_8               /* Port Size = 8 bit */ \
+				| BR_MS_FCM             /* MSEL = FCM */ \
+				| BR_V)                 /* valid */
+#define CFG_OR6_PRELIM          CFG_NAND_OR_PRELIM	/* NAND Options */
+
 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
-- 
1.5.4