[U-Boot] [PATCH v2] ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz

[Wolfgang Denk]

Dear Victor,

in message <1221573553-1882-1-git-send-email-vgallardo at amcc.com> you wrote:
> 
...
> + * Use these scan options for PLB bus greater than or equal 200MHz
> + * else use the defaults. These options are known to return a cycle
> + * delay of T2 or better with a 200MHz PLB bus. Scanning the
> + * full list of WDTR/CLKTR should work, but currently it does not.
> + * HW team is investigating.

As you probably have noticed, I hesitate to pull  the  current  patch
into  mainline,  because  it is still based on a temporary workaround.

Do you have any information when a clean solution for hte problem can
be expected? I really would like to wait for the final patch.

What do you think?

Best regards,

Wolfgang Denk

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