[U-Boot] [RFC][PATCH 2b/3] New i386 board (includes code relocation)
Graeme Russ
graeme.russ at gmail.com
Mon Sep 29 15:27:39 CEST 2008
Split to meet mailing list size limit
Initial addition of eNET files - builds clean but will not run until
additional i386 code changes are made
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
--
diff --git a/board/eNET/fpga.c b/board/eNET/fpga.c
new file mode 100644
index 0000000..a3e4677
--- /dev/null
+++ b/board/eNET/fpga.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Grandegger, DENX Software Engineering, wg at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <common.h>
+#include <command.h>
+#include <linux/ctype.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/ssi.h>
+#include <watchdog.h>
+#include <asm/io.h>
+
+#include "fpga.h"
+
+static u8 fpga_init(void);
+static u8 fpga_write(void *buf, size_t bsize);
+static u8 fpga_finalise(void);
+static void fpga_close(void);
+
+
+int fpga_load(int devnum, void *buf, size_t bsize )
+{
+ u8 ret = FPGA_SUCCESS;
+
+ WATCHDOG_RESET();
+
+ ret = fpga_init();
+
+ if (ret == FPGA_SUCCESS) {
+ ret = fpga_write(buf, bsize);
+ }
+
+ if (ret == FPGA_SUCCESS) {
+ ret = fpga_finalise();
+ }
+
+ fpga_close();
+
+ WATCHDOG_RESET();
+
+ return ret;
+}
+
+
+static u8 fpga_init(void)
+{
+ u8 ret = FPGA_FAIL_INIT;
+ u16 state = 0x0000;
+
+ /*
+ * Drop then raise the FPGA's program bit
+ */
+ writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_CLR);
+ udelay(CFG_FPGA_PROGRAM_BIT_DROP_TIME * 1000);
+ writew(CFG_FPGA_PROGRAM_PIO_BIT, CFG_FPGA_PIO_SET);
+
+ reset_timer();
+
+ while (get_timer(0) < CFG_FPGA_MAX_INIT_TIME) {
+ /*
+ * Check if the FPGA has raised its initialized bit
+ */
+ state = readw(CFG_FPGA_PIO_DATA);
+
+ if (state & CFG_FPGA_INIT_PIO_BIT) {
+ ret = FPGA_SUCCESS;
+ goto Done;
+ }
+
+ udelay (10);
+ }
+
+Done:
+ return ret;
+}
+
+
+static u8 fpga_write(void *buf, size_t bsize)
+{
+ u8 *ptr = (u8 *) buf;
+
+ /*
+ * Stream the buffer to the FPGA using the SSI
+ */
+ ssi_set_interface(CFG_FPGA_SSI_DATA_RATE, 0, 0, 0);
+
+ /*
+ * TODO: Can ssi_tx_byte() fail (port busy)?
+ */
+ while (bsize--)
+ ssi_tx_byte (*ptr);
+
+ return FPGA_SUCCESS;
+}
+
+
+static u8 fpga_finalise(void)
+{
+ u8 ret = FPGA_FAIL_FINALISE;
+ u16 state = 0x0000;
+
+ reset_timer();
+
+ while (get_timer(0) < CFG_FPGA_MAX_FINALISE_TIME) {
+ state = readw(CFG_FPGA_PIO_DATA);
+
+ if (state & CFG_FPGA_DONE_PIO_BIT) {
+ ret = FPGA_SUCCESS;
+ goto Done;
+ }
+
+ udelay (10);
+ }
+
+Done:
+ return ret;
+}
+
+static void fpga_close(void)
+{
+ u16 dirs = readw(CFG_FPGA_PIO_DIRECTION);
+
+ /*
+ * Set the program pin of the FPGA to be an input (high impedance)
+ */
+ dirs &= ~CFG_FPGA_PROGRAM_PIO_BIT;
+
+ writew(dirs, CFG_FPGA_PIO_DIRECTION);
+}
diff --git a/board/eNET/fpga.h b/board/eNET/fpga.h
new file mode 100644
index 0000000..a4db321
--- /dev/null
+++ b/board/eNET/fpga.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ at gmail.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef _FPGA_H_
+#define _FPGA_H_
+
+#define FPGA_SUCCESS 0
+#define FPGA_FAIL_INIT 1
+#define FPGA_FAIL_FINALISE 2
+#define FPGA_FAIL_START 3
+
+
+
+int fpga_load( int devnum, void *buf, size_t bsize );
+
+#endif /* _FPGA_H_ */
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
new file mode 100644
index 0000000..eab612c
--- /dev/null
+++ b/board/eNET/hardware.h
@@ -0,0 +1,13 @@
+/*
+ * hardware.h
+ *
+ * Created on: 17/09/2008
+ * Author: graeme
+ */
+
+#ifndef HARDWARE_H_
+#define HARDWARE_H_
+
+#include "hardware_defs.h"
+
+#endif /* HARDWARE_H_ */
diff --git a/board/eNET/hardware_defs.h b/board/eNET/hardware_defs.h
new file mode 100644
index 0000000..2ffa008
--- /dev/null
+++ b/board/eNET/hardware_defs.h
@@ -0,0 +1,19 @@
+/*
+ * hardware.h
+ *
+ * Created on: 11/09/2008
+ * Author: graeme
+ */
+
+#ifndef HARDWARE_DEFS_H_
+#define HARDWARE_DEFS_H_
+
+#define LED_LATCH_ADDRESS 0x1002
+#define LED_RUN_BITMASK 0x01
+#define LED_1_BITMASK 0x02
+#define LED_2_BITMASK 0x04
+#define LED_RX_BITMASK 0x08
+#define LED_TX_BITMASK 0x10
+#define LED_ERR_BITMASK 0x20
+
+#endif /* HARDWARE_H_ */
diff --git a/board/eNET/u-boot.lds b/board/eNET/u-boot.lds
new file mode 100644
index 0000000..7855c0b
--- /dev/null
+++ b/board/eNET/u-boot.lds
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engstr�m, Omicron Ceti AB, daniel at omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+ENTRY(_start)
+
+SECTIONS
+{
+ . = 0x38040000; /* Where bootcode in the flash is mapped */
+ .text : { *(.text); }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) *(.rodata.str1.1) *(.rodata.str1.32) }
+
+ _i386boot_text_size = SIZEOF(.text) + SIZEOF(.rodata);
+
+ . = 0x03FF0000; /* Ram data segment to use */
+ _i386boot_romdata_dest = ABSOLUTE(.);
+ .data : AT ( LOADADDR(.rodata) + SIZEOF(.rodata) ) { *(.data) }
+ _i386boot_romdata_start = LOADADDR(.data);
+
+ . = ALIGN(4);
+ .got : AT ( LOADADDR(.data) + SIZEOF(.data) ) { *(.got) }
+
+ . = ALIGN(4);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+ _i386boot_cmd_start = LOADADDR(.u_boot_cmd);
+
+ _i386boot_romdata_size = SIZEOF(.data) + SIZEOF(.got) + SIZEOF(.u_boot_cmd);
+
+ . = ALIGN(4);
+ _i386boot_bss_start = ABSOLUTE(.);
+ .bss (NOLOAD) : { *(.bss) }
+ _i386boot_bss_size = SIZEOF(.bss);
+
+ /* 16bit realmode trampoline code */
+ .realmode 0x7c0 : AT ( LOADADDR(.got) + SIZEOF(.got) + SIZEOF(.u_boot_cmd)) { *(.realmode) }
+
+ _i386boot_realmode = LOADADDR(.realmode);
+ _i386boot_realmode_size = SIZEOF(.realmode);
+
+ /* 16bit BIOS emulation code (just enough to boot Linux) */
+ .bios 0 : AT ( LOADADDR(.realmode) + SIZEOF(.realmode) ) { *(.bios) }
+
+ _i386boot_bios = LOADADDR(.bios);
+ _i386boot_bios_size = SIZEOF(.bios);
+
+ /* The load addresses below assumes that the flash
+ * will be mapped so that 0x387f0000 == 0xffff0000
+ * at reset time
+ *
+ * The fe00 and ff00 offsets of the start32 and start16
+ * segments are arbitrary, the just have to be mapped
+ * at reset and the code have to fit.
+ * The fff0 offset of reset is important, however.
+ */
+
+ . = 0xfffffe00;
+ .start32 : AT (0x3807fe00) { *(.start32); }
+
+ . = 0xf800;
+ .start16 : AT (0x3807f800) { *(.start16); }
+
+ . = 0xfff0;
+ .reset : AT (0x3807fff0) { *(.reset); }
+ _i386boot_end = (LOADADDR(.reset) + SIZEOF(.reset) );
+}
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 640b255..a5724b6 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -32,7 +32,7 @@
#include <config.h>
#include <pci.h>
#ifdef CONFIG_SC520_SSI
-#include <ssi.h>
+#include <asm/ic/ssi.h>
#endif
#include <asm/io.h>
#include <asm/pci.h>
diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c
index d99af26..047d3aa 100644
--- a/examples/82559_eeprom.c
+++ b/examples/82559_eeprom.c
@@ -19,7 +19,7 @@
*/
#define _PPC_STRING_H_ /* avoid unnecessary str/mem functions */
-#define _LINUX_STRING_H_ /* avoid unnecessary str/mem functions */
+/* #define _LINUX_STRING_H_ */ /* avoid unnecessary str/mem functions */
#include <common.h>
#include <exports.h>
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index 0f7e7a5..2da01ea 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -312,7 +312,10 @@ extern int sc520_pci_ints[];
void init_sc520(void);
unsigned long init_sc520_dram(void);
+
+#ifdef CONFIG_PCI
void pci_sc520_init(struct pci_controller *hose);
int pci_sc520_set_irq(int pci_pin, int irq);
+#endif
#endif
diff --git a/include/asm-i386/ic/sc520_defs.h b/include/asm-i386/ic/sc520_defs.h
new file mode 100644
index 0000000..c8f6311
--- /dev/null
+++ b/include/asm-i386/ic/sc520_defs.h
@@ -0,0 +1,1489 @@
+/*
+ * sc520_defs.h
+ *
+ * Created on: 17/09/2008
+ * Author: graeme
+ */
+
+#ifndef _ASM_IC_SC520_DEFS_H_
+#define _ASM_IC_SC520_DEFS_H_
+
+/* Memory mapped configuration registers, MMCR */
+#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */
+#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */
+#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */
+#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */
+#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/
+#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/
+#define SC520_ECCCTL 0x0020 /* ECC Control Register */
+#define SC520_ECCSTA 0x0021 /* ECC Status Register */
+#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */
+#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */
+#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */
+#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */
+#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */
+#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */
+#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */
+#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */
+#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */
+#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */
+#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */
+#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */
+#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */
+#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */
+#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */
+#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */
+#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */
+#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */
+#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */
+#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */
+#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */
+#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */
+#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */
+#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */
+#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */
+#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */
+#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */
+#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */
+#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */
+#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */
+#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */
+#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
+#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
+#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */
+#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */
+#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */
+#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */
+#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */
+#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */
+#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */
+#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */
+#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */
+#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */
+#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */
+#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */
+#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */
+#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */
+#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */
+#define SC520_CLKSEL 0x0c26 /* Clock Select */
+#define SC520_DSCTL 0x0c28 /* Drive Strength Control */
+#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */
+#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */
+#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */
+#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */
+#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */
+#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */
+#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */
+#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */
+#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
+#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */
+#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */
+#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */
+#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */
+#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */
+#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */
+#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */
+#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */
+#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */
+#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */
+#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */
+#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */
+#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */
+#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */
+#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */
+#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */
+#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */
+#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */
+#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */
+#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */
+#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */
+#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */
+#define SC520_SSICTL 0x0cd0 /* SSI Control */
+#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */
+#define SC520_SSICMD 0x0cd2 /* SSI Command */
+#define SC520_SSISTA 0x0cd3 /* SSI Status */
+#define SC520_SSIRCV 0x0cd4 /* SSI Receive */
+#define SC520_PICICR 0x0d00 /* Interrupt Control Register */
+#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */
+#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */
+#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */
+#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */
+#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */
+#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */
+#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */
+#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */
+#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */
+#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */
+#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */
+#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */
+#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */
+#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */
+#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */
+#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */
+#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */
+#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */
+#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */
+#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */
+#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */
+#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */
+#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */
+#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */
+#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */
+#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */
+#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */
+#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */
+#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */
+#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */
+#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */
+#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */
+#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */
+#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */
+#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */
+#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */
+#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */
+#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */
+#define SC520_SYSINFO 0x0d70 /* System Board Information Register */
+#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */
+#define SC520_RESSTA 0x0d74 /* Reset Status Register */
+#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */
+#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */
+#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */
+#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */
+#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */
+#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */
+#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */
+#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */
+#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */
+#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */
+#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */
+#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */
+#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */
+#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */
+#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */
+#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */
+#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */
+#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */
+#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */
+#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */
+#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */
+#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */
+#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */
+#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */
+#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */
+#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */
+#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */
+#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */
+#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */
+#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */
+#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */
+
+/* MMCR Register bits (not all of them :) ) */
+
+/* SSI Stuff */
+#define CTL_CLK_SEL_4 0x00 /* Nominal Bit Rate = 8 MHz */
+#define CTL_CLK_SEL_8 0x10 /* Nominal Bit Rate = 4 MHz */
+#define CTL_CLK_SEL_16 0x20 /* Nominal Bit Rate = 2 MHz */
+#define CTL_CLK_SEL_32 0x30 /* Nominal Bit Rate = 1 MHz */
+#define CTL_CLK_SEL_64 0x40 /* Nominal Bit Rate = 512 KHz */
+#define CTL_CLK_SEL_128 0x50 /* Nominal Bit Rate = 256 KHz */
+#define CTL_CLK_SEL_256 0x60 /* Nominal Bit Rate = 128 KHz */
+#define CTL_CLK_SEL_512 0x70 /* Nominal Bit Rate = 64 KHz */
+
+#define TC_INT_ENB 0x08 /* Transaction Complete Interrupt Enable */
+#define PHS_INV_ENB 0x04 /* SSI Inverted Phase Mode Enable */
+#define CLK_INV_ENB 0x02 /* SSI Inverted Clock Mode Enable */
+#define MSBF_ENB 0x01 /* SSI Most Significant Bit First Mode Enable */
+
+#define SSICMD_CMD_SEL_XMITRCV 0x03 /* Simultaneous Transmit / Receive Transaction */
+#define SSICMD_CMD_SEL_RCV 0x02 /* Receive Transaction */
+#define SSICMD_CMD_SEL_XMIT 0x01 /* Transmit Transaction */
+#define SSISTA_BSY 0x02 /* SSI Busy */
+#define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */
+
+
+/* BITS for SC520_ADDDECCTL: */
+#define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */
+#define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */
+#define RTC_DIS 0x04 /* RTC Disable */
+#define UART2_DIS 0x02 /* UART2 Disable */
+#define UART1_DIS 0x01 /* UART1 Disable */
+
+/* bus mapping constants (used for PCI core initialization) */ /* bus mapping constants */
+#define SC520_REG_ADDR 0x00000cf8
+#define SC520_REG_DATA 0x00000cfc
+
+
+#define SC520_ISA_MEM_PHYS 0x00000000
+#define SC520_ISA_MEM_BUS 0x00000000
+#define SC520_ISA_MEM_SIZE 0x01000000
+
+#define SC520_ISA_IO_PHYS 0x00000000
+#define SC520_ISA_IO_BUS 0x00000000
+#define SC520_ISA_IO_SIZE 0x00001000
+
+/* PCI I/O space from 0x1000 to 0xdfff
+ * (make 0xe000-0xfdff available for stuff like PCCard boot) */
+#define SC520_PCI_IO_PHYS 0x00001000
+#define SC520_PCI_IO_BUS 0x00001000
+#define SC520_PCI_IO_SIZE 0x0000d000
+
+/* system memory from 0x00000000 to 0x0fffffff */
+#define SC520_PCI_MEMORY_PHYS 0x00000000
+#define SC520_PCI_MEMORY_BUS 0x00000000
+#define SC520_PCI_MEMORY_SIZE 0x10000000
+
+/* PCI bus memory from 0x10000000 to 0x26ffffff
+ * (make 0x27000000 - 0x27ffffff available for stuff like PCCard boot) */
+#define SC520_PCI_MEM_PHYS 0x10000000
+#define SC520_PCI_MEM_BUS 0x10000000
+#define SC520_PCI_MEM_SIZE 0x17000000
+
+/* 0x28000000 - 0x3fffffff is used by the flash banks */
+
+/* 0x40000000 - 0xffffffff is not adressable by the SC520 */
+
+/* priority numbers used for interrupt channel mappings */
+#define SC520_IRQ_DISABLED 0
+#define SC520_IRQ0 1
+#define SC520_IRQ1 2
+#define SC520_IRQ2 4 /* same as IRQ9 */
+#define SC520_IRQ3 11
+#define SC520_IRQ4 12
+#define SC520_IRQ5 13
+#define SC520_IRQ6 21
+#define SC520_IRQ7 22
+#define SC520_IRQ8 3
+#define SC520_IRQ9 4
+#define SC520_IRQ10 5
+#define SC520_IRQ11 6
+#define SC520_IRQ12 7
+#define SC520_IRQ13 8
+#define SC520_IRQ14 9
+#define SC520_IRQ15 10
+
+
+/* pin number used for PCI interrupt mappings */
+#define SC520_PCI_INTA 0
+#define SC520_PCI_INTB 1
+#define SC520_PCI_INTC 2
+#define SC520_PCI_INTD 3
+#define SC520_PCI_GPIRQ0 4
+#define SC520_PCI_GPIRQ1 5
+#define SC520_PCI_GPIRQ2 6
+#define SC520_PCI_GPIRQ3 7
+#define SC520_PCI_GPIRQ4 8
+#define SC520_PCI_GPIRQ5 9
+#define SC520_PCI_GPIRQ6 10
+#define SC520_PCI_GPIRQ7 11
+#define SC520_PCI_GPIRQ8 12
+#define SC520_PCI_GPIRQ9 13
+#define SC520_PCI_GPIRQ10 14
+
+
+
+/* PIC I/O mapped registers */
+
+#define MPICIR 0x20 /* Master PIC Interrupt Request Register */
+#define MPICISR 0x20 /* Master PIC In-Service Register */
+#define MPICICW1 0x20 /* Master PIC Initialization Control Word 1 Register */
+#define MPICOCW2 0x20 /* Master PIC Operation Control Word 2 Register */
+#define MPICOCW3 0x20 /* Master PIC Operation Control Word 3 Register */
+
+#define MPICICW2 0x21 /* Master PIC Initialization Control Word 2 Register */
+#define MPICICW3 0x21 /* Master PIC Initialization Control Word 3 Register */
+#define MPICICW4 0x21 /* Master PIC Initialization Control Word 4 Register */
+#define MPICINTMSK 0x21 /* Master PIC Interrupt Mask Register */
+
+#define S2PICIR 0x24 /* Slave 2 PIC Interrupt Request Register */
+#define S2PICISR 0x24 /* Slave 2 PIC In-Service Register */
+#define S2PICICW1 0x24 /* Slave 2 PIC Initialization Control Word 1 Register */
+#define S2PICOCW2 0x24 /* Slave 2 PIC Operation Control Word 2 Register */
+#define S2PICOCW3 0x24 /* Slave 2 PIC Operation Control Word 3 Register */
+
+#define S2PICICW2 0x25 /* Slave 2 PIC Initialization Control Word 2 Register */
+#define S2PICICW3 0x25 /* Slave 2 PIC Initialization Control Word 3 Register */
+#define S2PICICW4 0x25 /* Slave 2 PIC Initialization Control Word 4 Register */
+#define S2PICINTMSK 0x25 /* Slave 2 PIC Interrupt Mask Register */
+
+#define S1PICIR 0xa0 /* Slave 1 PIC Interrupt Request Register */
+#define S1PICISR 0xa0 /* Slave 1 PIC In-Service Register */
+#define S1PICICW1 0xa0 /* Slave 1 PIC Initialization Control Word 1 Register */
+#define S1PICOCW2 0xa0 /* Slave 1 PIC Operation Control Word 2 Register */
+#define S1PICOCW3 0xa0 /* Slave 1 PIC Operation Control Word 3 Register */
+
+#define S1PICICW2 0xa1 /* Slave 1 PIC Initialization Control Word 2 Register */
+#define S1PICICW3 0xa1 /* Slave 1 PIC Initialization Control Word 3 Register */
+#define S1PICICW4 0xa1 /* Slave 1 PIC Initialization Control Word 4 Register */
+#define S1PICINTMSK 0xa1 /* Slave 1 PIC Interrupt Mask Register */
+
+/*
+Programmable Interrupt Controller Register Bit Definitions
+*/
+
+/* Interrupt Control Register Bit Definitions */
+
+#define NMI_DONE 0x80 /* NMI Routine Done */
+#define NMI_ENB 0x40 /* Master NMI Done */
+#define S2_GINT_MODE 0x04 /* Slave 2 PIC Global Interrupt Mode Enable */
+#define S1_GINT_MODE 0x02 /* Slave 1 PIC Global Interrupt Mode Enable */
+#define M_GINT_MODE 0x01 /* Master PIC Global Interrupt Mode Enable */
+
+/* Master , SLAVEs 1&2 PIC Interrupt Mode Register Bit Definitions */
+
+#define CH7_INT_MODE 0x80 /* PIC Channel 7 Interrupt Mode 0-edge 1-level */
+#define CH6_INT_MODE 0x40 /* PIC Channel 6 Interrupt Mode 0-edge 1-level */
+#define CH5_INT_MODE 0x20 /* PIC Channel 5 Interrupt Mode 0-edge 1-level */
+#define CH4_INT_MODE 0x10 /* PIC Channel 4 Interrupt Mode 0-edge 1-level */
+#define CH3_INT_MODE 0x08 /* PIC Channel 3 Interrupt Mode 0-edge 1-level */
+#define CH2_INT_MODE 0x04 /* PIC Channel 2 Interrupt Mode 0-edge 1-level */
+#define CH1_INT_MODE 0x02 /* PIC Channel 1 Interrupt Mode 0-edge 1-level */
+#define CH0_INT_MODE 0x01 /* PIC Channel 0 Interrupt Mode 0-edge 1-level */
+
+/* Software Interrupt 16-1 Control Register Bit Definitions */
+
+#define SW_P16_TRIG 0x8000 /* Directly Trigger Priority Level P16 0-don't assert int, 1-assert int*/
+#define SW_P15_TRIG 0x4000 /* Directly Trigger Priority Level P15 */
+#define SW_P14_TRIG 0x2000 /* Directly Trigger Priority Level P14 */
+#define SW_P13_TRIG 0x1000 /* Directly Trigger Priority Level P13 */
+#define SW_P12_TRIG 0x0800 /* Directly Trigger Priority Level P12 */
+#define SW_P11_TRIG 0x0400 /* Directly Trigger Priority Level P11 */
+#define SW_P10_TRIG 0x0200 /* Directly Trigger Priority Level P10 */
+#define SW_P9_TRIG 0x0100 /* Directly Trigger Priority Level P9 */
+#define SW_P8_TRIG 0x0080 /* Directly Trigger Priority Level P8 */
+#define SW_P7_TRIG 0x0040 /* Directly Trigger Priority Level P7 */
+#define SW_P6_TRIG 0x0020 /* Directly Trigger Priority Level P6 */
+#define SW_P5_TRIG 0x0010 /* Directly Trigger Priority Level P5 */
+#define SW_P4_TRIG 0x0008 /* Directly Trigger Priority Level P4 */
+#define SW_P3_TRIG 0x0004 /* Directly Trigger Priority Level P3 */
+#define SW_P2_TRIG 0x0002 /* Directly Trigger Priority Level P2 */
+#define SW_P1_TRIG 0x0001 /* Directly Trigger Priority Level P1 */
+
+/* Software Interrupt 22-17/NMI Control Register Bit Defintions */
+
+#define NMI_TRIG 0x0040 /* Software NMI Source */
+#define SW_P22_TRIG 0x0020 /* Directly Trigger Priority Level P22 */
+#define SW_P21_TRIG 0x0010 /* Directly Trigger Priority Level P21 */
+#define SW_P20_TRIG 0x0008 /* Directly Trigger Priority Level P20 */
+#define SW_P19_TRIG 0x0004 /* Directly Trigger Priority Level P19 */
+#define SW_P18_TRIG 0x0002 /* Directly Trigger Priority Level P18 */
+#define SW_P17_TRIG 0x0001 /* Directly Trigger Priority Level P17 */
+
+/* Interrupt Pin Polarity Register Bit Definitions */
+
+#define INTD_POL 0x8000 /* PCI Interrupt Request /INTD Polarity */
+#define INTC_POL 0x4000 /* PCI Interrupt Request /INTC Polarity */
+#define INTB_POL 0x2000 /* PCI Interrupt Request /INTB Polarity */
+#define INTA_POL 0x1000 /* PCI Interrupt Request /INTA Polarity */
+
+#define GPINT10_POL 0x0400 /* General-Purpose Interrupt Request GPIRQ10 Polarity 0 - high to low, 1 low to high */
+#define GPINT9_POL 0x0200 /* General-Purpose Interrupt Request GPIRQ9 Polarity 0 - high to low, 1 low to high */
+#define GPINT8_POL 0x0100 /* General-Purpose Interrupt Request GPIRQ8 Polarity 0 - high to low, 1 low to high */
+#define GPINT7_POL 0x0080 /* General-Purpose Interrupt Request GPIRQ7 Polarity 0 - high to low, 1 low to high */
+#define GPINT6_POL 0x0040 /* General-Purpose Interrupt Request GPIRQ6 Polarity 0 - high to low, 1 low to high */
+#define GPINT5_POL 0x0020 /* General-Purpose Interrupt Request GPIRQ5 Polarity 0 - high to low, 1 low to high */
+#define GPINT4_POL 0x0010 /* General-Purpose Interrupt Request GPIRQ4 Polarity 0 - high to low, 1 low to high */
+#define GPINT3_POL 0x0008 /* General-Purpose Interrupt Request GPIRQ3 Polarity 0 - high to low, 1 low to high */
+#define GPINT2_POL 0x0004 /* General-Purpose Interrupt Request GPIRQ2 Polarity 0 - high to low, 1 low to high */
+#define GPINT1_POL 0x0002 /* General-Purpose Interrupt Request GPIRQ1 Polarity 0 - high to low, 1 low to high */
+#define GPINT0_POL 0x0001 /* General-Purpose Interrupt Request GPIRQ0 Polarity 0 - high to low, 1 low to high */
+
+/* PCI Host Bridge Interrupt Mapping Register Bit Definitions */
+
+#define PCI_NMI_ENB 0x0010 /* PCI Host Bridge NMI Enable */
+
+#define PCI_IRQ_MAP_P0 0x0000 /* PCI Host Bridge Interrupt Mapping: Disable PCI interrupt from reaching PIC */
+#define PCI_IRQ_MAP_P1 0x0001 /* PCI Host Bridge Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/
+#define PCI_IRQ_MAP_P2 0x0002 /* PCI Host Bridge Interrupt Mapping: Priority P2 (Master PIC IR1)*/
+#define PCI_IRQ_MAP_P3 0x0003 /* PCI Host Bridge Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/
+#define PCI_IRQ_MAP_P4 0x0004 /* PCI Host Bridge Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/
+#define PCI_IRQ_MAP_P5 0x0005 /* PCI Host Bridge Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/
+#define PCI_IRQ_MAP_P6 0x0006 /* PCI Host Bridge Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/
+#define PCI_IRQ_MAP_P7 0x0007 /* PCI Host Bridge Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/
+#define PCI_IRQ_MAP_P8 0x0008 /* PCI Host Bridge Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/
+#define PCI_IRQ_MAP_P9 0x0009 /* PCI Host Bridge Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/
+#define PCI_IRQ_MAP_P10 0x000a /* PCI Host Bridge Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/
+#define PCI_IRQ_MAP_P11 0x000b /* PCI Host Bridge Interrupt Mapping: Priority P11 (Master PIC IR3)*/
+#define PCI_IRQ_MAP_P12 0x000c /* PCI Host Bridge Interrupt Mapping: Priority P12 (Master PIC IR4)*/
+#define PCI_IRQ_MAP_P13 0x000d /* PCI Host Bridge Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/
+#define PCI_IRQ_MAP_P14 0x000e /* PCI Host Bridge Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/
+#define PCI_IRQ_MAP_P15 0x000f /* PCI Host Bridge Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/
+#define PCI_IRQ_MAP_P16 0x0010 /* PCI Host Bridge Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/
+#define PCI_IRQ_MAP_P17 0x0011 /* PCI Host Bridge Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/
+#define PCI_IRQ_MAP_P18 0x0012 /* PCI Host Bridge Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/
+#define PCI_IRQ_MAP_P19 0x0013 /* PCI Host Bridge Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/
+#define PCI_IRQ_MAP_P20 0x0014 /* PCI Host Bridge Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/
+#define PCI_IRQ_MAP_P21 0x0015 /* PCI Host Bridge Interrupt Mapping: Priority P21 (Master PIC IR6)*/
+#define PCI_IRQ_MAP_P22 0x0016 /* PCI Host Bridge Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */
+#define PCI_IRQ_MAP_DA 0x0017 /* PCI Host Bridge Interrupt Mapping: disable internal-interrupt from reaching PIC*/
+#define PCI_IRQ_MAP_NMI 0x001F /* PCI Host Bridge Interrupt Mapping: NMI Source*/
+
+/* ECC Interrupt Mapping Register Bit Definitions */
+
+#define ECC_NMI_ENB 0x0100 /* ECC NMI Enable */
+
+#define ECC_IRQ_MAP_P0 0x0000 /* SDRAM ECC Interrupt Mapping: Disable PCI interrupt from reaching PIC */
+#define ECC_IRQ_MAP_P1 0x0001 /* SDRAM ECC Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/
+#define ECC_IRQ_MAP_P2 0x0002 /* SDRAM ECC Interrupt Mapping: Priority P2 (Master PIC IR1)*/
+#define ECC_IRQ_MAP_P3 0x0003 /* SDRAM ECC Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/
+#define ECC_IRQ_MAP_P4 0x0004 /* SDRAM ECC Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/
+#define ECC_IRQ_MAP_P5 0x0005 /* SDRAM ECC Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/
+#define ECC_IRQ_MAP_P6 0x0006 /* SDRAM ECC Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/
+#define ECC_IRQ_MAP_P7 0x0007 /* SDRAM ECC Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/
+#define ECC_IRQ_MAP_P8 0x0008 /* SDRAM ECC Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/
+#define ECC_IRQ_MAP_P9 0x0009 /* SDRAM ECC Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/
+#define ECC_IRQ_MAP_P10 0x000a /* SDRAM ECC Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/
+#define ECC_IRQ_MAP_P11 0x000b /* SDRAM ECC Interrupt Mapping: Priority P11 (Master PIC IR3)*/
+#define ECC_IRQ_MAP_P12 0x000c /* SDRAM ECC Interrupt Mapping: Priority P12 (Master PIC IR4)*/
+#define ECC_IRQ_MAP_P13 0x000d /* SDRAM ECC Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/
+#define ECC_IRQ_MAP_P14 0x000e /* SDRAM ECC Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/
+#define ECC_IRQ_MAP_P15 0x000f /* SDRAM ECC Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/
+#define ECC_IRQ_MAP_P16 0x0010 /* SDRAM ECC Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/
+#define ECC_IRQ_MAP_P17 0x0011 /* SDRAM ECC Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/
+#define ECC_IRQ_MAP_P18 0x0012 /* SDRAM ECC Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/
+#define ECC_IRQ_MAP_P19 0x0013 /* SDRAM ECC Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/
+#define ECC_IRQ_MAP_P20 0x0014 /* SDRAM ECC Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/
+#define ECC_IRQ_MAP_P21 0x0015 /* SDRAM ECC Interrupt Mapping: Priority P21 (Master PIC IR6)*/
+#define ECC_IRQ_MAP_P22 0x0016 /* SDRAM ECC Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */
+#define ECC_IRQ_MAP_DA 0x0017 /* SDRAM ECC Interrupt Mapping: disable internal-interrupt from reaching PIC*/
+
+/* Interrupt Mappings for GP TIMER 0
+GP TImer 1
+GP Timer 2
+PIT0
+PIT1
+PIT2
+UART 1
+UART 2
+PCI A
+PCI B
+PCI C
+PCI D
+DMA Buffer Chaining
+SSI
+WDT
+RTC
+Write-Protection Violation
+AMDebug JTAG RX/TX
+Floating Point Error
+GPIRQ0 - QPIRQ10
+*/
+
+#define INT_MAP_P0 0x0000 /* Interrupt Mapping: Disable PCI interrupt from reaching PIC */
+#define INT_MAP_P1 0x0001 /* Interrupt Mapping: Priority P1 (Master PIC IR0) (highest priority)*/
+#define INT_MAP_P2 0x0002 /* Interrupt Mapping: Priority P2 (Master PIC IR1)*/
+#define INT_MAP_P3 0x0003 /* Interrupt Mapping: Priority P3 (Slave PIC IR0/Master PIC IR2)*/
+#define INT_MAP_P4 0x0004 /* Interrupt Mapping: Priority P4 (Slave 1 PIC IR1)*/
+#define INT_MAP_P5 0x0005 /* Interrupt Mapping: Priority P5 (Slave 1 PIC IR2)*/
+#define INT_MAP_P6 0x0006 /* Interrupt Mapping: Priority P6 (Slave 1 PIC IR3)*/
+#define INT_MAP_P7 0x0007 /* Interrupt Mapping: Priority P7 (Slave 1 PIC IR4)*/
+#define INT_MAP_P8 0x0008 /* Interrupt Mapping: Priority P8 (Slave 1 PIC IR5)*/
+#define INT_MAP_P9 0x0009 /* Interrupt Mapping: Priority P9 (Slave 1 PIC IR6)*/
+#define INT_MAP_P10 0x000a /* Interrupt Mapping: Priority P10 (Slave 1 PIC IR7)*/
+#define INT_MAP_P11 0x000b /* Interrupt Mapping: Priority P11 (Master PIC IR3)*/
+#define INT_MAP_P12 0x000c /* Interrupt Mapping: Priority P12 (Master PIC IR4)*/
+#define INT_MAP_P13 0x000d /* Interrupt Mapping: Priority P13 (Slave 2 PIC IR0/Master PIC IR5)*/
+#define INT_MAP_P14 0x000e /* Interrupt Mapping: Priority P14 (Slave 2 PIC IR1)*/
+#define INT_MAP_P15 0x000f /* Interrupt Mapping: Priority P15 (Slave 2 PIC IR2)*/
+#define INT_MAP_P16 0x0010 /* Interrupt Mapping: Priority P16 (Slave 2 PIC IR3)*/
+#define INT_MAP_P17 0x0011 /* Interrupt Mapping: Priority P17 (Slave 2 PIC IR4)*/
+#define INT_MAP_P18 0x0012 /* Interrupt Mapping: Priority P18 (Slave 2 PIC IR5)*/
+#define INT_MAP_P19 0x0013 /* Interrupt Mapping: Priority P19 (Slave 2 PIC IR6)*/
+#define INT_MAP_P20 0x0014 /* Interrupt Mapping: Priority P20 (Slave 2 PIC IR7)*/
+#define INT_MAP_P21 0x0015 /* Interrupt Mapping: Priority P21 (Master PIC IR6)*/
+#define INT_MAP_P22 0x0016 /* Interrupt Mapping: Priority P22 (Master PIC IR7)(lowest priority) */
+#define INT_MAP_DA 0x0017 /* Interrupt Mapping: disable internal-interrupt from reaching PIC*/
+#define INT_MAP_NMI 0x001F /* Interrupt Mapping: NMI Source*/
+
+/* Master, SLAVE 1,2 PIC Interrupt Request Register Bit Definitions */
+
+#define IR7 0x80 /* Interrupt Request 7 */
+#define IR6 0x40 /* Interrupt Request 6 */
+#define IR5 0x20 /* Interrupt Request 5 */
+#define IR4 0x10 /* Interrupt Request 4 */
+#define IR3 0x08 /* Interrupt Request 3 */
+#define IR2 0x04 /* Interrupt Request 2 */
+#define IR1 0x02 /* Interrupt Request 1 */
+#define IR0 0x01 /* Interrupt Request 0 */
+
+/* Master, SLAVE 1,2 PIC In-Service Register Bit Definitions */
+
+#define IS7 0x80 /* Interrupt Request 7 In-Service */
+#define IS6 0x40 /* Interrupt Request 6 In-Service */
+#define IS5 0x20 /* Interrupt Request 5 In-Service */
+#define IS4 0x10 /* Interrupt Request 4 In-Service */
+#define IS3 0x08 /* Interrupt Request 3 In-Service */
+#define IS2 0x04 /* Interrupt Request 2 In-Service */
+#define IS1 0x02 /* Interrupt Request 1 In-Service */
+#define IS0 0x01 /* Interrupt Request 0 In-Service */
+
+/* Master PIC Initilization Control Word 1 Register Bit Definitions */
+
+#define SLCT_ICW1 0x10 /* Select ICW1 */
+#define LTIM 0x08 /* Level-Triggered Interrupt Mode */
+#define ADI 0x04 /* Address Interval */
+#define SNGL 0x02 /* Single PIC */
+#define IC4 0x01 /* Initilization Control Word 4 */
+
+/* Master PIC Operation Control Word 2 Register Bit Definitions */
+
+#define R_SL_EOI_RAEOIC 0x00 /* Interrupt Request EOI and Priority Rotation Controls: Rotate in auto EOI mode (clear)*/
+#define R_SL_EOI_NEOI 0x20 /* Interrupt Request EOI and Priority Rotation Controls: Non-specific EOI */
+#define R_SL_EOI_NOP 0x40 /* Interrupt Request EOI and Priority Rotation Controls: NOP */
+#define R_SL_EOI_SEOI 0x60 /* Interrupt Request EOI and Priority Rotation Controls: Specific EOI */
+#define R_SL_EOI_RAEOIS 0x80 /* Interrupt Request EOI and Priority Rotation Controls: Rotate in auto EOI mode (set)*/
+#define R_SL_EOI_RONEOI 0xA0 /* Interrupt Request EOI and Priority Rotation Controls: Rotate on non-specific EOI command */
+#define R_SL_EOI_SPC 0xC0 /* Interrupt Request EOI and Priority Rotation Controls: Set Priority Command */
+#define R_SL_EOI_ROEOIC 0xE0 /* Interrupt Request EOI and Priority Rotation Controls: Rotate on specific EOI command */
+
+#define IS_OCW3 0x08 /* Access is OCW3 */
+
+#define LS_IR0 0x00 /* Specific EOI Level Select: IR0 */
+#define LS_IR1 0x01 /* Specific EOI Level Select: IR1 */
+#define LS_IR2 0x02 /* Specific EOI Level Select: IR2 */
+#define LS_IR3 0x03 /* Specific EOI Level Select: IR3 */
+#define LS_IR4 0x04 /* Specific EOI Level Select: IR4 */
+#define LS_IR5 0x05 /* Specific EOI Level Select: IR5 */
+#define LS_IR6 0x06 /* Specific EOI Level Select: IR6 */
+#define LS_IR7 0x07 /* Specific EOI Level Select: IR7 */
+
+/* Master PIC Operation Control Word 3 */
+
+#define ESMMSMM_NOP 0x00 /* Special Mask Mode: NOP */
+#define ESMMSMM_RSM 0x40 /* Special Mask Mode: Reset Special mask */
+#define ESMMSMM_SSM 0x60 /* Special Mask Mode: Set Special mask */
+
+#define P 0x04 /* PIC Poll Command */
+
+#define RRRIS_NC 0x00 /* Status Register Select: No change from last state */
+#define RRRIS_MPICIR 0x02 /* Status Register Select: Next Port 0020h read returns MPICIR register contents */
+#define RRRIS_MPICISR 0x03 /* Status Register Select: Next Port 0020h read returns MPICISR register contents */
+
+/* Master PIC Intialization Control Word 2 Register Masks */
+
+#define T7_T3 0xF8 /* Bits 7-3 of Base Interrupt Vector Number for this PIC */
+#define A10_A8 0x07 /* A10-A8 of Interrupt Vector */
+
+/* Master PIC Intilization Control Word 3 Register Bit Definitions */
+
+#define S7 0x80 /* Channel 7 Slave Cascade Select */
+#define S6 0x40 /* Channel 6 Slave Cascade Select */
+#define S5 0x20 /* Channel 5 Slave Cascade Select */
+#define S4 0x10 /* Channel 4 Slave Cascade Select */
+#define S3 0x08 /* Channel 3 Slave Cascade Select */
+#define S2 0x04 /* Channel 2 Slave Cascade Select */
+#define S1 0x02 /* Channel 1 Slave Cascade Select */
+#define S0 0x01 /* Channel 0 Slave Cascade Select */
+
+/* Master PIC Initilization Control Word 4 Register Bit Definitions */
+
+#define SFNM 0x10 /* Special Fully Nested Mode Enable */
+#define BUFMS_NBM 0x00 /* Buffered Mode and Master/Slave Select: Non-buffered mode */
+#define BUFMS_BMS 0x08 /* Buffered Mode and Master/Slave Select: Buffered Mode/slave */
+#define BUFMS_BMM 0x0C /* Buffered Mode and Master/Slave Select: Buffered mode/master */
+
+#define AEOI 0x02 /* Automatic EOI Mode */
+#define PM 0x01 /* Microprocessor Mode */
+
+/* Master, SLAVE 1,2 PIC Interrupt Mask Register Bit Definitions */
+
+#define IM7 0x80 /* IR7 Mask */
+#define IM6 0x40 /* IR6 Mask */
+#define IM5 0x20 /* IR5 Mask */
+#define IM4 0x10 /* IR4 Mask */
+#define IM3 0x08 /* IR3 Mask */
+#define IM2 0x04 /* IR2 Mask */
+#define IM1 0x02 /* IR1 Mask */
+#define IM0 0x01 /* IR0 Mask */
+
+/* other SLAVE1 and SLAVE2 PIC definitions have already been previously defined
+ just use the name of the bit as specified in the Register set manual */
+
+/* Slave 1 PIC Initilization Control Word 3 Register Masks */
+
+#define ID2_ID0 0x07 /* Slave 1 PIC ID 2-0 */
+
+/**********************************************
+* Reset Generation Registers *
+**********************************************/
+
+/* MMCR Registers */
+
+#define OFFS_SYSINFO 0x0D70 /* System Board Information Register */
+#define OFFS_RESCFG 0x0D72 /* Reset Configuration Register */
+#define OFFS_RESSTA 0x0D74 /* Reset Status Register */
+
+#define SYSINFO (MMCR + OFFS_SYSINFO) /* System Board Information Register */
+#define RESCFG (MMCR + OFFS_RESCFG) /* Reset Configuration Register */
+#define RESSTA (MMCR + OFFS_RESSTA) /* Reset Status Register */
+
+/* I/O Mapped Registers */
+
+#define SCPDATA 0x60 /* SCP DATA Port */
+#define SCPCMD 0x64 /* SCP Command Port */
+#define SYSCTLA 0x92 /* System Control Port A */
+#define FPUERRCLR 0xF0 /* FPU Error Interrupt Clear */
+
+/*
+Reset Generation Register Bit Definitions
+*/
+
+/* System Board Information Register Masks */
+
+#define RST_ID 0xFF /* Reset Latched Input Data */
+
+/* Reset Configuration Register Bit Definitions */
+
+#define ICE_ON_RST 0x08 /* Enter AMDebug Mode on Next Reset */
+#define PRG_RST_ENB 0x04 /* Programmable Reset Enable */
+#define GP_RST 0x02 /* Software GP Bus Reset */
+#define SYS_RST 0x01 /* Software System Reset */
+
+/* Reset Status Register Bit Definitions */
+
+#define SCP_RST_DET 0x40 /* SCP Reset Detect */
+#define ICE_HRST_DET 0x20 /* AMDebug Utiliity Hard Reset Detect */
+#define ICE_SRST_DET 0x10 /* AMDebug Utility Sytem Reset Detect */
+#define WDT_RST_DET 0x08 /* WDT Reset Detect */
+#define SD_RST_DET 0x04 /* CPU Shutdown Reset Detect */
+#define PRGRST_DET 0x02 /* PRGRESET Detect */
+#define PWRGOOD_DET 0x01 /* POWERGOOD Reset Detect */
+
+/* SCP Data Port Register Masks */
+
+#define SCP_DATA 0xFF /* System Control Processor Data */
+
+/* SCP Data Port Register Bit Definitions */
+
+#define A20_GATE 0x02 /* A20 Gate Data */
+#define CPU_RST 0x01 /* CPU Reset Control */
+
+/* SCP Command Port Register Masks */
+
+#define SCP_CMD 0xFF /* SCP Command */
+
+/* System Control Port A Register Bit Definitions */
+
+#define A20G_CTL 0x02 /* A20 Gate Control */
+/* CPU_RST - Alternate CPU Core Reset Control, already defined */
+
+/* Floating Point Error Interrupt Clear Register Mask */
+
+#define FPUERR_RST 0xFF /* Clear FPU Error Interrupt Request */
+
+/**********************************
+* GP Bus DMA Controller Registers *
+**********************************/
+
+/* GP-DMA MMCR Registers */
+
+#define OFFS_GPDMACTL 0x0D80 /* GP-DMa Control Register */
+#define OFFS_GPDMAMMIO 0x0D81 /* GP-DMA Memory-Mapped I/O Register */
+#define OFFS_GPDMAEXTCHMAPA 0x0D82 /* GP-DMA Resource Channel Map A */
+#define OFFS_GPDMAEXTCHMAPB 0x0D84 /* GP-DMA Resource Channel Map B */
+#define OFFS_GPDMAEXTPG0 0x0D86 /* GP-DMA Channel 0 Extended Page */
+#define OFFS_GPDMAEXTPG1 0x0D87 /* GP-DMA Channel 1 Extended Page */
+#define OFFS_GPDMAEXTPG2 0x0D88 /* GP-DMA Channel 2 Extended Page */
+#define OFFS_GPDMAEXTPG3 0x0D89 /* GP-DMA Channel 3 Extended Page */
+#define OFFS_GPDMAEXTPG5 0x0D8a /* GP-DMA Channel 5 Extended Page */
+#define OFFS_GPDMAEXTPG6 0x0D8b /* GP-DMA Channel 6 Extended Page */
+#define OFFS_GPDMAEXTPG7 0x0D8c /* GP-DMA Channel 7 Extended Page */
+#define OFFS_GPDMAEXTTC3 0x0D90 /* GP-DMA Channel 3 Extender Transfer count */
+#define OFFS_GPDMAEXTTC5 0x0D91 /* GP-DMA Channel 5 Extender Transfer count */
+#define OFFS_GPDMAEXTTC6 0x0D92 /* GP-DMA Channel 6 Extender Transfer count */
+#define OFFS_GPDMAEXTTC7 0x0D93 /* GP-DMA Channel 7 Extender Transfer count */
+#define OFFS_GPDMABCCTL 0x0D98 /* Buffer Chaining Control */
+#define OFFS_GPDMABCSTA 0x0D99 /* Buffer Chaining Status */
+#define OFFS_GPDMABSINTENB 0x0D9A /* Buffer Chaining Interrupt Enable */
+#define OFFS_GPDMABCVAL 0x0D9B /* Buffer Chaining Valid */
+#define OFFS_GPDMANXTADDL3 0x0DA0 /* GP-DMA Channel 3 Next Address Low */
+#define OFFS_GPDMANXTADDH3 0x0DA2 /* GP-DMA Channel 3 Next Address High */
+#define OFFS_GPDMANXTADDL5 0x0DA4 /* GP-DMA Channel 5 Next Address Low */
+#define OFFS_GPDMANXTADDH5 0x0DA6 /* GP-DMA Channel 5 Next Address High */
+#define OFFS_GPDMANXTADDL6 0x0DA8 /* GP-DMA Channel 6 Next Address Low */
+#define OFFS_GPDMANXTADDH6 0x0DAA /* GP-DMA Channel 6 Next Address High */
+#define OFFS_GPDMANXTADDL7 0x0DAC /* GP-DMA Channel 7 Next Address Low */
+#define OFFS_GPDMANXTADDH7 0x0DAE /* GP-DMA Channel 7 Next Address High */
+#define OFFS_GPDMANXTTCL3 0x0DB0 /* GP-DMA Channel 3 Next Transfer Count Low */
+#define OFFS_GPDMANXTTCH3 0x0DB2 /* GP-DMA Channel 3 Next Transfer Count High */
+#define OFFS_GPDMANXTTCL5 0x0DB4 /* GP-DMA Channel 5 Next Transfer Count Low */
+#define OFFS_GPDMANXTTCH5 0x0DB6 /* GP-DMA Channel 5 Next Transfer Count High */
+#define OFFS_GPDMANXTTCL6 0x0DB8 /* GP-DMA Channel 6 Next Transfer Count Low */
+#define OFFS_GPDMANXTTCH6 0x0DBA /* GP-DMA Channel 6 Next Transfer Count High */
+#define OFFS_GPDMANXTTCL7 0x0DBC /* GP-DMA Channel 7 Next Transfer Count Low */
+#define OFFS_GPDMANXTTCH7 0x0DBE /* GP-DMA Channel 7 Next Transfer Count High */
+
+#define GPDMACTL (MMCR + OFFS_GPDMACTL) /* GP-DMa Control Register */
+#define GPDMAMMIO (MMCR + OFFS_GPDMAMMIO) /* GP-DMA Memory-Mapped I/O Register */
+#define GPDMAEXTCHMAPA (MMCR + OFFS_GPDMAEXTCHMAPA)/* GP-DMA Resource Channel Map A */
+#define GPDMAEXTCHMAPB (MMCR + OFFS_GPDMAEXTCHMAPB)/* GP-DMA Resource Channel Map B */
+#define GPDMAEXTPG0 (MMCR + OFFS_GPDMAEXTPG0) /* GP-DMA Channel 0 Extended Page */
+#define GPDMAEXTPG1 (MMCR + OFFS_GPDMAEXTPG1) /* GP-DMA Channel 1 Extended Page */
+#define GPDMAEXTPG2 (MMCR + OFFS_GPDMAEXTPG2) /* GP-DMA Channel 2 Extended Page */
+#define GPDMAEXTPG3 (MMCR + OFFS_GPDMAEXTPG3) /* GP-DMA Channel 3 Extended Page */
+#define GPDMAEXTPG5 (MMCR + OFFS_GPDMAEXTPG5) /* GP-DMA Channel 5 Extended Page */
+#define GPDMAEXTPG6 (MMCR + OFFS_GPDMAEXTPG6) /* GP-DMA Channel 6 Extended Page */
+#define GPDMAEXTPG7 (MMCR + OFFS_GPDMAEXTPG7) /* GP-DMA Channel 7 Extended Page */
+#define GPDMAEXTTC3 (MMCR + OFFS_GPDMAEXTTC3) /* GP-DMA Channel 3 Extender Transfer count */
+#define GPDMAEXTTC5 (MMCR + OFFS_GPDMAEXTTC5) /* GP-DMA Channel 5 Extender Transfer count */
+#define GPDMAEXTTC6 (MMCR + OFFS_GPDMAEXTTC6) /* GP-DMA Channel 6 Extender Transfer count */
+#define GPDMAEXTTC7 (MMCR + OFFS_GPDMAEXTTC7) /* GP-DMA Channel 7 Extender Transfer count */
+#define GPDMABCCTL (MMCR + OFFS_GPDMABCCTL) /* Buffer Chaining Control */
+#define GPDMABCSTA (MMCR + OFFS_GPDMABCSTA) /* Buffer Chaining Status */
+#define GPDMABSINTENB (MMCR + OFFS_GPDMABSINTENB) /* Buffer Chaining Interrupt Enable */
+#define GPDMABCVAL (MMCR + OFFS_GPDMABCVAL) /* Buffer Chaining Valid */
+#define GPDMANXTADDL3 (MMCR + OFFS_GPDMANXTADDL3) /* GP-DMA Channel 3 Next Address Low */
+#define GPDMANXTADDH3 (MMCR + OFFS_GPDMANXTADDH3) /* GP-DMA Channel 3 Next Address High */
+#define GPDMANXTADDL5 (MMCR + OFFS_GPDMANXTADDL5) /* GP-DMA Channel 5 Next Address Low */
+#define GPDMANXTADDH5 (MMCR + OFFS_GPDMANXTADDH5) /* GP-DMA Channel 5 Next Address High */
+#define GPDMANXTADDL6 (MMCR + OFFS_GPDMANXTADDL6) /* GP-DMA Channel 6 Next Address Low */
+#define GPDMANXTADDH6 (MMCR + OFFS_GPDMANXTADDH6) /* GP-DMA Channel 6 Next Address High */
+#define GPDMANXTADDL7 (MMCR + OFFS_GPDMANXTADDL7) /* GP-DMA Channel 7 Next Address Low */
+#define GPDMANXTADDH7 (MMCR + OFFS_GPDMANXTADDH7) /* GP-DMA Channel 7 Next Address High */
+#define GPDMANXTTCL3 (MMCR + OFFS_GPDMANXTTCL3) /* GP-DMA Channel 3 Next Transfer Count Low */
+#define GPDMANXTTCH3 (MMCR + OFFS_GPDMANXTTCH3) /* GP-DMA Channel 3 Next Transfer Count High */
+#define GPDMANXTTCL5 (MMCR + OFFS_GPDMANXTTCL5) /* GP-DMA Channel 5 Next Transfer Count Low */
+#define GPDMANXTTCH5 (MMCR + OFFS_GPDMANXTTCH5) /* GP-DMA Channel 5 Next Transfer Count High */
+#define GPDMANXTTCL6 (MMCR + OFFS_GPDMANXTTCL6) /* GP-DMA Channel 6 Next Transfer Count Low */
+#define GPDMANXTTCH6 (MMCR + OFFS_GPDMANXTTCH6) /* GP-DMA Channel 6 Next Transfer Count High */
+#define GPDMANXTTCL7 (MMCR + OFFS_GPDMANXTTCL7) /* GP-DMA Channel 7 Next Transfer Count Low */
+#define GPDMANXTTCH7 (MMCR + OFFS_GPDMANXTTCH7) /* GP-DMA Channel 7 Next Transfer Count High */
+
+/* GP-DMA Direct-Mapped Registers */
+
+#define GPDMA0MAR 0x0000 /* Slave DMA Channel 0 Memory Address */
+#define GPDMA0TC 0x0001 /* Slave DMA Channel 0 Transfer Count */
+#define GPDMA1MAR 0x0002 /* Slave DMA Channel 1 Memory Address */
+#define GPDMA1TC 0x0003 /* Slave DMA Channel 1 Transfer Count */
+#define GPDMA2MAR 0x0004 /* Slave DMA Channel 2 Memory Address */
+#define GPDMA2TC 0x0005 /* Slave DMA Channel 2 Transfer Count */
+#define GPDMA3MAR 0x0006 /* Slave DMA Channel 3 Memory Address */
+#define GPDMA3TC 0x0007 /* Slave DMA Channel 3 Transfer Count */
+#define SLDMASTA 0x0008 /* Slave DMA Channel 0-3 Status */
+#define SLDMACTL 0x0008 /* Slave DMA Channel 0-3 Control */
+#define SLDMASWREQ 0x0009 /* Slave Software DRQ(n) Request */
+#define SLDMAMSK 0x000A /* Slave DMA Channel 0-3 Mask */
+#define SLDMAMODE 0x000B /* Slave DMA Channel 0-3 Mode */
+#define SLDMACBP 0x000C /* Slave DMA Clear Byte Pointer */
+#define SLDMARST 0x000D /* Slave DMA Controller Reset */
+#define SLDMATMP 0x000D /* Slave DMA Controller Temporary */
+#define SLDMAMSKRST 0x000E /* Slave DMA Mask Reset */
+#define SLDMAGENMSK 0x000F /* Slave DMA General Mask */
+#define GPDMAGR0 0x0080 /* General 0 */
+#define GPDMA2PG 0x0081 /* Slave DMA Channel 2 Page */
+#define GPDMA3PG 0x0082 /* Slave DMA Channel 3 Page */
+#define GPDMA1PG 0x0083 /* Slave DMA Channel 1 Page */
+#define GPDMAGR1 0x0084 /* General 1 */
+#define GPDMAGR2 0x0085 /* General 2 */
+#define GPDMAGR3 0x0086 /* General 3 */
+#define GPDMA0PG 0x0087 /* Slave DMA Channel 0 Page */
+#define GPDMAGR4 0x0088 /* General 4 */
+#define GPDMA6PG 0x0089 /* Master DMA Channel 6 Page */
+#define GPDMA7PG 0x008a /* Master DMA Channel 7 Page */
+#define GPDMA5PG 0x008b /* Master DMA Channel 5 Page */
+#define GPDMAGR5 0x008c /* General 5 */
+#define GPDMAGR6 0x008d /* General 6 */
+#define GPDMAGR7 0x008e /* General 7 */
+#define GPDMAGR8 0x008f /* General 8 */
+#define GPDMA4MAR 0x00c0 /* Master DMA Channel 4 Memory Address */
+#define GPDMA4TC 0x00c2 /* Master DMA Channel 4 Transfer Count */
+#define GPDMA5MAR 0x00c4 /* Master DMA Channel 5 Memory Address */
+#define GPDMA5TC 0x00c6 /* Master DMA Channel 5 Transfer Count */
+#define GPDMA6MAR 0x00c8 /* Master DMA Channel 6 Memory Address */
+#define GPDMA6TC 0x00cc /* Master DMA Channel 6 Transfer Count */
+#define GPDMA7MAR 0x00ce /* Master DMA Channel 7 Memory Address */
+#define GPDMA7TC 0x00c2 /* Master DMA Channel 7 Transfer Count */
+#define MSTDMASTA 0x00d0 /* Master DMA Channel 4-7 Status */
+#define MSTDMACTL 0x00d0 /* Master DMA Channel 4-7 Control */
+#define MSTDMASWREQ 0x00d2 /* Master Software DRQ(n) Request */
+#define MSTDMAMSK 0x00d4 /* Master DMA Channel 4-7 Mask */
+#define MSTDMAMODE 0x00d6 /* Master DMA Channel 4-7 mode */
+#define MSTDMACBP 0x00d8 /* Master DMA Clear Byte Pointer */
+#define MSTDMARST 0x00da /* Master DMA Controller Reset */
+#define MSTDMATMP 0x00da /* Master DMA Temporary */
+#define MSTDMAMSKRST 0x00dc /* Master DMA Mask Reset */
+#define MSTDMAGENMSK 0x00de /* Master DMA General Mask */
+
+/*
+GP Bus DMA Controller Register Bit Definitions
+*/
+
+/* GP-DMA Control Register Bit Definitions */
+
+#define CH7_ALT_SIZE 0x80 /* Alternate Size for Channel 7 */
+#define CH6_ALT_SIZE 0x40 /* Alternate Size for Channel 6 */
+#define CH5_ALT_SIZE 0x20 /* Alternate Size for Channel 5 */
+#define CH3_ALT_SIZE 0x10 /* Alternate Size for Channel 3 */
+
+#define CLK_MODE_4MHZ 0x00 /* Clock Mode: GP Bus Controller at 4Mhz */
+#define CLK_MODE_8MHZ 0x04 /* Clock Mode: GP Bus Controller at 8Mhz */
+#define CLK_MODE_16MHZ 0x08 /* Clock Mode: GP Bus Controller at 16Mhz */
+
+#define ENH_MODE_ENB 0x01 /* Enhanced Mode Enable */
+
+/* GP-DMA Memory-Mapped I/O Register Bit Definitions */
+
+#define DMA7_MMAP 0x80 /* Memory-Mapped Device for DMA Channel 7 */
+#define DMA6_MMAP 0x40 /* Memory-Mapped Device for DMA Channel 6 */
+#define DMA5_MMAP 0x20 /* Memory-Mapped Device for DMA Channel 5 */
+#define DMA3_MMAP 0x08 /* Memory-Mapped Device for DMA Channel 3 */
+#define DMA2_MMAP 0x04 /* Memory-Mapped Device for DMA Channel 2 */
+#define DMA1_MMAP 0x02 /* Memory-Mapped Device for DMA Channel 1 */
+#define DMA0_MMAP 0x01 /* Memory-Mapped Device for DMA Channel 0 */
+
+/* GP-DMA Resource Channel Map A Register Bit Definitions */
+
+#define GPDRQ3_CHSEL_0 0x0000 /* GPDRQ3 Channel Mapping: Channel 0 */
+#define GPDRQ3_CHSEL_1 0x1000 /* GPDRQ3 Channel Mapping: Channel 1 */
+#define GPDRQ3_CHSEL_2 0x2000 /* GPDRQ3 Channel Mapping: Channel 2 */
+#define GPDRQ3_CHSEL_3 0x3000 /* GPDRQ3 Channel Mapping: Channel 3 */
+#define GPDRQ3_CHSEL_5 0x5000 /* GPDRQ3 Channel Mapping: Channel 5 */
+#define GPDRQ3_CHSEL_6 0x6000 /* GPDRQ3 Channel Mapping: Channel 6 */
+#define GPDRQ3_CHSEL_7 0x7000 /* GPDRQ3 Channel Mapping: Channel 7 */
+
+#define GPDRQ2_CHSEL_0 0x0000 /* GPDRQ2 Channel Mapping: Channel 0 */
+#define GPDRQ2_CHSEL_1 0x0100 /* GPDRQ2 Channel Mapping: Channel 1 */
+#define GPDRQ2_CHSEL_2 0x0200 /* GPDRQ2 Channel Mapping: Channel 2 */
+#define GPDRQ2_CHSEL_3 0x0300 /* GPDRQ2 Channel Mapping: Channel 3 */
+#define GPDRQ2_CHSEL_5 0x0500 /* GPDRQ2 Channel Mapping: Channel 5 */
+#define GPDRQ2_CHSEL_6 0x0600 /* GPDRQ2 Channel Mapping: Channel 6 */
+#define GPDRQ2_CHSEL_7 0x0700 /* GPDRQ2 Channel Mapping: Channel 7 */
+
+#define GPDRQ1_CHSEL_0 0x0000 /* GPDRQ1 Channel Mapping: Channel 0 */
+#define GPDRQ1_CHSEL_1 0x0010 /* GPDRQ1 Channel Mapping: Channel 1 */
+#define GPDRQ1_CHSEL_2 0x0020 /* GPDRQ1 Channel Mapping: Channel 2 */
+#define GPDRQ1_CHSEL_3 0x0030 /* GPDRQ1 Channel Mapping: Channel 3 */
+#define GPDRQ1_CHSEL_5 0x0050 /* GPDRQ1 Channel Mapping: Channel 5 */
+#define GPDRQ1_CHSEL_6 0x0060 /* GPDRQ1 Channel Mapping: Channel 6 */
+#define GPDRQ1_CHSEL_7 0x0070 /* GPDRQ1 Channel Mapping: Channel 7 */
+
+#define GPDRQ0_CHSEL_0 0x0000 /* GPDRQ0 Channel Mapping: Channel 0 */
+#define GPDRQ0_CHSEL_1 0x0001 /* GPDRQ0 Channel Mapping: Channel 1 */
+#define GPDRQ0_CHSEL_2 0x0002 /* GPDRQ0 Channel Mapping: Channel 2 */
+#define GPDRQ0_CHSEL_3 0x0003 /* GPDRQ0 Channel Mapping: Channel 3 */
+#define GPDRQ0_CHSEL_5 0x0005 /* GPDRQ0 Channel Mapping: Channel 5 */
+#define GPDRQ0_CHSEL_6 0x0006 /* GPDRQ0 Channel Mapping: Channel 6 */
+#define GPDRQ0_CHSEL_7 0x0007 /* GPDRQ0 Channel Mapping: Channel 7 */
+
+/* GP-DMA Resource Channel Map B Register Bit Definitions */
+
+#define TXDRQ3_CHSEL_0 0x0000 /* TXDRQ3 Channel Mapping: Channel 0 */
+#define TXDRQ3_CHSEL_1 0x1000 /* TXDRQ3 Channel Mapping: Channel 1 */
+#define TXDRQ3_CHSEL_2 0x2000 /* TXDRQ3 Channel Mapping: Channel 2 */
+#define TXDRQ3_CHSEL_3 0x3000 /* TXDRQ3 Channel Mapping: Channel 3 */
+
+#define TXDRQ2_CHSEL_0 0x0000 /* TXDRQ2 Channel Mapping: Channel 0 */
+#define TXDRQ2_CHSEL_1 0x0100 /* TXDRQ2 Channel Mapping: Channel 1 */
+#define TXDRQ2_CHSEL_2 0x0200 /* TXDRQ2 Channel Mapping: Channel 2 */
+#define TXDRQ2_CHSEL_3 0x0300 /* TXDRQ2 Channel Mapping: Channel 3 */
+
+#define TXDRQ1_CHSEL_0 0x0000 /* TXDRQ1 Channel Mapping: Channel 0 */
+#define TXDRQ1_CHSEL_1 0x0010 /* TXDRQ1 Channel Mapping: Channel 1 */
+#define TXDRQ1_CHSEL_2 0x0020 /* TXDRQ1 Channel Mapping: Channel 2 */
+#define TXDRQ1_CHSEL_3 0x0030 /* TXDRQ1 Channel Mapping: Channel 3 */
+
+#define TXDRQ0_CHSEL_0 0x0000 /* TXDRQ0 Channel Mapping: Channel 0 */
+#define TXDRQ0_CHSEL_1 0x0001 /* TXDRQ0 Channel Mapping: Channel 1 */
+#define TXDRQ0_CHSEL_2 0x0002 /* TXDRQ0 Channel Mapping: Channel 2 */
+#define TXDRQ0_CHSEL_3 0x0003 /* TXDRQ0 Channel Mapping: Channel 3 */
+
+/* GP-DMA Channel 0 Extended Page Register Masks */
+
+#define DMA0ADR 0x0F /* GP-DMA Channel 0 Extended Page Address */
+
+/* GP-DMA Channel 1 Extended Page Register Masks */
+
+#define DMA1ADR 0x0F /* GP-DMA Channel 1 Extended Page Address */
+
+/* GP-DMA Channel 2 Extended Page Register Masks */
+
+#define DMA2ADR 0x0F /* GP-DMA Channel 2 Extended Page Address */
+
+/* GP-DMA Channel 3 Extended Page Register Masks */
+
+#define DMA3ADR 0x0F /* GP-DMA Channel 3 Extended Page Address */
+
+/* GP-DMA Channel 5 Extended Page Register Masks */
+
+#define DMA5ADR 0x0F /* GP-DMA Channel 5 Extended Page Address */
+
+/* GP-DMA Channel 6 Extended Page Register Masks */
+
+#define DMA6ADR 0x0F /* GP-DMA Channel 6 Extended Page Address */
+
+/* GP-DMA Channel 7 Extended Page Register Masks */
+
+#define DMA7ADR 0x0F /* GP-DMA Channel 7 Extended Page Address */
+
+/* GP-DMA Channel 3 Extended Transfer Count Register Masks */
+
+#define DMA3TC 0xFF /* GP-DMA Channel 3 Transfer Count Extension */
+
+/* GP-DMA Channel 5 Extended Transfer Count Register Masks */
+
+#define DMA5TC 0xFF /* GP-DMA Channel 5 Transfer Count Extension */
+
+/* GP-DMA Channel 6 Extended Transfer Count Register Masks */
+
+#define DMA6TC 0xFF /* GP-DMA Channel 6 Transfer Count Extension */
+
+/* GP-DMA Channel 7 Extended Transfer Count Register Masks */
+
+#define DMA7TC 0xFF /* GP-DMA Channel 7 Transfer Count Extension */
+
+/* Buffer Chaining Control Register Bit Definitions */
+
+#define CH7_BCHN_ENB 0x08 /* Buffer Chaining Enable for Channel 7 */
+#define CH6_BCHN_ENB 0x04 /* Buffer Chaining Enable for Channel 6 */
+#define CH5_BCHN_ENB 0x02 /* Buffer Chaining Enable for Channel 5 */
+#define CH3_BCHN_ENB 0x01 /* Buffer Chaining Enable for Channel 3 */
+
+/* Buffer Chaining Status Register Bit Definitions */
+
+#define CH7_EOB_STA 0x08 /* End of Current Buffer in Channel 7 */
+#define CH6_EOB_STA 0x04 /* End of Current Buffer in Channel 6 */
+#define CH5_EOB_STA 0x02 /* End of Current Buffer in Channel 5 */
+#define CH3_EOB_STA 0x01 /* End of Current Buffer in Channel 3 */
+
+/* Buffer Chaining Interrupt Enable Register Bit Definitions */
+
+#define CH7_INT_ENB 0x08 /* Interrupt Enable for Channel 7 */
+#define CH6_INT_ENB 0x04 /* Interrupt Enable for Channel 6 */
+#define CH5_INT_ENB 0x02 /* Interrupt Enable for Channel 5 */
+#define CH3_INT_ENB 0x01 /* Interrupt Enable for Channel 3 */
+
+/* Buffer Chaining Valid Register Bit Definitions */
+
+#define CH7_CBUF_VAL 0x08 /* Chaining Buffer Valid for Channel 7 */
+#define CH6_CBUF_VAL 0x04 /* Chaining Buffer Valid for Channel 6 */
+#define CH5_CBUF_VAL 0x02 /* Chaining Buffer Valid for Channel 5 */
+#define CH3_CBUF_VAL 0x01 /* Chaining Buffer Valid for Channel 3 */
+
+/* GP-DMA Channel 3 Next Address Low Register Masks */
+
+#define DMA3_NXT_ADRL 0xFFFF /* GP-DMA Channel 3 Next Address Low*/
+
+/* GP-DMA Channel 3 Next Address High Register Masks */
+
+#define DMA3_NXT_ADRH 0x0FFF /* GP-DMA Channel 3 Next Address High */
+
+/* GP-DMA Channel 5 Next Address Low Register Masks */
+
+#define DMA5_NXT_ADRL 0xFFFF /* GP-DMA Channel 5 Next Address Low */
+
+/* GP-DMA Channel 5 Next Address High Register Masks */
+
+#define DMA5_NXT_ADRH 0x0FFF /* GP-DMA Channel 5 Next Address High */
+
+/* GP-DMA Channel 6 Next Address Low Register Masks */
+
+#define DMA6_NXT_ADRL 0xFFFF /* GP-DMA Channel 6 Next Address Low */
+
+/* GP-DMA Channel 6 Next Address High Register Masks */
+
+#define DMA6_NXT_ADRH 0x0FFF /* GP-DMA Channel 6 Next Address High */
+
+/* GP-DMA Channel 7 Next Address Low Register Masks */
+
+#define DMA7_NXT_ADRL 0xFFFF /* GP-DMA Channel 7 Next Address Low */
+
+/* GP-DMA Channel 7 Next Address High Register Masks */
+
+#define DMA7_NXT_ADRH 0x0FFF /* GP-DMA Channel 7 Next Address High */
+
+
+/* GP-DMA Channel 3 Next Transfer Count Low Register Masks */
+
+#define DMA3_NXT_TCL 0xFFFF /* GP-DMA Channel 3 Next Transfer Count Low*/
+
+/* GP-DMA Channel 3 Next Transfer Count High Register Masks */
+
+#define DMA3_NXT_TCH 0xFF /* GP-DMA Channel 3 Next Transfer Count High*/
+
+/* GP-DMA Channel 5 Next Transfer Count Low Register Masks */
+
+#define DMA5_NXT_TCL 0xFFFF /* GP-DMA Channel 5 Next Transfer Count Low */
+
+/* GP-DMA Channel 5 Next Transfer Count High Register Masks */
+
+#define DMA5_NXT_TCH 0xFF /* GP-DMA Channel 5 Next Transfer Count High*/
+
+/* GP-DMA Channel 6 Next Transfer Count Low Register Masks */
+
+#define DMA6_NXT_TCL 0xFFFF /* GP-DMA Channel 6 Next Transfer Count Low */
+
+/* GP-DMA Channel 6 Next Transfer Count High Register Masks */
+
+#define DMA6_NXT_TCH 0xFF /* GP-DMA Channel 6 Next Transfer Count High*/
+
+/* GP-DMA Channel 7 Next Transfer Count Low Register Masks */
+
+#define DMA7_NXT_TCL 0xFFFF /* GP-DMA Channel 7 Next Transfer Count Low */
+
+/* GP-DMA Channel 7 Next Transfer Count High Register Masks */
+
+#define DMA7_NXT_TCH 0xFF /* GP-DMA Channel 7 Next Transfer Count High*/
+
+/* Slave DMA Channel 0 Memory Address Register Masks */
+
+#define DMA0MAR 0xFF /* Lower 16 Bits of DMA Channel 0 Memory Address */
+
+/* Slave DMA Channel 0 Transfer Count Register Masks */
+
+#define DMA0TC 0xFF /* DMA Channel 0 Transfer Count */
+
+/* Slave DMA Channel 1 Memory Address Register Masks */
+
+#define DMA1MAR 0xFF /* Lower 16 Bits of DMA Channel 1 Memory Address */
+
+/* Slave DMA Channel 1 Transfer Count Register Masks */
+
+#define DMA1TC 0xFF /* DMA Channel 1 Transfer Count */
+
+/* Slave DMA Channel 2 Memory Address Register Masks */
+
+#define DMA2MAR 0xFF /* Lower 16 Bits of DMA Channel 2 Memory Address */
+
+/* Slave DMA Channel 2 Transfer Count Register Masks */
+
+#define DMA2TC 0xFF /* DMA Channel 2 Transfer Count */
+
+/* Slave DMA Channel 3 Memory Address Register Masks */
+
+#define DMA3MAR 0xFF /* Lower 16 Bits of DMA Channel 3 Memory Address */
+
+/* Slave DMA Channel 3 Transfer Count Register Masks */
+
+#define DMA3TC 0xFF /* DMA Channel 3 Transfer Count */
+
+/* Slave DMA Channel 0-3 Status Register Bit Definitions */
+
+#define DMAR3 0x80 /* Channel 3 DMA Request */
+#define DMAR2 0x40 /* Channel 2 DMA Request */
+#define DMAR1 0x20 /* Channel 1 DMA Request */
+#define DMAR0 0x10 /* Channel 0 DMA Request */
+
+#define TC3 0x08 /* Channel 3 Terminal Count */
+#define TC2 0x04 /* Channel 2 Terminal Count */
+#define TC1 0x02 /* Channel 1 Terminal Count */
+#define TC0 0x01 /* Channel 0 Terminal Count */
+
+/* Slave DMA Channel 0-3 Control Register Bit Definitions */
+
+#define DAKSEN 0x80 /* Internal /DACKX Sense */
+#define DRQSEN 0x40 /* Internal drqx Sense */
+#define WRTSEL 0x20 /* Write Selection Control */
+#define PRITYPE 0x10 /* Priority Type */
+#define COMPTIM 0x08 /* Compressed Timing */
+#define DMA_DIS 0x04 /* Disable DMA Controller */
+
+/* Slave Software DRQ(n) Request Register Bit Definitions */
+
+#define REQDMA 0x04 /* Software DMA Request */
+
+#define REQSEL_CH0 0x00 /* DMA Channel Select: channel 0 */
+#define REQSEL_CH1 0x01 /* DMA Channel Select: channel 1 */
+#define REQSEL_CH2 0x02 /* DMA Channel Select: channel 2 */
+#define REQSEL_CH3 0x03 /* DMA Channel Select: channel 3 */
+
+/* Slave DMA Channel 0-3 Mask Register Bit Definitions */
+
+#define CHMASK 0x40 /* DMA Channel Mask */
+
+#define MSKSEL_CH0 0x00 /* DMA Channel Mask Select: channel 0 */
+#define MSKSEL_CH1 0x01 /* DMA Channel Mask Select: channel 1 */
+#define MSKSEL_CH2 0x02 /* DMA Channel Mask Select: channel 2 */
+#define MSKSEL_CH3 0x03 /* DMA Channel Mask Select: channel 3 */
+
+/* Slave DMA Channel 0-3 Mode Register Bit Definitions */
+
+#define TRNMOD_DTM 0x00 /* Transfer Mode: Demand transfer */
+#define TRNMOD_STM 0x40 /* Transfer Mode: Single transfer */
+#define TRNMOD_BTM 0x80 /* Transfer Mode: Block transfer */
+#define TRNMOD_CM 0xC0 /* Transfer Mode: Cascade Mode */
+
+#define ADDDEC 0x20 /* Address Decrement */
+#define AINIT 0x10 /* Automatic Initilization Control */
+
+#define OPSEL_VM 0x00 /* Operation Select: Verify Mode */
+#define OPSEL_WT 0x40 /* Operation Select: Write Transfer Mode */
+#define OPSEL_RT 0x80 /* Operation Select: Read Transfer Mode */
+
+#define MODSEL_CH0 0x00 /* DMA Channel Select:channel 0 */
+#define MODSEL_CH1 0x01 /* DMA Channel Select:channel 1 */
+#define MODSEL_CH2 0x02 /* DMA Channel Select:channel 2 */
+#define MODSEL_CH30 0x03 /* DMA Channel Select:channel 3 */
+
+/* Slave DMA Clear Byte Pointer Register Masks */
+
+#define SLAVE_CBP 0xFF /* Slave DMA Clear Byte Pointer */
+
+/* Slave DMA Controller Reset Register Masks */
+
+#define SLAVE_RST 0xFF /* Slave DMA Controller Reset */
+
+/* Slave DMA Controller Temporary Register Masks */
+
+#define SLAVE_TMP 0xFF /* Slave DMa Controller Temporary Register */
+
+/* Slave DMA Mask Reset Register Masks */
+
+#define SLAVE_MSK_RST 0xFF /* Slave DMA Reset Mask */
+
+/* Slave DMA General Mask Register Bit Definitions */
+
+#define CH3_DIS 0x08 /* DMA Channel 3 Mask */
+#define CH2_DIS 0x04 /* DMA Channel 2 Mask */
+#define CH1_DIS 0x02 /* DMA Channel 1 Mask */
+#define CH0_DIS 0x01 /* DMA Channel 0 Mask */
+
+/* General 0 Register Masks */
+
+#define PORT80 0xFF /* General Purpose R/W Register */
+
+/* Slave DMA Channel 2 Page Register Masks */
+
+#define DMA2MAR 0xFF /* DMA Channel 2 Memory Address Bits [23-16] */
+
+/* Slave DMA Channel 3 Page Register Masks */
+
+#define DMA3MAR 0xFF /* DMA Channel 3 Memory Address Bits [23-16] */
+
+/* Slave DMA Channel 1 Page Register Masks */
+
+#define DMA1MAR 0xFF /* DMA Channel 1 Memory Address Bits [23-16] */
+
+/* General 1 Register Masks */
+
+#define PORT84 0xFF /* General Purpose R/W Register */
+
+/* General 2 Register Masks */
+
+#define PORT85 0xFF /* General Purpose R/W Register */
+
+/* General 3 Register Masks */
+
+#define PORT86 0xFF /* General Purpose R/W Register */
+
+/* Slave DMA Channel 0 Page Register Masks */
+
+#define DMA0MAR 0xFF /* DMA Channel 0 Memory Address Bits [23-16] */
+
+/* General 4 Register Masks */
+
+#define PORT88 0xFF /* General Purpose R/W Register */
+
+
+
+/* Master DMA Channel 6 Page Register Masks */
+
+#define DMA6MAR_H 0xFE /* DMA Channel 6 Memory Address Bits [23-17] */
+
+/* Master DMA Channel 7 Page Register Masks */
+
+#define DMA7MAR_H 0xFE /* DMA Channel 7 Memory Address Bits [23-17] */
+
+/* Master DMA Channel 5 Page Register Masks */
+
+#define DMA5MAR_H 0xFE /* DMA Channel 5 Memory Address Bits [23-17] */
+
+/* General 5 Register Masks */
+
+#define PORT8C 0xFF /* General Purpose R/W Register */
+
+/* General 6 Register Masks */
+
+#define PORT8D 0xFF /* General Purpose R/W Register */
+
+/* General 7 Register Masks */
+
+#define PORT8E 0xFF /* General Purpose R/W Register */
+
+/* General 8 Register Masks */
+
+#define PORT8F 0xFF /* General Purpose R/W Register */
+
+/* Master DMA Channel 4 Memory Address Register Masks */
+
+#define DMA4MAR 0xFF /* DMA Channel 4 Memory Address */
+
+/* Master DMA Channel 4 Transfer Count Register Masks */
+
+#define DMA4TC 0xFF /* DMA Channel 4 Transfer Count */
+
+/* Master DMA Channel 5 Memory Address Register Masks */
+
+#define DMA5MAR 0xFF /* DMA Channel 5 Memory Address */
+
+/* Master DMA Channel 5 Transfer Count Register Masks */
+
+#define DMA5TC 0xFF /* DMA Channel 5 Transfer Count */
+
+/* Master DMA Channel 6 Memory Address Register Masks */
+
+#define DMA6MAR 0xFF /* DMA Channel 6 Memory Address */
+
+/* Master DMA Channel 6 Transfer Count Register Masks */
+
+#define DMA6TC 0xFF /* DMA Channel 6 Transfer Count */
+
+/* Master DMA Channel 7 Memory Address Register Masks */
+
+#define DMA7MAR 0xFF /* DMA Channel 7 Memory Address */
+
+/* Master DMA Channel 7 Transfer Count Register Masks */
+
+#define DMA7TC 0xFF /* DMA Channel 7 Transfer Count */
+
+/* Master DMA Channel 4-7 Status Register Bit Definitions */
+
+#define DMAR7 0x80 /* Channel 7 DMA Request */
+#define DMAR6 0x40 /* Channel 6 DMA Request */
+#define DMAR5 0x20 /* Channel 5 DMA Request */
+#define DMAR4 0x10 /* Channel 4 DMA Request */
+
+#define TC7 0x08 /* Channel 7 Terminal Count */
+#define TC6 0x04 /* Channel 6 Terminal Count */
+#define TC5 0x02 /* Channel 5 Terminal Count */
+#define TC4 0x01 /* Channel 4 Terminal Count */
+
+/* Master DMA Channel 4-7 Control Bit Definitions already defined previously */
+
+ /* REQDMA bit already definined */
+
+#define REQSEL1_CH4 0x00 /* DMA Channel Select: Channel 4 */
+#define REQSEL1_CH5 0x01 /* DMA Channel Select: Channel 5 */
+#define REQSEL1_CH6 0x02 /* DMA Channel Select: Channel 6 */
+#define REQSEL1_CH7 0x03 /* DMA Channel Select: Channel 7 */
+
+/* Master DMA Channel 4-7 Mask Register Definitions */
+
+ /* CHMASK bit already correctly defined previously */
+
+#define MSKSEL_CH4 0x00 /* DMA Channel Mask Select: channel 4 */
+#define MSKSEL_CH5 0x01 /* DMA Channel Mask Select: channel 5 */
+#define MSKSEL_CH6 0x02 /* DMA Channel Mask Select: channel 6 */
+#define MSKSEL_CH7 0x03 /* DMA Channel Mask Select: channel 7 */
+
+/* Master DMA Channel 4-7 Mode Register Bit Definitions */
+
+ /* TRNMOD bits already defined */
+ /* ADDDEC bit already defined */
+ /* AINIT bit already defined */
+ /* OPSEL bits already defined */
+
+#define MODSEL_CH4 0x00 /* DMA Channel Select: Channel 4 */
+#define MODSEL_CH5 0x01 /* DMA Channel Select: Channel 5 */
+#define MODSEL_CH6 0x02 /* DMA Channel Select: Channel 6 */
+#define MODSEL_CH7 0x03 /* DMA Channel Select: Channel 7 */
+
+/* Master DEMA Clear Byte Pointer Register Masks */
+
+#define MASTR_CBP 0xFF /* Master DMA Clear Byte Pointer */
+
+/* Master DMA Controller Reset Register Masks */
+
+#define MASTR_RST 0xFF /* Master DMA Controller Reset */
+
+/* Master DMA Controller Temporary Register Masks */
+
+#define MASTR_TMP 0xFF /* Master DMA Controller Temporary Register */
+
+/* Master DMA Mask Reset Register Masks */
+
+#define MASTR_MSK_RST 0xFF /* Master DMA Reset Mask */
+
+/* Master DMA General Mask Register Bit Definitions */
+
+#define CH7_DIS 0x08 /* DMA Channel 7 Mask */
+#define CH6_DIS 0x04 /* DMA Channel 6 Mask */
+#define CH5_DIS 0x02 /* DMA Channel 5 Mask */
+#define CH4_DIS 0x01 /* DMA Channel 4 Mask */
+
+/****************************
+* Real-Time Clock Registers *
+****************************/
+
+/* Real-Time Clock Direct-Mapped Registers */
+
+#define RTCIDX 0x0070 /* RTC/CMOS RAM Index Register */
+#define RTCDATA 0x0071 /* RTC/CMOS RAM Data Port */
+
+/* Real-Time Clock Indexed Registers */
+
+#define RTCCURSEC 0x00 /* RTC Current Second */
+#define RTCALMSEC 0x01 /* RTC Alarm Second */
+#define RTCCURMIN 0x02 /* RTC Current Minute */
+#define RTCALMMIN 0x03 /* RTC Alarm Minute */
+#define RTCCURHR 0x04 /* RTC Current Hour */
+#define RTCALMHR 0x05 /* RTC Alarm Hour */
+#define RTCCURDOW 0x06 /* RTC Current Day of Week */
+#define RTCCURDOM 0x07 /* RTC Current Day of Month */
+#define RTCDURMON 0x08 /* RTC Current Month */
+#define RTCCURYR 0x09 /* RTC Current Year */
+#define RTCCTLA 0x0a /* RTC Control A */
+#define RTCCTLB 0x0b /* RTC Control A */
+#define RTCCTLC 0x0c /* RTC Control A */
+#define RTCCTLD 0x0d /* RTC Control A */
+
+/*
+Real-Time Clock Register Bit Definitions
+*/
+
+/* RTC/CMOS RAM Index Register Mask */
+
+#define CMOSIDX 0x7E /* RTC/CMOS RAM Index */
+
+/* RTC/CMOS RAM Data Port Register Mask */
+
+#define CMOSDATA 0xFF /* RTC/CMOS Data Port */
+
+/* RTC Current Second Register Mask */
+
+#define SECOND 0xFF /* RTC Current Second */
+
+/* RTC Alarm Second Register Mask */
+
+#define ALM_SECOND 0xFF /* RTC Alarm Second */
+
+/* RTC Current Minute Register Mask */
+
+#define MINUTE 0xFF /* RTC Current Minute */
+
+/* RTC Alarm Minute Register Mask */
+
+#define ALM_MINUTE 0xFF /* RTC Alarm Minute */
+
+/* RTC Current Hour Register Bit Definitions */
+
+#define AM_PM 0x80 /* RTC AM/PM Indicator */
+
+/* RTC Current Hour Register Mask */
+
+#define HOUR 0x7F /* RTC Current Hour */
+
+/* RTC Alarm Hour Register Bit Definitions */
+
+#define ALARM_AM_PM 0x80 /* RTC Alarm AM/PM Indicator */
+
+/* RTC Alarm Hour Register Mask */
+
+#define ALM_HOUR 0x7F /* RTC Alarm Hour */
+
+/* RTC Current Day of the Week Register Bit Definitions */
+
+#define SUNDAY 0x01 /* Sunday day of week */
+#define MONDAY 0x02 /* Monday day of week */
+#define TUESDAY 0x03 /* Tuesday day of week */
+#define WEDNESDAY 0x04 /* Wednesday day of week */
+#define THURDAY 0x05 /* Thursday day of week */
+#define FRIDAY 0x06 /* Friday!!!! day of week */
+#define SATURDAY 0x07 /* Saturday day of week */
+
+/* RTC Current Day of the Week Register Mask */
+
+#define DAY_OF_WEEK 0xFF /* RTC Current Day of the Week */
+
+/* RTC Current Day of the Month Register Mask */
+
+#define DAY_OF_MTH 0xFF /* RTC Current Day of the Month */
+
+/* RTC Current Month Register Bit Definitions */
+
+#define JANUARY 0x01 /* month of January */
+#define FEBRUARY 0x02 /* month of February */
+#define MARCH 0x03 /* month of March */
+#define APRIL 0x04 /* month of April */
+#define MAY 0x05 /* month of May */
+#define JUNE 0x06 /* month of June */
+#define JULY 0x07 /* month of July */
+#define AUGUST 0x08 /* month of August */
+#define SEPTEMBER 0x09 /* month of September */
+#define OCTOBER 0x0a /* month of October */
+#define NOVEMBER 0x0b /* month of November */
+#define DECEMBER 0x0c /* month of December */
+
+/* RTC Current Month Register Mask */
+
+#define MONTH 0xFF /* RTC Current Month */
+
+/* RTC Current Year Register Mask */
+
+#define YEAR 0xFF /* RTC Current Year */
+
+/* RTC Control A Register Bit Definitions */
+
+#define UIP 0x80 /* Update in Progress */
+
+#define OSC_CTL_ENB 0x20 /* Enable RTC to be updated once per sec (normal) */
+#define OSC_CTL_HOLD 0x60 /* Hold RTC in reset state */
+
+#define RATE_SEL_PID 0x00 /* Rate Selection: Periodic Interrupt Disabled */
+#define RATE_SEL_3_906m 0x01 /* Rate Selection: 3.906 milliseconds */
+#define RATE_SEL_7_812m 0x02 /* Rate Selection: 7.812 milliseconds */
+#define RATE_SEL_122_070u 0x03 /* Rate Selection: 122.070 microseconds */
+#define RATE_SEL_244_141u 0x04 /* Rate Selection: 244.141 microseconds */
+#define RATE_SEL_488_281u 0x05 /* Rate Selection: 488.281 microseconds */
+#define RATE_SEL_976_563u 0x06 /* Rate Selection: 976.563 microseconds */
+
+#define RATE_SEL_1_953m 0x09 /* Rate Selection: 1.953 milliseconds */
+#define RATE_SEL_15_625m 0x0a /* Rate Selection: 15.625 milliseconds */
+#define RATE_SEL_31_250m 0x0b /* Rate Selection: 31.250 milliseconds */
+#define RATE_SEL_62_500m 0x0c /* Rate Selection: 62.500 milliseconds */
+#define RATE_SEL_125_000m 0x0d /* Rate Selection: 125.000 milliseconds */
+#define RATE_SEL_250_000m 0x0e /* Rate Selection: 250.000 milliseconds */
+#define RATE_SEL_500_000m 0x0f /* Rate Selection: 500.000 milliseconds */
+
+/* RTC Control B Register Bit Definitions */
+
+#define SET 0x80 /* Set Bit */
+#define PER_INT_ENB 0x40 /* Periodic Interrupt Enable */
+#define ALM_INT_ENB 0x20 /* Alarm Interrupt Enable */
+#define UPD_INT_ENB 0x10 /* Update-Ended Interrupt Enable */
+#define DATE_MODE 0x04 /* Date Mode */
+#define HOUR_MODE_SEL 0x02 /* 12/24-Hour Mode Select Bit */
+#define DS_ENB 0x01 /* Daylight Savings Enable */
+
+/* RTC Status C Register Bit Definitions */
+
+#define INT_FLG 0x80 /* Interrupt Request Flag */
+#define PER_INT_FLG 0x40 /* Periodic Interrupt Flag */
+#define ALM_INT_FLG 0x20 /* Alarm Interrupt Flag */
+#define UPD_INT_FLG 0x10 /* Update-Ended Interrupt Flag */
+
+
+/* RTC Status D Register Bit Definitions */
+
+#define RTC_VRT 0x80 /* Valid Ram and Time */
+
+/* General-Purpose CMOS RAM Mask */
+
+#define RTC_CMOS_REG_X 0xFF /* CMOS RAM Location */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#endif /* _ASM_IC_SC520_DEFS_H_ */
diff --git a/include/configs/eNET.h b/include/configs/eNET.h
new file mode 100644
index 0000000..4f206df
--- /dev/null
+++ b/include/configs/eNET.h
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, daniel at omicron.se.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define DEBUG_PARSER
+
+#define CONFIG_X86 1 /* This is a X86 CPU */
+#define CONFIG_SC520 1 /* Include support for AMD SC520 */
+#define CONFIG_SC520_SSI
+
+/*
+ * No video hardware on the eNET
+ */
+#undef CONFIG_VIDEO /* No Video Hardware */
+#undef CONFIG_CFB_CONSOLE
+
+#define CFG_SDRAM_DRCTMCTL 0x18
+
+#undef CFG_SDRAM_PRECHARGE_DELAY /* CFG_SDRAM_DRCTMCTL Overrides */
+#undef CFG_SDRAM_REFRESH_RATE /* CFG_SDRAM_DRCTMCTL Overrides */
+#undef CFG_SDRAM_RAS_CAS_DELAY /* CFG_SDRAM_DRCTMCTL Overrides */
+#undef CFG_SDRAM_CAS_LATENCY_2T /* CFG_SDRAM_DRCTMCTL Overrides */
+#undef CFG_SDRAM_CAS_LATENCY_3T /* CFG_SDRAM_DRCTMCTL Overrides */
+
+#define CFG_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
+#define CFG_RESET_GENERIC /* use tripple-fault to reset cpu */
+#undef CFG_RESET_SC520 /* use SC520 MMCR's to reset cpu */
+#define CFG_TIMER_SC520 /* use SC520 swtimers */
+#undef CFG_TIMER_GENERIC /* use the i8254 PIT timers */
+#undef CFG_TIMER_TSC /* use the Pentium TSC timers */
+#define CFG_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
+ * in the SC520 on the CDP */
+
+#define CFG_STACK_SIZE 0x8000 /* Size of bootloader stack */
+#define CFG_RELOC_ADDR 0x03fd0000 /* Address of relocated code */
+
+#define CONFIG_SHOW_BOOT_PROGRESS 1
+#define CONFIG_LAST_STAGE_INIT 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
+
+#define CONFIG_BAUDRATE 9600
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+
+#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */
+#define CONFIG_CMD_BDI /* bdinfo */
+#define CONFIG_CMD_BOOTD /* bootd */
+#define CONFIG_CMD_CONSOLE /* coninfo */
+#define CONFIG_CMD_ECHO /* echo arguments */
+#define CONFIG_CMD_ENV /* saveenv */
+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
+#define CONFIG_CMD_FPGA /* FPGA configuration Support */
+#define CONFIG_CMD_IMI /* iminfo */
+#define CONFIG_CMD_IMLS /* List all found images */
+#define CONFIG_CMD_ITEST /* Integer (and string) test */
+#define CONFIG_CMD_LOADB /* loadb */
+#define CONFIG_CMD_LOADS /* loads */
+#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
+#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
+#undef CONFIG_CMD_NFS /* NFS support */
+#define CONFIG_CMD_RUN /* run command in env variable */
+#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
+#define CONFIG_CMD_XIMG /* Load part of Multi Image */
+
+
+
+
+
+#define CONFIG_BOOTDELAY 15
+#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
+/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "boot > " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1024 /* incrementer freq: 1kHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 4 /* we have 4 banks of DRAM */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Environment in NVRAM */
+#define CONFIG_ENV_IS_IN_NVRAM
+#define CONFIG_ENV_ADDR 0x19000000
+#define CONFIG_ENV_SIZE 0x1000
+/************************************************************
+ * RTC
+ ***********************************************************/
+#define CONFIG_RTC_MC146818
+
+/*
+ * Enable hardware watchdog.
+ *
+ * WARNING: If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
+ * bottom (processor) board MUST be removed!
+ */
+#undef CONFIG_WATCHDOG
+#define CONFIG_HW_WATCHDOG
+
+/*
+ * PCI stuff
+ */
+#undef CONFIG_PCI /* include pci support */
+#undef CONFIG_PCI_PNP /* pci plug-and-play */
+#undef CONFIG_PCI_SCAN_SHOW
+
+#undef CFG_FIRST_PCI_IRQ
+#undef CFG_SECOND_PCI_IRQ
+#undef CFG_THIRD_PCI_IRQ
+#undef CFG_FORTH_PCI_IRQ
+/*
+ * #undef CFG_FIRST_PCI_IRQ 10
+ * #undef CFG_SECOND_PCI_IRQ 9
+ * #undef CFG_THIRD_PCI_IRQ 11
+ * #undef CFG_FORTH_PCI_IRQ 15
+ */
+/*
+ * Hardware watchdog stuff
+ */
+#define CFG_WATCHDOG_PIO_BIT 0x8000
+#define CFG_WATCHDIG_PIO_DATA SC520_PIODATA15_0
+#define CFG_WATCHDIG_PIO_CLR SC520_PIOCLR15_0
+#define CFG_WATCHDIG_PIO_SET SC520_PIOSET15_0
+
+/*
+ * FPGA stuff
+ */
+#define CFG_FPGA_PROGRAM_PIO_BIT 0x2000
+#define CFG_FPGA_INIT_PIO_BIT 0x4000
+#define CFG_FPGA_DONE_PIO_BIT 0x8000
+#define CFG_FPGA_PIO_DATA SC520_PIODATA31_16
+#define CFG_FPGA_PIO_DIRECTION SC520_PIODIR31_16
+#define CFG_FPGA_PIO_CLR SC520_PIOCLR31_16
+#define CFG_FPGA_PIO_SET SC520_PIOSET31_16
+#define CFG_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
+#define CFG_FPGA_MAX_INIT_TIME 10 /* milliseconds */
+#define CFG_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
+#define CFG_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
+
+#endif /* __CONFIG_H */
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