[U-Boot] [PATCH v2] Marvell Kirkwood family SOC support
Jean-Christophe PLAGNIOL-VILLARD
plagnioj at jcrosoft.com
Fri Apr 17 11:22:29 CEST 2009
On 17:33 Wed 08 Apr , Prafulla Wadaskar wrote:
> Kirkwood family controllers are highly integrated SOCs
> based on Feroceon-88FR131/Sheeva-88SV131 cpu core.
>
> SOC versions supported:-
> 1) 88F6281-Z0 define CONFIG_KW88F6281_Z0
> 2) 88F6281-A0 define CONFIG_KW88F6281_A0
> 3) 88F6192-A0 define CONFIG_KW88F6192_A0
>
> Other supported features:-
> 1) get_random_hex() fucntion
> 2) SPI port controller driver
> 3) PCI Express port initialization
>
> Contributors:
> Yotam Admon <yotam at marvell.com>
> Michael Blostein <michaelbl at marvell.com
>
> Reviewed-by: Ronen Shitrit <rshitrit at marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla at marvell.com>
> ---
> Changelog:
> v2: crated arch-kirkwood and moved some header files there
> renamed and moved spi.c to drivers/spi/
> renamed and moved serial.c to drivers/serial/
> doimage utility removed
> soc_init.S renamed as lowlevel_init.S
> debug prints removed
>
> board/Marvell/include/core.h | 4 +
> cpu/arm926ejs/kirkwood/Makefile | 50 ++++++
> cpu/arm926ejs/kirkwood/config.mk | 25 +++
> cpu/arm926ejs/kirkwood/dram.c | 55 +++++++
> cpu/arm926ejs/kirkwood/kwcore.c | 250 +++++++++++++++++++++++++++++
> cpu/arm926ejs/kirkwood/kwcore.h | 47 ++++++
> cpu/arm926ejs/kirkwood/lowlevel_init.S | 183 +++++++++++++++++++++
> cpu/arm926ejs/kirkwood/timer.c | 165 +++++++++++++++++++
> drivers/serial/Makefile | 1 +
> drivers/serial/kirkwood_serial.c | 187 +++++++++++++++++++++
> drivers/spi/Makefile | 1 +
> drivers/spi/kirkwood_spi.c | 199 +++++++++++++++++++++++
> include/asm-arm/arch-kirkwood/kirkwood.h | 142 ++++++++++++++++
> include/asm-arm/arch-kirkwood/kw88f6192.h | 37 +++++
> include/asm-arm/arch-kirkwood/kw88f6281.h | 43 +++++
> include/asm-arm/config.h | 4 +
> 16 files changed, 1393 insertions(+), 0 deletions(-)
> create mode 100644 cpu/arm926ejs/kirkwood/Makefile
> create mode 100644 cpu/arm926ejs/kirkwood/config.mk
> create mode 100644 cpu/arm926ejs/kirkwood/dram.c
> create mode 100644 cpu/arm926ejs/kirkwood/kwcore.c
> create mode 100644 cpu/arm926ejs/kirkwood/kwcore.h
> create mode 100644 cpu/arm926ejs/kirkwood/lowlevel_init.S
> create mode 100644 cpu/arm926ejs/kirkwood/timer.c
> create mode 100644 drivers/serial/kirkwood_serial.c
> create mode 100644 drivers/spi/kirkwood_spi.c
> create mode 100644 include/asm-arm/arch-kirkwood/kirkwood.h
> create mode 100644 include/asm-arm/arch-kirkwood/kw88f6192.h
> create mode 100644 include/asm-arm/arch-kirkwood/kw88f6281.h
>
> diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h
> index c413439..ecc4682 100644
> --- a/board/Marvell/include/core.h
> +++ b/board/Marvell/include/core.h
> @@ -12,9 +12,11 @@ space). The macros take care of Big/Little endian conversions.
> #ifndef __INCcoreh
> #define __INCcoreh
>
> +#ifndef CONFIG_KIRKWOOD
> #include "mv_gen_reg.h"
>
> extern unsigned int INTERNAL_REG_BASE_ADDR;
> +#endif /* CONFIG_KIRKWOOD */
>
> /****************************************/
> /* GENERAL Definitions */
> @@ -91,10 +93,12 @@ extern unsigned int INTERNAL_REG_BASE_ADDR;
> #define _1G 0x40000000
> #define _2G 0x80000000
>
> +#ifndef __ASSEMBLY__
> #ifndef BOOL_WAS_DEFINED
> #define BOOL_WAS_DEFINED
> typedef enum _bool{false,true} bool;
> #endif
> +#endif
>
> /* Little to Big endian conversion macros */
>
> diff --git a/cpu/arm926ejs/kirkwood/Makefile b/cpu/arm926ejs/kirkwood/Makefile
> new file mode 100644
> index 0000000..c917f0d
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/Makefile
> @@ -0,0 +1,50 @@
> +#
> +# (C) Copyright 2009
> +# Marvell Semiconductor <www.marvell.com>
> +# Prafulla Wadaskar <prafulla at marvell.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB = $(obj)lib$(SOC).a
> +
> +COBJS-y = dram.o
> +COBJS-y += kwcore.o
> +COBJS-y += timer.o
> +
> +SOBJS = lowlevel_init.o
> +
> +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
> +
> +all: $(obj).depend $(LIB)
> +
> +$(LIB): $(OBJS)
> + $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/cpu/arm926ejs/kirkwood/config.mk b/cpu/arm926ejs/kirkwood/config.mk
> new file mode 100644
> index 0000000..000eeb4
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/config.mk
> @@ -0,0 +1,25 @@
> +#
> +# (C) Copyright 2009
> +# Marvell Semiconductor <www.marvell.com>
> +# Prafulla Wadaskar <prafulla at marvell.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +
> +PLATFORM_CPPFLAGS += -march=armv5te
> diff --git a/cpu/arm926ejs/kirkwood/dram.c b/cpu/arm926ejs/kirkwood/dram.c
> new file mode 100644
> index 0000000..80e2b13
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/dram.c
> @@ -0,0 +1,55 @@
> +/*
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <config.h>
> +
> +/*
> + * kw_sdram_bar - reads SDRAM Base Address Register
> + */
> +u32 kw_sdram_bar(MEMORY_BANK bank)
> +{
> + u32 result = 0;
> + u32 enable = (0x01 & KW_REG_READ((0x1504 + bank * 8)));
please create macro for these registers
please use readx/writex (madatory)
> +
> + if ((!enable) || (bank > BANK3))
> + return 0;
> +
> + result = KW_REG_READ((0x1500 + bank * 8));
> + return result;
> +}
> +
> +/*
> + * kw_sdram_bs - reads SDRAM Bank size
> + */
> +u32 kw_sdram_bs(MEMORY_BANK bank)
> +{
> + u32 result = 0;
> + u32 enable = (0x01 & KW_REG_READ((0x1504 + bank * 8)));
> +
> + if ((!enable) || (bank > BANK3))
> + return 0;
> + result = (0xff000000 & KW_REG_READ((0x1504 + bank * 8)));
> + result += 0x01000000;
> + return result;
> +}
> diff --git a/cpu/arm926ejs/kirkwood/kwcore.c b/cpu/arm926ejs/kirkwood/kwcore.c
> new file mode 100644
> index 0000000..2e887d5
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/kwcore.c
> @@ -0,0 +1,250 @@
> +/*
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <u-boot/md5.h>
> +
> +void reset_cpu(unsigned long ignored)
> +{
> + KW_REG_BITS_SET(KW_REG_CPU_RSTOUTN_MASK, BIT2);
> + KW_REG_BITS_SET(KW_REG_CPU_SYS_SOFT_RST, BIT0);
plase use readx/writex
everywhere
> + while (1) ;
> +}
> +
> +/*
> + * Generates Ramdom hex number reading some time varient system registers
> + * and using md5 algorithm
> + */
> +unsigned char get_random_hex(void)
> +{
> + int i;
> + u32 inbuf[16];
> + u8 outbuf[16];
> +
> +#if defined (CONFIG_KW88F6281_Z0)
> + KW_REG_BITS_SET(0x1478, BIT7);
> +#elif defined (CONFIG_KW88F6281_A0) || defined (CONFIG_KW88F6192_A0)
could you detect it
> + /*
> + * in case of 88F6281/88F6192 A0,
> + * BIT7 need to reset to generate random values in 0x1470
> + */
> + KW_REG_BITS_RESET(0x1478, BIT7);
please use macro everywhere instead of hardcode value
> +#else
> +#error Undefined SOC Revision
> +#endif
> + for (i = 0; i < 16; i++) {
> + inbuf[i] = KW_REG_READ(0x1470);
> + }
> + md5((u8 *) inbuf, 64, outbuf);
> + return outbuf[outbuf[7] % 0x0f];
> +}
> +
> +/*
> + * kw_window_ctrl_reg_init - Mbus-L to Mbus Bridge Registers init.
> + */
> +int kw_window_ctrl_reg_init(void)
> +{
coudl explain a few more what you do and try use macro instead of hardcode
value
> + KW_REG_WRITE(KW_REG_WIN_CTRL(0), 0x0fffe841);
> + KW_REG_WRITE(KW_REG_WIN_BASE(0), 0x90000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(0), 0x90000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(0), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(1), 0x007f2f11);
> + KW_REG_WRITE(KW_REG_WIN_BASE(1), 0xF9000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(1), 0xF9000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(1), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(2), 0x00ffe041);
> + KW_REG_WRITE(KW_REG_WIN_BASE(2), 0xF0000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(2), 0xC0000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(2), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(3), 0x00ff1e11);
> + KW_REG_WRITE(KW_REG_WIN_BASE(3), 0xF8000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(3), 0x00000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(3), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(4), 0x00ff1d11);
> + KW_REG_WRITE(KW_REG_WIN_BASE(4), 0xFF000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(4), 0x00000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(4), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(5), 0x07ff1e10);
> + KW_REG_WRITE(KW_REG_WIN_BASE(5), 0xE8000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(5), 0x00000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(5), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(6), 0x07ff1d10);
> + KW_REG_WRITE(KW_REG_WIN_BASE(6), 0xF0000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(6), 0x00000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(6), 0x00000000);
> +
> + KW_REG_WRITE(KW_REG_WIN_CTRL(7), 0x00000131);
> + KW_REG_WRITE(KW_REG_WIN_BASE(7), 0xFB000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_LOW(7), 0x00000000);
> + KW_REG_WRITE(KW_REG_WIN_REMAP_HIGH(7), 0x00000000);
> +
> + return KW_OK;
> +}
> +
> +/*
> + * kw_gpio_init - Init gpios for default values
> + */
> +void kw_gpio_init(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
> +{
> + /* Init GPIOS to default values as per board requirement */
> + KW_REG_WRITE(KW_REG_GPP0_DATA_OUT, gpp0_oe_val);
> + KW_REG_WRITE(KW_REG_GPP1_DATA_OUT, gpp1_oe_val);
> + KW_REG_WRITE(KW_REG_GPP0_DATA_OUT_EN, gpp0_oe);
> + KW_REG_WRITE(KW_REG_GPP1_DATA_OUT_EN, gpp1_oe);
> +}
> +
> +/*
> + * kw_mpp_control_init - initialize mpp for board specific functionality
> + */
> +int kw_mpp_control_init(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
> + u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
> +{
> + /* program mpp registers */
> + KW_REG_WRITE(KW_REG_MPP_CONTROL0, mpp0_7);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL1, mpp8_15);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL2, mpp16_23);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL3, mpp24_31);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL4, mpp32_39);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL5, mpp40_47);
> + KW_REG_WRITE(KW_REG_MPP_CONTROL6, mpp48_55);
> + return KW_OK;
> +}
> +
> +/*
> + * kw_misc_init_r - SOC specific misc init (mainly cache initialization)
> + */
> +int kw_misc_init_r(void)
> +{
> + char *env;
> + volatile unsigned int temp;
> +
> + /*CPU streaming & write allocate */
> + env = getenv("enaWrAllo");
> + if (env && ((strcmp(env, "yes") == 0) || (strcmp(env, "Yes") == 0))) {
> + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0":"=r"(temp));
please cp15 api (the same as the kernel)
set_cr/get_cr
btw could explain why do you need to do it via env?
be aware that we have cache API
> + temp |= BIT28;
> + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0"::"r"(temp));
> +
> + } else {
> + __asm__ __volatile__("mrc p15, 1, %0, c15, c1, 0":"=r"(temp));
> + temp &= ~BIT28;
> + __asm__ __volatile__("mcr p15, 1, %0, c15, c1, 0"::"r"(temp));
> + }
> +
<snip>
> +
> diff --git a/cpu/arm926ejs/kirkwood/kwcore.h b/cpu/arm926ejs/kirkwood/kwcore.h
> new file mode 100644
> index 0000000..8d2a8cc
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/kwcore.h
> @@ -0,0 +1,47 @@
> +/*
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _KWCORE_H
> +#define _KWCORE_H
> +
> +/*
> + * functions
> + */
> +#ifndef __ASSEMBLY__
> +void reset_cpu(unsigned long ignored);
> +unsigned char get_random_hex(void);
> +typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK;
please do not use upper case
> +unsigned int kw_sdram_bar(MEMORY_BANK bank);
> +unsigned int kw_sdram_bs(MEMORY_BANK bank);
> +int kw_window_ctrl_reg_init(void);
> +void kw_gpio_init(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
> + unsigned int gpp0_oe, unsigned int gpp1_oe);
> +int kw_mpp_control_init(unsigned int mpp0_7, unsigned int mpp8_15,
> + unsigned int mpp16_23, unsigned int mpp24_31,
> + unsigned int mpp32_39, unsigned int mpp40_47,
> + unsigned int mpp48_55);
> +int kw_misc_init_r(void);
> +#endif /* __ASSEMBLY__ */
> +
> +#endif /* _KWCORE_H */
> diff --git a/cpu/arm926ejs/kirkwood/lowlevel_init.S b/cpu/arm926ejs/kirkwood/lowlevel_init.S
> new file mode 100644
> index 0000000..169e58b
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/lowlevel_init.S
> @@ -0,0 +1,183 @@
> +/*
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <config.h>
> +
> +#define CCR_CPU_2_MBUSL_TICK_DRV_OFFS 8
> +#define CCR_CPU_2_MBUSL_TICK_DRV_MASK (0xF << CCR_CPU_2_MBUSL_TICK_DRV_OFFS)
> +#define CCR_CPU_2_MBUSL_TICK_SMPL_OFFS 12
> +#define CCR_CPU_2_MBUSL_TICK_SMPL_MASK (0xF << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS)
> +
> +#define MSAR_DDRCLCK_RTIO_OFFS 5
> +#define MSAR_DDRCLCK_RTIO_MASK (0xF << MSAR_DDRCLCK_RTIO_OFFS)
> +
> +/* Ratio options for CPU to DDR for 6281/6192/6180 */
> +#define CPU_2_DDR_CLK_1x2 2
> +#define CPU_2_DDR_CLK_1x3 4
> +#define CPU_2_DDR_CLK_1x4 6
> +
> +/* Default values for CPU to Mbus-L DDR Interface Tick Driver and */
> +/* CPU to Mbus-L Tick Sample fields in CPU config register */
> +
> +#define TICK_DRV_1x1 0
> +#define TICK_DRV_1x2 0
> +#define TICK_DRV_1x3 1
> +#define TICK_DRV_1x4 2
> +#define TICK_SMPL_1x1 0
> +#define TICK_SMPL_1x2 1
> +#define TICK_SMPL_1x3 2
> +#define TICK_SMPL_1x4 3
> +#define CPU_2_MBUSL_DDR_CLK_1x2 \
> + ((TICK_DRV_1x2 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
> + (TICK_SMPL_1x2 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
> +#define CPU_2_MBUSL_DDR_CLK_1x3 \
> + ((TICK_DRV_1x3 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
> + (TICK_SMPL_1x3 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
> +#define CPU_2_MBUSL_DDR_CLK_1x4 \
> + ((TICK_DRV_1x4 << CCR_CPU_2_MBUSL_TICK_DRV_OFFS) | \
> + (TICK_SMPL_1x4 << CCR_CPU_2_MBUSL_TICK_SMPL_OFFS))
> +
please move all this define to header corresponding of the functionallity/IP
> +
> + .globl kw_cpu_if_pre_init
> +kw_cpu_if_pre_init:
do you really need to do this before relocation
> +
> + mov r11, LR /* Save link register */
will you call a sub routine?
> +
> + /*
> + * Configures the I/O voltage of the pads connected to Egigabit
> + * Ethernet interface to 1.8V
> + * By defult it is set to 3.3V
> + */
> +#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
> + KW_REG_READ_ASM (r7, r5, KW_REG_MPP_OUT_DRV_REG)
> + ldr r5, =BIT7
> + orr r7, r7, r5 /* Set RGMII PADS Voltage to 1.8V */
> + KW_REG_WRITE_ASM (r7, r5, KW_REG_MPP_OUT_DRV_REG)
> +#endif
> + /*
> + * Set egiga port0/1 in normal functional mode
> + * This is required becasue on kirkwood by default ports are in reset mode
> + * OS egiga driver may not have provision to set them in normal mode
> + * and if u-boot is build without network support, network may fail at OS level
> + */
> +#ifdef CONFIG_KIRKWOOD_EGIGA_INIT
> + KW_REG_READ_ASM (r7, r5, KW_ETH_PORT_SERIAL_CONTROL1_REG(0))
> + ldr r5, =~(BIT4)
> + and r7, r7, r5 /* Clear PortReset Bit */
> + KW_REG_WRITE_ASM (r7, r5, KW_ETH_PORT_SERIAL_CONTROL1_REG(0))
> +
> + KW_REG_READ_ASM (r7, r5, KW_ETH_PORT_SERIAL_CONTROL1_REG(1))
> + ldr r5, =~(BIT4)
> + and r7, r7, r5 /* Clear PortReset Bit */
> + KW_REG_WRITE_ASM (r7, r5, KW_ETH_PORT_SERIAL_CONTROL1_REG(1))
> +#endif
> +
> + /*
> + * Enable PCI Express Port0
> + */
> +#ifdef CONFIG_KIRKWOOD_PCIE_INIT
> + KW_REG_READ_ASM (r7, r5, KW_REG_CPU_CTRL_STAT)
> + ldr r5, =BIT0
> + orr r7, r7, r5 /* Set PEX0En Bit */
> + KW_REG_WRITE_ASM (r7, r5, KW_REG_CPU_CTRL_STAT)
> +#endif
> +
> +#ifdef CONFIG_KW88F6281_Z0
> + /* Get the "sample on reset" register */
> + KW_REG_READ_ASM (r4, r5, KW_REG_MPP_SMPL_AT_RST)
> + ldr r5, =MSAR_DDRCLCK_RTIO_MASK
> + and r5, r4, r5
> + mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS
> +
> + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x2
> + cmp r5, #CPU_2_DDR_CLK_1x2
> + beq set_config_reg
> +
> + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
> + cmp r5, #CPU_2_DDR_CLK_1x3
> + beq set_config_reg
> +
> + ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
> + cmp r5, #CPU_2_DDR_CLK_1x4
> + beq set_config_reg
> +
> + ldr r4, =0
> +
> +set_config_reg:
> + /* Read CPU Config register */
> + KW_REG_READ_ASM (r7, r5, KW_REG_CPU_CONFIG)
> + ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK)
> + and r7, r7, r5 /* Clear register fields */
> + orr r7, r7, r4 /* Set the values according to the findings */
> + KW_REG_WRITE_ASM (r7, r5, KW_REG_CPU_CONFIG)
> +
> +done:
> +#endif
> + mov PC, r11 /* r11 is saved link register */
> +
> + .globl kw_enable_invalidate_l2_cache
> +kw_enable_invalidate_l2_cache:
> + mov r11, LR /* Save link register */
> +
> + /* Enable L2 cache in write through mode */
> + KW_REG_READ_ASM(r4, r1, KW_REG_CPU_L2_CONFIG)
please remove thhis KW_RED_READ_ASM
or do it via asm macro as we have done for sh2/3/4
> + orr r4, r4, #0x18
> + KW_REG_WRITE_ASM(r4, r1, KW_REG_CPU_L2_CONFIG)
> + /* Read operation to make sure the L2 bit is set */
> + KW_REG_READ_ASM(r4, r1, KW_REG_CPU_L2_CONFIG)
> +
> + /* invalidate L2 cache */
> + mov r0, #0
> + mcr p15, 1, r0, c15, c11, 0
please create a macro for this
> +
> + mov PC, r11 /* r11 is saved link register */
> +
> + .globl lowlevel_init
in this case call it arch_lowlevel_init
and update start.S to call it just be the lowlevel_init
which is board lowlevel init
> +lowlevel_init:
if you have multple sub call use the stack will be beter
> + /* Linux expects` the internal registers to be at 0xf1000000 */
> + ldr r1, = KW_OFFSET_REG
> + ldr r3, = KW_REGS_PHY_BASE
> + str r3,[r1]
> +
> + /* save Link Registers */
> + mov r2, lr
> +
> + /* Enable L2 cache in write through mode */
> + bl kw_enable_invalidate_l2_cache
> +
> +#ifdef CONFIG_BOARD_LOWLEVEL_INIT
> + /*
> + * if Kirkwood is configured not to use its internal bootROM
> + * This will be needed specially for DRAM configuration
> + */
> + bl board_lowlevel_init
> +#endif
> +
> + /*
> + * Initialize BUS-L to DDR configuration parameters
> + * Must be done prior to DDR operation
> + */
> + bl kw_cpu_if_pre_init
> + mov lr, r2
> + mov pc, lr
> diff --git a/cpu/arm926ejs/kirkwood/timer.c b/cpu/arm926ejs/kirkwood/timer.c
> new file mode 100644
> index 0000000..4ab1a54
> --- /dev/null
> +++ b/cpu/arm926ejs/kirkwood/timer.c
> @@ -0,0 +1,165 @@
> +/*
> + * Copyright (C) Marvell International Ltd. and its affiliates
> + * Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +
> +#define UBOOT_CNTR 0 /* counter to use for uboot timer */
> +
> +/*
> + * ARM Timers Registers Map
> + */
> +#define CNTMR_CTRL_REG KW_REG_TMR_CTRL
> +#define CNTMR_RELOAD_REG(tmrNum) (KW_REG_TMR_RELOAD + tmrNum*8)
> +#define CNTMR_VAL_REG(tmrNum) (KW_REG_TMR_VAL + tmrNum*8)
please no uppercase in the var name
> +
> +/*
> + * ARM Timers Control Register
> + * CPU_TIMERS_CTRL_REG (CTCR)
> + */
> +#define TIMER0_NUM 0
> +#define TIMER1_NUM 1
> +#define WATCHDOG_NUM 2
> +
> +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
> +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
> +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
> +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
> +
> +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
> +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) BIT1
> +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
> +
> +/*
> + * ARM Timer\Watchdog Reload Register
> + * CNTMR_RELOAD_REG (TRR)
> + */
> +#define TRG_ARM_TIMER_REL_OFFS 0
> +#define TRG_ARM_TIMER_REL_MASK 0xffffffff
> +
> +/*
> + * ARM Timer\Watchdog Register
> + * CNTMR_VAL_REG (TVRG)
> + */
> +#define TVR_ARM_TIMER_OFFS 0
> +#define TVR_ARM_TIMER_MASK 0xffffffff
> +#define TVR_ARM_TIMER_MAX 0xffffffff
please move all this define to a header
and nearly all precedent comment can be apply to the rest of the patch
Best Regards,
J.
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