[U-Boot] [PATCH] omap2420h4: move arch pre lowlevel init to board

[Jean-Christophe PLAGNIOL-VILLARD]

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
Cc: Richard Woodruff <r-woodruff2 at ti.com>
---
 board/omap2420h4/lowlevel_init.S |   23 +++++++++++++++++++++++
 cpu/arm1136/start.S              |   20 +++-----------------
 include/configs/omap2420h4.h     |    1 +
 3 files changed, 27 insertions(+), 17 deletions(-)

diff --git a/board/omap2420h4/lowlevel_init.S b/board/omap2420h4/lowlevel_init.S
index 9752fc4..e017e1e 100644
--- a/board/omap2420h4/lowlevel_init.S
+++ b/board/omap2420h4/lowlevel_init.S
@@ -158,6 +158,29 @@ pll_div_add:
 pll_div_val:
     .word DPLL_VAL	/* DPLL setting (300MHz default) */
 
+.global board_pre_lowlevel_init
+board_pre_lowlevel_init:
+	/* Copy vectors to mask ROM indirect addr */
+	add	r0, r0, #4		/* skip reset vector		    */
+	mov	r2, #64			/* r2 <- size to copy		    */
+	add	r2, r0, r2		/* r2 <- source end address	    */
+	mov	r1, #SRAM_OFFSET0	/* build vect addr		    */
+	mov	r3, #SRAM_OFFSET1
+	add	r1, r1, r3
+	mov	r3, #SRAM_OFFSET2
+	add	r1, r1, r3
+next:
+	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
+	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
+	cmp	r0, r2			/* until source end address [r2]    */
+	bne	next			/* loop until equal */
+	mov	ip,	lr		/* save link reg across call */
+	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
+	mov	lr,	ip		/* restore link reg */
+
+	/* the mask ROM code should have PLL and others stable */
+	mov	pc, lr
+
 .globl lowlevel_init
 lowlevel_init:
 	ldr	sp,	SRAM_STACK
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S
index e622338..05220ed 100644
--- a/cpu/arm1136/start.S
+++ b/cpu/arm1136/start.S
@@ -128,25 +128,11 @@ reset:
 	orr	r0,r0,#0xd3
 	msr	cpsr,r0
 
-#ifdef CONFIG_OMAP2420H4
-       /* Copy vectors to mask ROM indirect addr */
+#ifdef CONFIG_BOARD_PRE_LOWLEVEL_INIT
 	adr	r0, _start		/* r0 <- current position of code   */
-		add     r0, r0, #4				/* skip reset vector			*/
-	mov	r2, #64			/* r2 <- size to copy  */
-	add	r2, r0, r2		/* r2 <- source end address	    */
-	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	bne	next			/* loop until equal */
-	bl	cpy_clk_code		/* put dpll adjust code behind vectors */
+	bl	board_pre_lowlevel_init
 #endif
-	/* the mask ROM code should have PLL and others stable */
+
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl  cpu_init_crit
 #endif
diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h
index 1803b13..5683b3a 100644
--- a/include/configs/omap2420h4.h
+++ b/include/configs/omap2420h4.h
@@ -37,6 +37,7 @@
 #define CONFIG_OMAP2420H4        1    /* and on a H4 board */
 /*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
 /*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
+#define CONFIG_BOARD_PRE_LOWLEVEL_INIT
 
 /* Clock config to target*/
 #define PRCM_CONFIG_II	1
-- 
1.6.2.1