[U-Boot] [patch u-boot git arm/next] davinci: display correct clock info

[David Brownell]

On Wednesday 29 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:38 Wed 29 Apr     , David Brownell wrote:
> > From: David Brownell <dbrownell at users.sourceforge.net>
> > 
> > Make the DaVinci clock display code work on the dm355 too ... there
> > are pre- and post- dividers on its PLLs, which most other DaVinci
> > processors don't use; and it uses different PLL dividers.  Stubbed
> > in support for the DM6467 too.  Verified on dm355 and dm6446.
> > 
> > Signed-off-by: David Brownell <dbrownell at users.sourceforge.net>
> > ---
> > This should move to cpu/arm926ejs/davinci (cpuinfo.c?) someday,
> > like the other SoC-specific code.  For another patch.
>
> good idea
> 
> cpu.c will be better

I was thinking of using CONFIG_DISPLAY_CPUINFO hooks for that,
and those seem to be in cpuinfo.c files.  (Someday, when time
allows.)


> btw a clock design as done for at91 & avr32 will be nice too

It's missing from at91rm9200 ... ;)

Those seem to be useful if U-Boot is the first stage boot
loader, running out of NOR flash and needing to do lots of
low level setup:  configure PLLs, clock divisors, memory
timings, start DRAM, and so on.

But most DaVinci boards boot from NAND flash nowadays, making
U-boot be a third stage loader with no lowlevel init.  So
it doesn't need such code ... but if it did, it would touch
the PLL controllers in very different ways (modifying the
registers and handshaking, not just reading like this).


> > +/* offsets from PLL controller base */
> > +#define PLLC_PLLCTL	0x100
> > +#define PLLC_PLLM	0x110
> > +#define PLLC_PREDIV	0x114
> > +#define PLLC_PLLDIV1	0x118
> > +#define PLLC_PLLDIV2	0x11c
> > +#define PLLC_PLLDIV3	0x120
> > +#define PLLC_POSTDIV	0x128
> > +#define PLLC_BPDIV	0x12c
> > +#define PLLC_PLLDIV4	0x160
> > +#define PLLC_PLLDIV5	0x164
> > +#define PLLC_PLLDIV6	0x168
> > +#define PLLC_PLLDIV8	0x170
> > +#define PLLC_PLLDIV9	0x174
>
> who will init the PLL?
> can we detect it if they are already init?

PLL setup is part of lowlevel init ... usually it's
done by the second stage boot loader (UBL) if this
is booting from anything except NOR flash.  For NOR
boot that's now done in cpu/.../lowlevel_init.S code.

By the time this code is called, that's been done a
long time ago ... we're running out of DRAM, which
can't work without active PLLs.  (The oscillator is
from 20-30 MHz, the DRAM clock must be 125 MHz and
up, QED.)


> > +
> > +#define BIT(x)		(1 << (x))
> please remove

When there's a standard definition somewhere ... the
one in include/asm/arch-ixp/ixp425.h is unusable here.


> > +
> > +static inline unsigned pll_prediv(volatile void *pllbase)
> > +{
> > +#ifdef CONFIG_SOC_DM355
> > +	/* this register read seems to fail on pll0 */
>
> maybe an errata?

I didn't see it published, if so.  I noticed that issue
when doing similar code on Linux.


> >  void dv_display_clk_infos(void)
> >  {
> > -	printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2);
> > -	printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) /
> > -	       ((REG(PLL2_DIV2) & 0x1f) + 1) / 2);
> > +	printf("ARM Clock: %dMHz\n",
> > +			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
> > +	printf("DDR Clock: %dMHz\n",
> > +			/* DDR PHY uses an x2 input clock */
> > +			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
> > +				/ 2);
> > +	printf("\n");
> puts("");

OK

> 
> Best Regards,
> J.
> 
>