[U-Boot] [PATCH 1/2 v2] 85xx: CONFIG_MP Boot Page Translation update

[Kumar Gala]

On Aug 5, 2009, at 5:23 PM, Peter Tyser wrote:

> Previously, when CONFIG_MP was defined Boot Page Translation was
> unconditionally enabled and secondary cores were put in a spin loop at
> address 0xfffff000.  The 0xfffffxxx address range (ie the Boot Page)  
> was
> being remapped to SDRAM via the BPTR register.
>
> This change puts secondary cores into spin loops at their 'true'  
> address
> in SDRAM and doesn't require Boot Page Translation to always be  
> enabled.
> The main advantage of this change is that Boot Page Translation can be
> disabled after the secondary cores are brought up which allows the
> memory region at 0xfffffxxx to be used for other peripherals, etc.
>
> By default, Boot Page Translation remains enabled while U-Boot  
> executes.
> A new CONFIG_MPC8xxx_DISABLE_BPTR define has been added which causes
> Boot Page Translation to be disabled for those boards which wish to  
> use
> the 0xfffffxxx address range as part of their normal memory map.
>
> Signed-off-by: Peter Tyser <ptyser at xes-inc.com>
> ---
> Changes since v1:
> - Use clrbits_be32() instead of in/out_be32()
>
> This is very similar to "85xx: Fix mapping of 0xfffffxxx when  
> CONFIG_MP"
> The 2 differences are:
>
> - Boot page translation is only disabled when  
> CONFIG_MPC8xxx_DISABLT_BPTR
>  is defined.
>
> - Instead of zeroing out BPTR when disabling translation, this
>  patch only disables translation, but maintins the translation
>  address.  This should make it easier to properly re-enable
>  translation if need be.
>
> cpu/mpc85xx/mp.c      |   22 ++++++++++++++++++++--
> cpu/mpc85xx/release.S |   30 +++++++++++++++++++++++++-----
> 2 files changed, 45 insertions(+), 7 deletions(-)
>
> diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
> index 76f02a4..53fc3be 100644
> --- a/cpu/mpc85xx/mp.c
> +++ b/cpu/mpc85xx/mp.c
> @@ -129,7 +129,7 @@ ulong get_spin_addr(void)
>
> 	ulong addr =
> 		(ulong)&__spin_table - (ulong)&__secondary_start_page;
> -	addr += 0xfffff000;
> +	addr += determine_mp_bootpg();

changing this has some issues.  We expect the the address that the  
spin table is at to be marked cache-inhibited.

>
> 	return addr;
> }
> @@ -137,7 +137,8 @@ ulong get_spin_addr(void)
> static void pq3_mp_up(unsigned long bootpg)
> {
> 	u32 up, cpu_up_mask, whoami;
> -	u32 *table = (u32 *)get_spin_addr();
> +	/* The table is at 0xfffffxxx due to boot page translation below */
> +	u32 *table = (u32 *)(0xfffff000 | get_spin_addr());
> 	volatile u32 bpcr;
> 	volatile ccsr_local_ecm_t *ecm = (void *) 
> (CONFIG_SYS_MPC85xx_ECM_ADDR);
> 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
> @@ -146,6 +147,8 @@ static void pq3_mp_up(unsigned long bootpg)
> 	int timeout = 10;
>
> 	whoami = in_be32(&pic->whoami);
> +
> +	/* Translate 0xfffffxxx 'bootpg' address range to SDRAM */
> 	out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
>
> 	/* disable time base at the platform */
> @@ -194,6 +197,17 @@ static void pq3_mp_up(unsigned long bootpg)
>
> 	devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
> 	out_be32(&gur->devdisr, devdisr);
> +
> +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
> +	/*
> +	 * Disabling Boot Page Translation allows the memory region  
> 0xfffff000
> +	 * to 0xffffffff to be used normally.  Leaving Boot Page Translation
> +	 * enabled remaps 0xfffff000 to SDRAM which makes that memory region
> +	 * unusable for normal operation but it does allow OSes to easily
> +	 * reset a processor core to put it back into U-Boot's spinloop.
> +	 */
> +	clrbits_be32(&ecm->bptr, 0x80000000);
> +#endif
> }
>
> void cpu_mp_lmb_reserve(struct lmb *lmb)
> @@ -206,9 +220,13 @@ void cpu_mp_lmb_reserve(struct lmb *lmb)
> void setup_mp(void)
> {
> 	extern ulong __secondary_start_page;
> +	extern ulong __bootpg_addr;
> 	ulong fixup = (ulong)&__secondary_start_page;
> 	u32 bootpg = determine_mp_bootpg();
>
> +	/* Store the bootpg's SDRAM address for use by secondary CPU cores  
> */
> +	__bootpg_addr = bootpg;
> +
> 	memcpy((void *)bootpg, (void *)fixup, 4096);
> 	flush_cache(bootpg, 4096);
>
> diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
> index fbefc2c..6799633 100644
> --- a/cpu/mpc85xx/release.S
> +++ b/cpu/mpc85xx/release.S
> @@ -114,23 +114,38 @@ __secondary_start_page:
> 	stw	r3,ENTRY_R6_UPPER(r10)
> 	stw	r3,ENTRY_R6_LOWER(r10)
>
> +	/* load r13 with the address of the 'bootpg' in SDRAM */
> +	lis	r13,toreset(__bootpg_addr)@h
> +	ori	r13,r13,toreset(__bootpg_addr)@l
> +	lwz	r13,0(r13)
> +
> 	/* setup mapping for AS = 1, and jump there */
> 	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
> 	mtspr	SPRN_MAS0,r11
> 	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
> 	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
> 	mtspr	SPRN_MAS1,r11
> -	lis	r11,(0xfffff000|MAS2_I)@h
> -	ori	r11,r11,(0xfffff000|MAS2_I)@l
> +	oris	r11,r13,(MAS2_I)@h
> +	ori	r11,r13,(MAS2_I)@l
> 	mtspr	SPRN_MAS2,r11
> -	lis	r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h
> -	ori	r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l
> +	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
> +	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
> 	mtspr	SPRN_MAS3,r11
> 	tlbwe
>
> 	bl	1f
> 1:	mflr	r11
> -	addi	r11,r11,28
> +	/*
> +	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
> +	 * this mask to fixup the cpu spin table and the address that we  
> want
> +	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
> +	 * bootpg is at 0x7ffff000 in SDRAM.
> +	 */
> +	ori	r13,r13,0xfff
> +	and	r11, r11, r13
> +	and	r10, r10, r13
> +
> +	addi	r11,r11,(2f-1b)
> 	mfmsr	r13
> 	ori	r12,r13,MSR_IS|MSR_DS at l
>
> @@ -200,6 +215,11 @@ __secondary_start_page:
> 	mtspr	SPRN_SRR1,r13
> 	rfi
>
> +	/* Allocate some space for the SDRAM address of the bootpg */
> +	.globl __bootpg_addr
> +__bootpg_addr:
> +	.long	0
> +
> 	.align L1_CACHE_SHIFT
> 	.globl __spin_table
> __spin_table:
> -- 
> 1.6.2.1