[U-Boot] [PATCH] NAND: DaVinci: Adding 4 BIT ECC support

[Scott Wood]

On Tue, Aug 11, 2009 at 10:45:05AM -0400, s-paulraj at ti.com wrote:
> +static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
> +{
> +	u32 val;
> +
> +	switch (mode) {
> +	case NAND_ECC_WRITE:
> +	case NAND_ECC_READ:
> +		/*
> +		 * Start a new ECC calculation for reading or writing 512 bytes
> +		 * of data.
> +		 */
> +		val = (emif_regs->NANDFCR & ~(3 << 4)) | (1 << 12);
> +		emif_regs->NANDFCR = val;
> +		break;
> +	case NAND_ECC_READSYN:
> +		val = emif_regs->NAND4BITECC1;

Use I/O accessors.

> +	for (i = 0; i < 100; i++)
> +		udelay(this->chip_delay);

No explanation for the delay?  Is there any status register you can poll?

Is it truly 100 times the chip delay (even if that changes), or is it a
fixed delay that just happens to work out to that?

> +static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
> +					  uint8_t *read_ecc, uint8_t *calc_ecc)
> +{
> +	return nand_davinci_4bit_compare_ecc(mtd, read_ecc, dat);
> +}

Why have a wrapper?  This seems to be the only place where compare_ecc is
used.

-Scott