[U-Boot] [PATCH] ppc/85xx: Added PCIe support for P1 P2 RDB

Kumar Gala galak at kernel.crashing.org
Thu Aug 20 17:48:18 CEST 2009


On Aug 20, 2009, at 10:14 AM, Wolfgang Denk wrote:

> Dear Poonam Aggrwal,
>
> In message <1250775054-20418-1-git-send-email-poonam.aggrwal at freescale.com 
> > you wrote:
>> * Added PCIe support for P1 P2 RDB
>> * Calls the fsl_pci_init_port function to initialize all the PCIe  
>> ports
>>  on the board.
>>
>> Signed-off-by: Poonam Aggrwal <poonam.aggrwal at freescale.com>
>> Signed-off-by: Kumar Gala <galak at kernel.crashing.org>
>> ---
>> - applies on git.denx.de/u-boot-mpc85xx.git branch->next
>> board/freescale/p1_p2_rdb/Makefile |    1 +
>> board/freescale/p1_p2_rdb/pci.c    |  112 ++++++++++++++++++++++++++ 
>> ++++++++++
>> include/configs/P1_P2_RDB.h        |    6 ++
>> 3 files changed, 119 insertions(+), 0 deletions(-)
>> create mode 100644 board/freescale/p1_p2_rdb/pci.c
>>
>> diff --git a/board/freescale/p1_p2_rdb/Makefile b/board/freescale/ 
>> p1_p2_rdb/Makefile
>> index 9107263..c366f7c 100644
>> --- a/board/freescale/p1_p2_rdb/Makefile
>> +++ b/board/freescale/p1_p2_rdb/Makefile
>> @@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).a
>> COBJS-y	+= $(BOARD).o
>> COBJS-y	+= law.o
>> COBJS-y	+= tlb.o
>> +COBJS-$(CONFIG_PCI)  += pci.o
>> COBJS-y	+= ddr.o
>
> Please (make and) keep list sorted.
>
> ...
>> +void ft_pci_board_setup(void *blob)
>> +{
>> +#ifdef CONFIG_PCIE2
>> +	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
>
> PCIE2 ... pci1 ... pcie2 ???

The device tree has always been more generic and used 'pci' for PCI,  
PCI-X, and PCIe buses.

>
>> +#endif
>> +#ifdef CONFIG_PCIE1
>> +	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
>
> PCIE1 ... pci2 ... pcie1 ???
>
> This looks broken to me?


This is actually correct.. This has to do w/stupid FSL documentation  
and #.  The device tree "orders" PCI buses based on there register  
offset in CCSRBAR.  So 0x9000 is pci1, 0xa000 is pci2.  However FSL  
docs and some internal SoC screwness lists the PCIe controller @ 9000  
as PCIE2 and the one at A000 as PCIE1.

Probably should add a comment in the code about this.

- k


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