[U-Boot] [PATCH 15/17] Move eNET low-level initialisation into asm
Graeme Russ
graeme.russ at gmail.com
Sun Aug 23 04:59:59 CEST 2009
Allows earlier indication of boot progress by initialising the LEDs and
Serial Port while the CPU is still in 16-bit (Real) mode
Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
---
board/eNET/eNET.c | 24 --------
board/eNET/eNET_start.S | 7 ++-
board/eNET/eNET_start16.S | 130 ++++++++++++++++++++++++++++++++++++++++++-
board/eNET/hardware.h | 16 +++++
include/asm-i386/ic/sc520.h | 20 ++++++-
5 files changed, 167 insertions(+), 30 deletions(-)
diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 29cf295..3dc63a8 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c
@@ -46,14 +46,6 @@ unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
void init_sc520_enet (void)
{
/* Set CPU Speed to 100MHz */
- sc520_mmcr->cpuctl = 0x01;
- gd->cpu_clk = 100000000;
-
- /* wait at least one millisecond */
- asm("movl $0x2000,%%ecx\n"
- "0: pushl %%ecx\n"
- "popl %%ecx\n"
- "loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
sc520_mmcr->dbctl = 0x11;
@@ -79,14 +71,6 @@ int board_init(void)
sc520_mmcr->gpwrw = 0x05; /* GP Write pulse width */
sc520_mmcr->gpwroff = 0x01; /* GP Write offset */
- sc520_mmcr->piodata15_0 = 0x0630; /* PIO15_PIO0 Data */
- sc520_mmcr->piodata31_16 = 0x2000; /* PIO31_PIO16 Data */
- sc520_mmcr->piodir31_16 = 0x2000; /* GPIO Direction */
- sc520_mmcr->piodir15_0 = 0x87b5; /* GPIO Direction */
- sc520_mmcr->piopfs31_16 = 0x0dfe; /* GPIO pin function 31-16 reg */
- sc520_mmcr->piopfs15_0 = 0x200a; /* GPIO pin function 15-0 reg */
- sc520_mmcr->cspfs = 0x00f8; /* Chip Select Pin Function Select */
-
sc520_mmcr->par[2] = 0x200713f8; /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
sc520_mmcr->par[3] = 0x2c0712f8; /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
sc520_mmcr->par[4] = 0x300711f8; /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
@@ -102,18 +86,10 @@ int board_init(void)
/* sc520_mmcr->par14 = 0x8bfff800; */ /* BOOTCS at 0x18000000 */
/* sc520_mmcr->par15 = 0x38201000; */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
- /* Disable Watchdog */
- sc520_mmcr->wdtmrctl = 0x3333;
- sc520_mmcr->wdtmrctl = 0xcccc;
- sc520_mmcr->wdtmrctl = 0x0000;
-
/* Chip Select Configuration */
- sc520_mmcr->bootcsctl = 0x0033;
sc520_mmcr->romcs1ctl = 0x0615;
sc520_mmcr->romcs2ctl = 0x0615;
- sc520_mmcr->adddecctl = 0x02;
- sc520_mmcr->uart1ctl = 0x07;
sc520_mmcr->sysarbctl = 0x06;
sc520_mmcr->sysarbmenb = 0x0003;
diff --git a/board/eNET/eNET_start.S b/board/eNET/eNET_start.S
index 1b07d62..9052935 100644
--- a/board/eNET/eNET_start.S
+++ b/board/eNET/eNET_start.S
@@ -21,12 +21,17 @@
* MA 02111-1307 USA
*/
+#include <asm/ic/sc520.h>
#include "hardware.h"
/* board early intialization */
.globl early_board_init
early_board_init:
- /* No 32-bit board specific initialisation */
+ /* Light up the LEDs */
+ movw $LED_LATCH_ADDRESS, %dx
+ movb $LED_1_BITMASK | LED_2_BITMASK, %al
+ outb %al, %dx
+
jmp *%ebp /* return to caller */
.globl show_boot_progress_asm
diff --git a/board/eNET/eNET_start16.S b/board/eNET/eNET_start16.S
index 48e4d83..31b33ec 100644
--- a/board/eNET/eNET_start16.S
+++ b/board/eNET/eNET_start16.S
@@ -27,8 +27,7 @@
* that is used by U-boot to its final destination.
*/
-/* #include <asm/ic/sc520_defs.h> */
-
+#include <asm/ic/sc520.h>
#include "hardware.h"
.text
@@ -45,6 +44,65 @@ board_init16:
movw $0xdf00, %ax
movw %ax, %ds
+ /* Disable Watchdog */
+ movl $SC520_WDTMRCTL, %edi
+ movw $0x3333, %ax
+ movw %ax, (%di)
+ movw $0xcccc, %ax
+ movw %ax, (%di)
+ movw $0x3333, %ax
+ movw %ax, (%di)
+
+ /* Set CPU to 100MHz Speed */
+ movb $0x01, %al
+ movl $SC520_CPUCTL, %edi
+ movb %al, (%di)
+
+ /* wait at least one millisecond */
+ movl $0x1000,%ecx
+cpuspddelay:
+ loop cpuspddelay
+
+ /* PIO15_PIO0 Data */
+ movl $SC520_PIODATA15_0, %edi
+ movw $0x0630, %ax
+ movw %ax, (%di)
+
+ /* PIO31_PIO16 Data */
+ movl $SC520_PIODATA31_16, %edi
+ movw $0x2000, %ax
+ movw %ax, (%di)
+
+ /* PIO Direction */
+ movl $SC520_PIODIR31_16, %edi
+ movw $0x2000, %ax
+ movw %ax, (%di)
+
+ /* PIO Direction */
+ movl $SC520_PIODIR15_0, %edi
+ movw $0x87b5, %ax
+ movw %ax, (%di)
+
+ /* PIO pin function 31-16 reg */
+ movl $SC520_PIOPFS31_16, %edi
+ movw $0x0dfe, %ax
+ movw %ax, (%di)
+
+ /* PIO pin function 15-0 reg */
+ movl $SC520_PIOPFS15_0, %edi
+ movw $0x200a, %ax
+ movw %ax, (%di)
+
+ /* Chip Select Pin Function Select */
+ movl $SC520_CSPFS, %edi
+ movw $0x00f8, %ax
+ movw %ax, (%di)
+
+ /* Setup Chip Select for Boot Flash */
+ movl $SC520_BOOTCSCTL, %edi
+ movw $0x0033, %ax
+ movl %eax, (%di)
+
/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
movl $0x00c0, %edi /* SC520_PAR14 */
movl $0x8bfff800, %eax /* TODO: Check this */
@@ -60,6 +118,74 @@ board_init16:
xorw %ax, %ax
movb %al, (%di)
+ /* Enable UART 1 */
+ movl $SC520_ADDDECCTL, %edi
+ movb $0x02, %al
+ movb %al, (%di)
+
+ /* Configure UART 1 - 9600 Baud 8N1 */
+ movl $SC520_UART1CTL, %edi
+ movb $0x07, %al
+ movb %al, (%di)
+
+ /* Set DLAB bit */
+ movw $(UART0_BASE + UART_LCR), %dx
+ movb $0x80, %al
+ outb %al, %dx
+
+ /* Set baudrate divisor (LSB) */
+ movw $(UART0_BASE + UART_DLL), %dx
+ movb $0x0c, %al
+ outb %al, %dx
+
+ /* Set baudrate divisor (MSB) */
+ movw $(UART0_BASE + UART_DLM), %dx
+ movb $0x00, %al
+ outb %al, %dx
+
+ /* clear DLAB; set 8 bits, no parity */
+ movw $(UART0_BASE + UART_LCR), %dx
+ movb $0x03, %al
+ outb %al, %dx
+
+ /* enable FIFO */
+ movw $(UART0_BASE + UART_FCR), %dx
+ movb $0x01, %al
+ outb %al, %dx
+
+ /* Set DTR and RTS active */
+ movw $(UART0_BASE + UART_MCR), %dx
+ movb $0x0b, %al
+ outb %al, %dx
+
+ /* clear line status */
+ movw $(UART0_BASE + UART_LSR), %dx
+ inb %dx, %al
+
+ /* read receive buffer */
+ movw $(UART0_BASE + UART_RBR), %dx
+ inb %dx, %al
+
+ /* set scratchpad */
+ movw $(UART0_BASE + UART_SCR), %dx
+ movb $0x00, %al
+ outb %al, %dx
+
+ /* Disable Interrupts */
+ movw $(UART0_BASE + UART_IER), %dx
+ movb $0x00, %al
+ outb %al, %dx
+
+ /* wait for the UART clock to settle */
+ movl $0x10000,%ecx
+uartdelay:
+ loop uartdelay
+
+ /* Light up the LEDs */
+ movw $LED_LATCH_ADDRESS, %dx
+ movb $LED_1_BITMASK, %al
+ outb %al, %dx
+
/* Disabe MMCR alias */
movw $0xfffc, %dx
movl $0x000000cb, %eax
diff --git a/board/eNET/hardware.h b/board/eNET/hardware.h
index 42474a6..5a8ae40 100644
--- a/board/eNET/hardware.h
+++ b/board/eNET/hardware.h
@@ -32,4 +32,20 @@
#define LED_TX_BITMASK 0x10
#define LED_ERR_BITMASK 0x20
+/* Serial Port Definitions */
+#define UART0_BASE 0x3f8
+
+#define UART_RBR 0x00
+#define UART_THR 0x00
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
#endif /* HARDWARE_H_ */
diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index 57c9904..723e38f 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB <daniel at omicron.se>.
+ * Daniel Engstr�m, Omicron Ceti AB <daniel at omicron.se>.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -134,7 +134,8 @@ typedef struct sc520_mmcr {
u16 gptmr0cnt; /* GP timer 0 count */
u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */
u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */
- u16 gptmr1ctl; /* GP timer 1 mode/control */
+ u16 gptmr1ctl; /*#define SC520_SWTMRMILLI 0x
+ GP timer 1 mode/control */
u16 gptmr1cnt; /* GP timer 1 count */
u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */
u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/
@@ -223,7 +224,8 @@ typedef struct sc520_mmcr {
u8 pad_0xd8d[0x03];
u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */
u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */
- u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */
+ u8 gpdmaexttc6; /* GP-DMA ch+#define SC520_CPUCTL 0x0001
+ annel 6 extender transfer count */
u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */
u8 pad_0xd94[0x4];
u8 gpdmabcctl; /* buffer chaining control */
@@ -256,11 +258,23 @@ extern volatile sc520_mmcr_t *sc520_mmcr;
#endif
/* MMCR Offsets (required for assembler code */
+#define SC520_CPUCTL 0x0001 /* CPU Control */
#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
+#define SC520_BOOTCSCTL 0x0050 /* BOOT Flaash Chip Select Control */
+#define SC520_ADDDECCTL 0x0080 /* Address Decode Control */
#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
+#define SC520_PIOPFS15_0 0x0c20 /* GPIO pin function 15-0 reg */
+#define SC520_PIOPFS31_16 0x0c22 /* GPIO pin function 31-16 reg */
+#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */
+#define SC520_PIODIR15_0 0x0c2a /* GPIO Direction */
+#define SC520_PIODIR31_16 0x0c2c /* GPIO Direction */
+#define SC520_PIODATA15_0 0x0c30 /* PIO15_PIO0 Data */
+#define SC520_PIODATA31_16 0x0c32 /* PIO31_PIO16 Data */
#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
+#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control */
+#define SC520_UART1CTL 0x0cc0 /* UART 1 Control */
/* MMCR Register bits (not all of them :) ) */
--
1.6.0.2.GIT
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