[U-Boot] [PATCH] Support for Embedtronics/MRFSA board.
Sami Kantoluoto
sami.kantoluoto at embedtronics.fi
Sat Aug 29 19:22:09 CEST 2009
Adds support for Embedtronics Oy's MRFSA board. Board features
AT91SAM9G20 controller, 64 MB of SDRAM, two 64 Mbit data flashses
(AT45DB321), SD card slot, GSM modem, GPS receiver, ZigBee (CC2420),
USB host ports, USB device port, two RS232 and one RS422/RS485 port,
two opto isolated inputs, two relays and bunch of leds.
This patch supports booting (e.g. Linux kernel) from following
media/interface:
- dataflash
- ethernet
- debug serial port
- SD/MMC
Signed-off-by: Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
---
Makefile | 13 +
board/embedtronics/mrfsa/Makefile | 60 +++++
board/embedtronics/mrfsa/config.mk | 1 +
board/embedtronics/mrfsa/iopins.h | 36 +++
board/embedtronics/mrfsa/ks8995ma.h | 255 ++++++++++++++++++
board/embedtronics/mrfsa/mrfsa.c | 481 ++++++++++++++++++++++++++++++++++
board/embedtronics/mrfsa/partition.c | 44 +++
board/embedtronics/mrfsa/watchdog.c | 62 +++++
common/console.c | 6 +
cpu/arm926ejs/at91/timer.c | 7 +-
drivers/net/macb.c | 4 +
include/asm-arm/mach-types.h | 13 +
include/configs/mrfsa.h | 197 ++++++++++++++
lib_arm/bootm.c | 13 +
14 files changed, 1191 insertions(+), 1 deletions(-)
create mode 100644 board/embedtronics/mrfsa/Makefile
create mode 100644 board/embedtronics/mrfsa/config.mk
create mode 100644 board/embedtronics/mrfsa/iopins.h
create mode 100644 board/embedtronics/mrfsa/ks8995ma.h
create mode 100644 board/embedtronics/mrfsa/mrfsa.c
create mode 100644 board/embedtronics/mrfsa/partition.c
create mode 100644 board/embedtronics/mrfsa/watchdog.c
create mode 100644 include/configs/mrfsa.h
diff --git a/Makefile b/Makefile
index 02393b6..b66421c 100644
--- a/Makefile
+++ b/Makefile
@@ -2751,6 +2751,19 @@ at91sam9g20ek_config : unconfig
fi;
@$(MKCONFIG) -a at91sam9260ek arm arm926ejs at91sam9260ek atmel at91
+mrfsa_dataflash_cs0_config \
+mrfsa_dataflash_cs1_config \
+mrfsa_config : unconfig
+ @mkdir -p $(obj)include
+ @if [ "$(findstring dataflash_cs1,$@)" ] ; then \
+ echo "#define CONFIG_SYS_USE_DATAFLASH_CS1 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+ else \
+ echo "#define CONFIG_SYS_USE_DATAFLASH_CS0 1" >>$(obj)include/config.h ; \
+ $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \
+ fi;
+ @$(MKCONFIG) -a mrfsa arm arm926ejs mrfsa embedtronics at91
+
at91sam9xeek_nandflash_config \
at91sam9xeek_dataflash_cs0_config \
at91sam9xeek_dataflash_cs1_config \
diff --git a/board/embedtronics/mrfsa/Makefile b/board/embedtronics/mrfsa/Makefile
new file mode 100644
index 0000000..9875638
--- /dev/null
+++ b/board/embedtronics/mrfsa/Makefile
@@ -0,0 +1,60 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop at leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2009
+# Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+# Embedtronics Oy <www.embedtronics.fi>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += mrfsa.o
+COBJS-y += partition.o
+COBJS-y += watchdog.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/embedtronics/mrfsa/config.mk b/board/embedtronics/mrfsa/config.mk
new file mode 100644
index 0000000..ff2cfd1
--- /dev/null
+++ b/board/embedtronics/mrfsa/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0x23f00000
diff --git a/board/embedtronics/mrfsa/iopins.h b/board/embedtronics/mrfsa/iopins.h
new file mode 100644
index 0000000..e7824dd
--- /dev/null
+++ b/board/embedtronics/mrfsa/iopins.h
@@ -0,0 +1,36 @@
+/*
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtronics Oy <www.embedtronics.fi>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _mrfsa_iopins_h
+#define _mrfsa_iopins_h
+
+/* some output pins: */
+#define PIN_SPI0_CSZB AT91_PIN_PB31 /* ZigBee slave select */
+#define PIN_SPI0_CSETH AT91_PIN_PB30 /* ethernet switch slave select */
+#define PIN_SPI0_CSSR AT91_PIN_PB17 /* shift register slave select */
+#define PIN_RESET_OUT AT91_PIN_PC14 /* resets switch, active low */
+#define PIN_NICEDOG AT91_PIN_PC4 /* wathcdog pin, must be pulsed
+ * periodically */
+
+#endif /* !_mrfsa_iopins_h */
diff --git a/board/embedtronics/mrfsa/ks8995ma.h b/board/embedtronics/mrfsa/ks8995ma.h
new file mode 100644
index 0000000..bfc7bad
--- /dev/null
+++ b/board/embedtronics/mrfsa/ks8995ma.h
@@ -0,0 +1,255 @@
+/*
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtronics Oy <www.embedtronics.fi>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _dev_spi_ks8995ma_h_
+#define _dev_spi_ks8995ma_h_ 1
+
+#define KS_OK 0
+#define KS_ERROR -1
+
+#define KS_RD_DATA 0x03
+#define KS_WR_DATA 0x02
+
+enum {
+ KS_ID0 = 0,
+ KS_ID1,
+ KS_GC0,
+ KS_GC1,
+ KS_GC2,
+ KS_GC3,
+ KS_GC4,
+ KS_GC5,
+ KS_GC6,
+ KS_GC7,
+ KS_GC8,
+ KS_GC9,
+
+ KS_P_CR0 = 0,
+ KS_P_CR1,
+ KS_P_CR2,
+ KS_P_CR3,
+ KS_P_CR4,
+ KS_P_CR5,
+ KS_P_CR6,
+ KS_P_CR7,
+ KS_P_CR8,
+ KS_P_CR9,
+ KS_P_CR10,
+ KS_P_CR11,
+ KS_P_CR12,
+ KS_P_CR13,
+ KS_P_SR0,
+ KS_P_CR14,
+
+ KS_P1 = 16,
+ KS_P2 = 32,
+ KS_P3 = 48,
+ KS_P4 = 64,
+ KS_P5 = 80,
+
+ KS_TOS_PCR0 = 96,
+ KS_TOS_PCR1,
+ KS_TOS_PCR2,
+ KS_TOS_PCR3,
+ KS_TOS_PCR4,
+ KS_TOS_PCR5,
+ KS_TOS_PCR6,
+ KS_TOS_PCR7,
+
+ KS_TOS_MAC0,
+ KS_TOS_MAC1,
+ KS_TOS_MAC2,
+ KS_TOS_MAC3,
+ KS_TOS_MAC4,
+ KS_TOS_MAC5,
+
+ KS_IAC0,
+ KS_IAC1,
+ KS_IDR8,
+ KS_IDR7,
+ KS_IDR6,
+ KS_IDR5,
+ KS_IDR4,
+ KS_IDR3,
+ KS_IDR2,
+ KS_IDR1,
+ KS_IDR0,
+
+ KS_DTS0,
+ KS_DTS1,
+ KS_DTC0,
+ KS_DTC1,
+ KS_ATC0,
+ KS_ATC1,
+ KS_ATS,
+};
+
+#define KS_ID0_FAMILY_ID 0xFF
+
+#define KS_ID1_CHIP_ID 0xF0
+#define KS_ID1_CHIP_ID_B 4
+#define KS_ID1_REV_ID 0x0E
+#define KS_ID1_START_SWITCH 0x01
+
+#define KS_GC0_802_1P_PRIO 0x70
+#define KS_GC0_802_1P_PRIO_B 4
+#define KS_GC0_ENABLE_PHY_MII 0x08
+#define KS_GC0_SHARED_BUFFER 0x04
+#define KS_GC0_UNH_MODE 0x02
+#define KS_GC0_LINK_CHANGE_AGE 0x01
+
+#define KS_GC1_PASS_ALL 0x80
+#define KS_GC1_PROMISCUOUS GC1_PASS_ALL
+#define KS_GC1_TX_FLOW_CTL_DISABLE 0x20
+#define KS_GC1_RX_FLOW_CTL_DISABLE 0x10
+#define KS_GC1_FRAME_LENGTH_CHK 0x08
+#define KS_GC1_AGING 0x04
+#define KS_GC1_FAST_AGING 0x02
+#define KS_GC1_AGGRESSIVE_BACK_OFF 0x01
+
+#define KS_GC2_UNICAST_VLAN_DISC 0x80
+#define KS_GC2_MULTICAST_STORM_DIS 0x40
+#define KS_GC2_BACK_PRESSURE_MODE 0x20
+#define KS_GC2_FAIR_MODE 0x10
+#define KS_GC2_NO_EXCESSIVE_DROP 0x08
+#define KS_GC2_HUGE_PACKET 0x04
+#define KS_GC2_DISABLE_LENGTH_CHK 0x02
+#define KS_GC2_PRIORITY_BUF 0x01
+
+#define KS_GC3_802_1Q_VLAN 0x80
+#define KS_GC3_IGMP_SNOOP 0x40
+#define KS_GC3_MII_DIRECT_MODE 0x20
+#define KS_GC3_MII_PRE_TAG 0x10
+#define KS_GC3_PRIO_SCHEME_SEL 0x0C
+#define KS_GC3_PRIO_SCHEME_HIGH 0x00
+#define KS_GC3_PRIO_SCHEME_10_1 0x04
+#define KS_GC3_PRIO_SCHEME_5_1 0x08
+#define KS_GC3_PRIO_SCHEME_2_1 0x0C
+#define KS_GC3_TAG_MASK 0x02
+#define KS_GC3_RX_AND_TX_SNIFF 0x01
+
+#define KS_GC4_MII_BACK_PRESSURE 0x80
+#define KS_GC4_MII_HALF_DUPLEX 0x40
+#define KS_GC4_MII_FLOW_ENA 0x20
+#define KS_GC4_MII_10_MBPS 0x10
+#define KS_GC4_NULL_VID_REPLACE 0x08
+#define KS_GC4_BCAST_STORM_PROT 0x07
+#define KS_GC4_BCAST_STORM_PROT_B 0
+
+#define KS_GC5_BCAST_STORM_PROT 0xFF
+#define KS_GC5_BCAST_STORM_PROT_B 0
+
+#define KS_GC9_PHY_PWR_SAVE 0x08
+#define KS_GC9_PHY_LED_MODE 0x02
+#define KS_GC9_TPID_MODE 0x01
+
+#define KS_P_CR0_BCAST_STORM_PROT_ENA 0x80
+#define KS_P_CR0_DIFFSERV_PRIO_ENA 0x40
+#define KS_P_CR0_802_1P_PRIO_ENA 0x20
+#define KS_P_CR0_CLASSIFICATION_ENA 0x10
+#define KS_P_CR0_TAG_INSERTION 0x04
+#define KS_P_CR0_TAG_REMOVAL 0x02
+#define KS_P_CR0_PRIO_ENA 0x01
+
+#define KS_P_CR1_SNIFFER_PORT 0x80
+#define KS_P_CR1_RECEIVE_SNIFF 0x40
+#define KS_P_CR1_TRANSMIT_SNIFF 0x20
+#define KS_P_CR1_PORT_VLAN_MASK 0x1F
+
+#define KS_P_CR2_VLAN_FILTERING 0x40
+#define KS_P_CR2_DISCARD_NON_PVID 0x20
+#define KS_P_CR2_FORCE_FLOW_CTL 0x10
+#define KS_P_CR2_BACK_PRESURE_ENA 0x08
+#define KS_P_CR2_TRANSMIT_ENA 0x04
+#define KS_P_CR2_RECEIVE_ENA 0x02
+#define KS_P_CR2_LEARNING_DIS 0x01
+
+#define KS_P_CR7_TX_LOW_PRIO_RATE 0xF0
+#define KS_P_CR7_TX_HIGH_PRIO_RATE 0x0F
+
+#define KS_P_CR10_RX_LOW_PRIO_RATE 0xF0
+#define KS_P_CR10_RX_HIGH_PRIO_RATE 0x0F
+
+#define KS_P_CR11_RX_DIFF_PRIO_ENA 0x80
+#define KS_P_CR11_RX_LOW_PRIO_RATE_ENA 0x40
+#define KS_P_CR11_RX_HIGH_PRIO_RATE_ENA 0x20
+#define KS_P_CR11_RX_LOW_PRIO_RATE_FLOW 0x10
+#define KS_P_CR11_RX_HIGH_PRIO_RATE_FLOW 0x08
+#define KS_P_CR11_TX_DIFF_PRIO_ENA 0x04
+#define KS_P_CR11_TX_LOW_PRIO_RATE_ENA 0x02
+#define KS_P_CR11_TX_HIGH_PRIO_RATE_ENA 0x01
+
+#define KS_P_CR12_AUTO_NEG_DIS 0x80
+#define KS_P_CR12_100_MBPS 0x40
+#define KS_P_CR12_FULL_DUPLEX 0x20
+#define KS_P_CR12_ADVERTISED_FLOW_CTL 0x10
+#define KS_P_CR12_ADVERTISED_100_FD 0x08
+#define KS_P_CR12_ADVERTISED_100_HD 0x04
+#define KS_P_CR12_ADVERTISED_10_FD 0x02
+#define KS_P_CR12_ADVERTISED_10_HD 0x01
+
+#define KS_P_CR13_LED_OFF 0x80
+#define KS_P_CR13_TX_DIS 0x40
+#define KS_P_CR13_RESTART_AN 0x20
+#define KS_P_CR13_FAR_END_DIS 0x10
+#define KS_P_CR13_PWR_DOWN 0x08
+#define KS_P_CR13_AUTO_MDI_MDI_X_DIS 0x04
+#define KS_P_CR13_FORCED_MDI 0x02
+#define KS_P_CR13_MAC_LOOPBACK 0x01
+
+#define KS_P_PS0_MDI 0x80
+#define KS_P_PS0_AN_DONE 0x40
+#define KS_P_PS0_LINK_GOOD 0x20
+#define KS_P_PS0_PARTNER_FLOW_CTL_CAP 0x10
+#define KS_P_PS0_PARTNER_100BT_FD_CAP 0x08
+#define KS_P_PS0_PARTNER_100BT_HD_CAP 0x04
+#define KS_P_PS0_PARTNER_10BT_FD_CAP 0x02
+#define KS_P_PS0_PARTNER_10BT_HD_CAP 0x01
+
+#define KS_P_CR14_PHY_LOOPBACK 0x80
+#define KS_P_CR14_REMOTE_LOOPBACK 0x40
+#define KS_P_CR14_PHY_ISOLATE 0x20
+#define KS_P_CR14_SOFT_RESET 0x10
+#define KS_P_CR14_FORCE_LINK 0x08
+#define KS_P_CR14_FAR_END_FAULT 0x01
+
+#define KS_IAC0_RD 0x10
+#define KS_IAC0_TBL 0x0C
+#define KS_IAC0_TBL_STATIC_MAC 0x00
+#define KS_IAC0_TBL_VLAN 0x04
+#define KS_IAC0_TBL_DYNAMIC_MAC 0x08
+#define KS_IAC0_TBL_MIB_COUNTER 0x0C
+#define KS_IAC0_ADDR_HIGH 0x03
+
+typedef union ks_ind_data {
+ u_int8_t Buf[9];
+ struct {
+ u_int8_t _reserved[(72 - 21) / 8];
+ u_int8_t Membership;
+#define KS_MEMB_VALID 0x20
+ u_int16_t VID;
+ } __attribute__ ((packed)) VLAN;
+} ks_ind_data_t;
+
+#endif /* !_dev_spi_ks8995ma_h_ */
diff --git a/board/embedtronics/mrfsa/mrfsa.c b/board/embedtronics/mrfsa/mrfsa.c
new file mode 100644
index 0000000..6420c4b
--- /dev/null
+++ b/board/embedtronics/mrfsa/mrfsa.c
@@ -0,0 +1,481 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtronics Oy <www.embedtronics.fi>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_spi.h>
+#include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+#if defined(CONFIG_RESET_PHY_R) || defined(CONFIG_MACB)
+#include <net.h>
+#include <netdev.h>
+#endif
+
+#include "ks8995ma.h"
+#include "iopins.h"
+
+#ifndef CONFIG_NO_VLANS
+#define CONFIG_NO_VLANS 1
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* ------------------------------------------------------------------------- */
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static void mrfsa_serial_hw_init (void)
+{
+#ifdef CONFIG_USART0
+ at91_set_A_periph (AT91_PIN_PB4, 1); /* TXD0 */
+ at91_set_A_periph (AT91_PIN_PB5, 0); /* RXD0 */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US0);
+#endif
+
+#ifdef CONFIG_USART1
+ at91_set_A_periph (AT91_PIN_PB6, 1); /* TXD1 */
+ at91_set_A_periph (AT91_PIN_PB7, 0); /* RXD1 */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US1);
+#endif
+
+#ifdef CONFIG_USART2
+ at91_set_A_periph (AT91_PIN_PB8, 1); /* TXD2 */
+ at91_set_A_periph (AT91_PIN_PB9, 0); /* RXD2 */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_US2);
+#endif
+
+#ifdef CONFIG_USART3 /* DBGU */
+ at91_set_A_periph (AT91_PIN_PB14, 0); /* DRXD */
+ at91_set_A_periph (AT91_PIN_PB15, 1); /* DTXD */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91_ID_SYS);
+#endif
+}
+
+static void mrfsa_spi_hw_init (void)
+{
+ unsigned long mode;
+
+ /* Enable clock for SPI */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
+
+ at91_set_A_periph (AT91_PIN_PA3, 1); /* SPI0_NPCS0 */
+ at91_set_B_periph (AT91_PIN_PC11, 1); /* SPI0_NPCS1 */
+ at91_set_gpio_output (PIN_SPI0_CSETH, 1); /* CSETH */
+ at91_set_gpio_output (PIN_SPI0_CSSR, 1); /* CSSR */
+ at91_set_gpio_output (PIN_SPI0_CSZB, 1); /* CSZB */
+
+ at91_set_A_periph (AT91_PIN_PA0, 0); /* SPI0_MISO */
+ at91_set_A_periph (AT91_PIN_PA1, 0); /* SPI0_MOSI */
+ at91_set_A_periph (AT91_PIN_PA2, 0); /* SPI0_SPCK */
+}
+
+static int spi_transfer (unsigned csr, unsigned cspin, const void *src,
+ void *dst, int len)
+{
+ unsigned long mode;
+ unsigned int timeout;
+
+ /* make sure SPI is not clocking data */
+ writel (AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
+ AT91_BASE_SPI + AT91_SPI_PTCR);
+
+ /* select slave parameters */
+ mode = readl (AT91_BASE_SPI + AT91_SPI_MR);
+ mode &= 0xfff0ffff;
+ writel (mode | (((0xf & ~(1 << csr)) << 16) & AT91_SPI_PCS),
+ AT91_BASE_SPI + AT91_SPI_MR);
+
+ /* Initialize the Transmit and Receive Pointer */
+ writel ((unsigned int)dst, AT91_BASE_SPI + AT91_SPI_RPR);
+ writel ((unsigned int)src, AT91_BASE_SPI + AT91_SPI_TPR);
+
+ /* Initialize the Transmit and Receive Counters */
+ writel (len, AT91_BASE_SPI + AT91_SPI_RCR);
+ writel (len, AT91_BASE_SPI + AT91_SPI_TCR);
+
+ /* arm simple, non interrupt dependent timer */
+ reset_timer_masked ();
+ timeout = 0;
+
+ /* select slave */
+ at91_set_gpio_value (cspin, 0);
+
+ /* transmit data */
+ writel (AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
+ while (!(readl (AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
+ ((timeout = get_timer_masked ()) < CONFIG_SYS_SPI_WRITE_TOUT)) ;
+ writel (AT91_SPI_TXTDIS + AT91_SPI_RXTDIS,
+ AT91_BASE_SPI + AT91_SPI_PTCR);
+
+ /* deselect slave */
+ at91_set_gpio_value (cspin, 1);
+
+ /* return error on failure */
+ if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
+ printf ("Error Timeout\n\r");
+ return -1;
+ }
+
+ /* success! */
+ return 0;
+}
+
+static int shreg_wr (unsigned sh1, unsigned sh2)
+{
+ unsigned char buf[2] = { sh1, sh2 };
+ return spi_transfer (3, PIN_SPI0_CSSR, buf, buf, 2);
+}
+
+#ifdef CONFIG_MACB
+static void mrfsa_macb_hw_init (void)
+{
+ /* Enable clock */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
+
+ /* Need to reset PHY -> 500ms reset */
+ at91_sys_write (AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN);
+
+ at91_sys_write (AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
+
+ /* Wait for end hardware reset */
+ while (!(at91_sys_read (AT91_RSTC_SR) & AT91_RSTC_NRSTL)) ;
+
+ /* Restore NRST value */
+ at91_sys_write (AT91_RSTC_MR, AT91_RSTC_KEY |
+ (AT91_RSTC_ERSTL & (0x0 << 8)) | AT91_RSTC_URSTEN);
+
+ at91_set_A_periph (AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
+ at91_set_A_periph (AT91_PIN_PA17, 0); /* ERXDV */
+ at91_set_A_periph (AT91_PIN_PA14, 0); /* ERX0 */
+ at91_set_A_periph (AT91_PIN_PA15, 0); /* ERX1 */
+ at91_set_A_periph (AT91_PIN_PA18, 0); /* ERXER */
+ at91_set_A_periph (AT91_PIN_PA16, 0); /* ETXEN */
+ at91_set_A_periph (AT91_PIN_PA12, 0); /* ETX0 */
+ at91_set_A_periph (AT91_PIN_PA13, 0); /* ETX1 */
+ at91_set_A_periph (AT91_PIN_PA21, 0); /* EMDIO */
+ at91_set_A_periph (AT91_PIN_PA20, 0); /* EMDC */
+
+#ifndef CONFIG_RMII
+ at91_set_B_periph (AT91_PIN_PA28, 0); /* ECRS */
+ at91_set_B_periph (AT91_PIN_PA29, 0); /* ECOL */
+ at91_set_B_periph (AT91_PIN_PA25, 0); /* ERX2 */
+ at91_set_B_periph (AT91_PIN_PA26, 0); /* ERX3 */
+ at91_set_B_periph (AT91_PIN_PA27, 0); /* ERXCK */
+ at91_set_B_periph (AT91_PIN_PA23, 0); /* ETX2 */
+ at91_set_B_periph (AT91_PIN_PA24, 0); /* ETX3 */
+ at91_set_B_periph (AT91_PIN_PA22, 0); /* ETXER */
+#endif
+ at91_macb_hw_init ();
+}
+#endif
+
+#ifdef CONFIG_ATMEL_MCI
+static void mrfsa_mci_hw_init (void)
+{
+ /* Enable clock */
+ at91_sys_write (AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI);
+
+ /* configure I/O */
+ at91_set_A_periph (AT91_PIN_PA6, 1);
+ at91_set_A_periph (AT91_PIN_PA7, 1);
+ at91_set_A_periph (AT91_PIN_PA8, 1);
+ at91_set_A_periph (AT91_PIN_PA9, 1);
+ at91_set_A_periph (AT91_PIN_PA10, 1);
+ at91_set_A_periph (AT91_PIN_PA11, 1);
+}
+#endif /* CONFIG_ATMEL_MCI */
+
+void mrfsa_wdt_init (void);
+
+int board_init (void)
+{
+ at91_set_gpio_output (PIN_RESET_OUT, 1); /* reset output */
+
+ /* Enable Ctrlc */
+ console_init_f ();
+
+ /* arch number of MRFSA-Board */
+ gd->bd->bi_arch_number = MACH_TYPE_MRFSA;
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ mrfsa_serial_hw_init ();
+
+#ifdef CONFIG_HW_WATCHDOG
+ mrfsa_wdt_init ();
+#endif
+
+#ifdef CONFIG_ATMEL_MCI
+ mrfsa_mci_hw_init ();
+#endif
+
+ mrfsa_spi_hw_init ();
+
+#ifdef CONFIG_MACB
+ mrfsa_macb_hw_init ();
+#endif
+
+ return 0;
+}
+
+int board_late_init (void)
+{
+ /* prepare CSR(3) for shift registers */
+ writel (AT91_SPI_NCPHA
+ | AT91_SPI_BITS_8
+ | ((AT91C_MASTER_CLOCK / 10000000) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR (3));
+
+ /* set shift registers */
+ shreg_wr(0xfe, 0x30);
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+static unsigned int ks_cmd (unsigned rdwr, unsigned reg, unsigned value,
+ unsigned *retvalue)
+{
+ unsigned char cmd[4] = { rdwr, reg, value }, rsp[4];
+ int ret;
+
+ ret = spi_transfer (2, PIN_SPI0_CSETH, cmd, rsp, 4);
+
+ if (ret != 0) {
+ return KS_ERROR;
+ }
+
+ if (retvalue) {
+ *retvalue = rsp[2];
+ }
+
+ return KS_OK;
+}
+
+static unsigned int ks_write_reg (unsigned reg, unsigned value)
+{
+ /*printf("%s: reg=%02x, value=%02x\n", __FUNCTION__, reg, value); */
+ return ks_cmd (KS_WR_DATA, reg, value, 0);
+}
+
+static unsigned int ks_read_reg (unsigned reg, unsigned *value)
+{
+ int ret = ks_cmd (KS_RD_DATA, reg, 0, value);
+ /*printf("%s: reg=%02x, value=%02x, ret=%d\n", __FUNCTION__, reg, *value, ret); */
+ return ret;
+}
+
+#ifndef CONFIG_NO_VLANS
+static unsigned int ks_ind_wr (unsigned table, unsigned addr,
+ const unsigned char *data, int dlen)
+{
+ int i, ret;
+
+ for (ret = KS_OK, i = 9 - dlen; ret == KS_OK && (i <= 8); i++) {
+ ret = ks_write_reg (KS_IDR8 + i, *data++);
+ }
+
+ if (ret == KS_OK) {
+ ret =
+ ks_write_reg (KS_IAC0,
+ (table & KS_IAC0_TBL) | ((addr >> 8) &
+ KS_IAC0_ADDR_HIGH));
+ }
+
+ if (ret == KS_OK) {
+ ret = ks_write_reg (KS_IAC1, addr & 0xff);
+ }
+
+ return ret;
+}
+
+static int ks_write_vtab (unsigned ndx, unsigned vid, unsigned fid,
+ unsigned members)
+{
+ unsigned char buf[3] = {
+ 0x20 | (members & 0x1F),
+ (fid << 4) | ((vid >> 8) & 0xF),
+ vid & 0xFF
+ };
+ return ks_ind_wr (KS_IAC0_TBL_VLAN, ndx, buf, 3);
+}
+#endif /* !CONFIG_NO_VLANS */
+
+static int ks_reset (void)
+{
+ static const struct {
+ unsigned char reg, value;
+ } table[] = {
+#ifndef CONFIG_NO_VLANS
+ {
+ KS_GC3, KS_GC3_802_1Q_VLAN}, {
+ KS_GC4, KS_GC4_MII_FLOW_ENA}, {
+ -1, 1}, {
+ -1, 2}, {
+ -1, 3}, {
+ -1, 4}, {
+ KS_GC9, 0}, {
+ KS_P1 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, {
+ KS_P1 + KS_P_CR1, 0x10}, {
+ KS_P1 + KS_P_CR2,
+ KS_P_CR2_VLAN_FILTERING |
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, {
+ KS_P1 + KS_P_CR3, 0}, {
+ KS_P1 + KS_P_CR4, 1}, {
+ KS_P2 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, {
+ KS_P2 + KS_P_CR1, 0x10}, {
+ KS_P2 + KS_P_CR2,
+ KS_P_CR2_VLAN_FILTERING |
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, {
+ KS_P2 + KS_P_CR3, 0}, {
+ KS_P2 + KS_P_CR4, 2}, {
+ KS_P3 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, {
+ KS_P3 + KS_P_CR1, 0x10}, {
+ KS_P3 + KS_P_CR2,
+ KS_P_CR2_VLAN_FILTERING |
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, {
+ KS_P3 + KS_P_CR3, 0}, {
+ KS_P3 + KS_P_CR4, 3}, {
+ KS_P4 + KS_P_CR0, KS_P_CR0_TAG_REMOVAL}, {
+ KS_P4 + KS_P_CR1, 0x10}, {
+ KS_P4 + KS_P_CR2,
+ KS_P_CR2_VLAN_FILTERING |
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA}, {
+ KS_P4 + KS_P_CR3, 0}, {
+ KS_P4 + KS_P_CR4, 4}, {
+ KS_P5 + KS_P_CR0, KS_P_CR0_TAG_INSERTION}, {
+ KS_P5 + KS_P_CR1, 0x0F}, {
+ KS_P5 + KS_P_CR2,
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA},
+#else /* CONFIG_NO_VLANS */
+ {
+ KS_GC3, 0}, {
+ KS_GC4, KS_GC4_MII_FLOW_ENA}, {
+ KS_GC9, 0},
+#if 0 /* defaults are good enough (normal switch) */
+ {
+ KS_P1 + KS_P_CR1, 0x1F}, {
+ KS_P1 + KS_P_CR2, KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA},
+ {
+ KS_P2 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, {
+ KS_P3 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, {
+ KS_P4 + KS_P_CR2, KS_P_CR2_LEARNING_DIS}, {
+ KS_P5 + KS_P_CR1, 0x01}, {
+ KS_P5 + KS_P_CR2,
+ KS_P_CR2_TRANSMIT_ENA | KS_P_CR2_RECEIVE_ENA},
+#endif
+#endif /* CONFIG_NO_VLANS */
+ };
+ unsigned long mode;
+ unsigned id0, id1;
+ int ret, i;
+
+ /* Reset switch */
+ at91_set_gpio_value (PIN_RESET_OUT, 0); /* enable /RESET_OUT */
+ udelay (1000); /* wait a bit */
+ at91_set_gpio_value (PIN_RESET_OUT, 1); /* disable /RESET_OUT */
+ udelay (20000); /* wait until switch is ready */
+
+ /* prepare CSR(2) for ethernet switch */
+ writel (AT91_SPI_NCPHA
+ | AT91_SPI_BITS_8
+ | ((AT91C_MASTER_CLOCK / 5000000) << 8),
+ AT91_BASE_SPI + AT91_SPI_CSR (2));
+
+ /* start configuring the switch */
+ if ((ret = ks_read_reg (KS_ID0, &id0)) == KS_OK
+ && (ret = ks_read_reg (KS_ID1, &id1)) == KS_OK) {
+ if (id0 == 0x95 && !(id1 & 0xF0)) {
+ printf ("KS8995MA detected\n");
+ } else {
+ printf ("KS8995MA NOT detected, id0=%02x, id1=%02x\n",
+ id0, id1);
+ }
+ }
+
+ /* configure.. */
+ for (i = 0; ret == KS_OK && i < (sizeof (table) / sizeof (table[0]));
+ i++) {
+ if (table[i].reg != (unsigned char)-1) {
+ ret = ks_write_reg (table[i].reg, table[i].value);
+#ifndef CONFIG_NO_VLANS
+ } else {
+ ret =
+ ks_write_vtab (table[i].value - 1, table[i].value,
+ table[i].value,
+ 0x10 | (1 << (table[i].value - 1)));
+#endif /* !CONFIG_NO_VLANS */
+ }
+ }
+
+ /* and finally start the switch: */
+ if (ret == KS_OK) {
+ ret = ks_write_reg (KS_ID1, KS_ID1_START_SWITCH);
+ }
+
+ return ret;
+}
+
+void reset_phy (void)
+{
+ /* configure switch */
+ ks_reset ();
+
+#ifdef CONFIG_MACB
+ /*
+ * Initialize ethernet HW addr prior to starting Linux,
+ * needed for nfsroot
+ */
+ eth_init (gd->bd);
+#endif
+}
+#endif /* !CONFIG_NO_VLANS */
+
+int board_eth_init (bd_t * bis)
+{
+ int rc = 0;
+#ifdef CONFIG_MACB
+ rc = macb_eth_initialize (0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
+#endif
+ return rc;
+}
diff --git a/board/embedtronics/mrfsa/partition.c b/board/embedtronics/mrfsa/partition.c
new file mode 100644
index 0000000..1f88f1b
--- /dev/null
+++ b/board/embedtronics/mrfsa/partition.c
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf at atmel.com>
+ *
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtronics Oy <www.embedtronics.fi>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+ {0x00000000, 0x000041FF, FLAG_PROTECT_CLEAR /*SET*/, 0, "Bootstrap"},
+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+ {0x00008400, 0x00041FFF, FLAG_PROTECT_CLEAR /*SET*/, 0, "U-Boot"},
+ {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
+ {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
+};
diff --git a/board/embedtronics/mrfsa/watchdog.c b/board/embedtronics/mrfsa/watchdog.c
new file mode 100644
index 0000000..95f5ac3
--- /dev/null
+++ b/board/embedtronics/mrfsa/watchdog.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtroncs Oy <www.embedtronics.fi>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MRFSA board level hardware watchdog.
+ */
+#include <common.h>
+#include <asm/arch/at91sam9260.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+#ifdef CONFIG_HW_WATCHDOG
+#include <watchdog.h>
+#include "iopins.h"
+
+static void at91_wdt_reset (void)
+{
+ at91_sys_write (AT91_WDT + AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
+}
+
+void hw_watchdog_reset (void)
+{
+ at91_set_gpio_value (PIN_NICEDOG, 1);
+ at91_wdt_reset ();
+ at91_set_gpio_value (PIN_NICEDOG, 0);
+}
+
+void mrfsa_wdt_init (void)
+{
+ at91_wdt_reset ();
+ at91_sys_write (AT91_WDT + AT91_WDT_MR,
+ AT91_WDT_WDD | AT91_WDT_WDV | AT91_WDT_WDRSTEN |
+ AT91_WDT_WDRPROC | AT91_WDT_WDDBGHLT);
+ at91_set_gpio_output (PIN_NICEDOG, 0);
+
+ hw_watchdog_reset ();
+}
+
+#endif /* CONFIG_HW_WATCHDOG */
diff --git a/common/console.c b/common/console.c
index 867c12c..fb6e409 100644
--- a/common/console.c
+++ b/common/console.c
@@ -311,6 +311,12 @@ int getc(void)
int tstc(void)
{
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_reset();
+#endif
+#ifdef CONFIG_WATCHDOG
+ watchdog_reset();
+#endif
#ifdef CONFIG_DISABLE_CONSOLE
if (gd->flags & GD_FLG_DISABLE_CONSOLE)
return 0;
diff --git a/cpu/arm926ejs/at91/timer.c b/cpu/arm926ejs/at91/timer.c
index 811bb3c..03fce54 100644
--- a/cpu/arm926ejs/at91/timer.c
+++ b/cpu/arm926ejs/at91/timer.c
@@ -83,7 +83,12 @@ int timer_init(void)
unsigned long long get_ticks(void)
{
ulong now = READ_TIMER;
-
+#ifdef CONFIG_HW_WATCHDOG
+ hw_watchdog_reset();
+#endif
+#ifdef CONFIG_WATCHDOG
+ watchdog_reset();
+#endif
if (now >= lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
timestamp += (now - lastinc);
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index c184353..9e2e771 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -291,6 +291,7 @@ static int macb_recv(struct eth_device *netdev)
return 0;
}
+#ifndef CONFIG_NO_PHY
static void macb_phy_reset(struct macb_device *macb)
{
struct eth_device *netdev = &macb->netdev;
@@ -403,6 +404,7 @@ static int macb_phy_init(struct macb_device *macb)
return 1;
}
}
+#endif /* CONFIG_NO_PHY */
static int macb_init(struct eth_device *netdev, bd_t *bd)
{
@@ -463,8 +465,10 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
#endif
#endif /* CONFIG_RMII */
+#ifndef CONFIG_NO_PHY
if (!macb_phy_init(macb))
return -1;
+#endif /* CONFIG_NO_PHY */
/* Enable TX and RX */
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 5293d67..316c05e 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -2241,6 +2241,7 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_OMAP3_WL_FF 2258
#define MACH_TYPE_SIMCOM 2259
#define MACH_TYPE_MCWEBIO 2260
+#define MACH_TYPE_MRFSA 2295
#ifdef CONFIG_ARCH_EBSA110
# ifdef machine_arch_type
@@ -28990,6 +28991,18 @@ extern unsigned int __machine_arch_type;
# define machine_is_mcwebio() (0)
#endif
+#ifdef CONFIG_MACH_MRFSA
+# ifdef machine_arch_type
+# undef machine_arch_type
+# define machine_arch_type __machine_arch_type
+# else
+# define machine_arch_type MACH_TYPE_MRFSA
+# endif
+# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA)
+#else
+# define machine_is_mrfsa() (0)
+#endif
+
/*
* These have not yet been registered
*/
diff --git a/include/configs/mrfsa.h b/include/configs/mrfsa.h
new file mode 100644
index 0000000..83ad18b
--- /dev/null
+++ b/include/configs/mrfsa.h
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2009
+ * Sami Kantoluoto <sami.kantoluoto at embedtronics.fi>
+ * Embedtronics Oy <www.embedtronics.fi>
+ *
+ * Configuation settings for the MRFSA board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* ARM asynchronous clock */
+#define AT91_MAIN_CLOCK 20000000 /* 20.000 MHz crystal */
+#define AT91C_MASTER_CLOCK 133333333 /* peripheral clock */
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
+
+#define AT91_CPU_NAME "AT91SAM9G20"
+#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC */
+
+#define CONFIG_ARCH_CPU_INIT
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_ATMEL_USART 1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3 1 /* USART 3 is DBGU */
+
+/* LED */
+#undef CONFIG_AT91_LED
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE 1
+#define CONFIG_BOOTP_BOOTPATH 1
+#define CONFIG_BOOTP_GATEWAY 1
+#define CONFIG_BOOTP_HOSTNAME 1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_MMC 1
+#define CONFIG_CMD_PING 1
+#define CONFIG_CMD_DHCP 1
+#define CONFIG_CMD_USB 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_EXT2 1
+
+#define CONFIG_MMC 1
+#define CONFIG_ATMEL_MCI 1
+
+#define CONFIG_DOS_PARTITION 1 /* support DOS partition table */
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM 0x20000000
+#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH 1
+#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
+#define AT91_SPI_CLK 15000000
+
+#define DATAFLASH_TCSS (0x22 << 16)
+#define DATAFLASH_TCHS (0x1 << 24)
+
+/* NAND flash - no nand flash on this board */
+#ifdef CONFIG_CMD_NAND
+#error No NAND FLASH
+#endif
+#define CONFIG_SYS_NO_NAND 1
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH 1
+
+/* Ethernet */
+#define CONFIG_MACB 1
+#define CONFIG_NO_PHY 1
+#undef CONFIG_RMII
+#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_RETRY_COUNT 20
+#define CONFIG_RESET_PHY_R 1
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g20"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_STORAGE 1
+
+#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END 0x23e00000
+
+#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
+
+/* bootstrap + u-boot + env + linux in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH 1
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mmcblk0p1 rootwait rw"
+
+#elif CONFIG_SYS_USE_DATAFLASH_CS1
+
+/* bootstrap + u-boot + env + linux in dataflash on CS1 */
+#define CONFIG_ENV_IS_IN_DATAFLASH 1
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
+#define CONFIG_ENV_OFFSET 0x4200
+#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE 0x4200
+#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
+#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
+ "root=/dev/mmcblk0p1 rootwait rw"
+
+#endif
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT "U-Boot> "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMDLINE_EDITING 1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE (32*1024) /* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#define CONFIG_HW_WATCHDOG 1 /* we've hardware watchdog */
+
+#define BOARD_LATE_INIT 1
+#define MMCI_BASE AT91SAM9260_BASE_MCI
+
+#endif
diff --git a/lib_arm/bootm.c b/lib_arm/bootm.c
index 128b7e3..e882d9b 100644
--- a/lib_arm/bootm.c
+++ b/lib_arm/bootm.c
@@ -27,6 +27,11 @@
#include <u-boot/zlib.h>
#include <asm/byteorder.h>
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+#include <watchdog.h>
+#endif
+
+
DECLARE_GLOBAL_DATA_PTR;
#if defined (CONFIG_SETUP_MEMORY_TAGS) || \
@@ -123,8 +128,16 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
}
#endif
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+
cleanup_before_linux ();
+#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
+ WATCHDOG_RESET();
+#endif
+
theKernel (0, machid, bd->bi_boot_params);
/* does not return */
--
1.6.0.4
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