[U-Boot] [PATCH V3 3/3] Add support for the LaCie ED Mini V2 board
Albert Aribaud
albert.aribaud at free.fr
Tue Dec 1 21:27:05 CET 2009
This patch adds support for the LaCie ED Mini V2 product
which is based on the Marvell Orion5x SoC.
Current support is limited to console and Flash.
Flash support uses LEGACY as the Macronix 29LV400
used on ED Mini V2 is not 100% CFI compliant.
Signed-off-by: Albert Aribaud <albert.aribaud at free.fr>
---
MAINTAINERS | 4 +
MAKEALL | 1 +
Makefile | 3 +
board/LaCie/edminiv2/Makefile | 58 ++++++
board/LaCie/edminiv2/config.mk | 27 +++
board/LaCie/edminiv2/edminiv2.c | 100 +++++++++++
board/LaCie/edminiv2/edminiv2.h | 59 ++++++
board/LaCie/edminiv2/lowlevel_init.S | 324 ++++++++++++++++++++++++++++++++++
include/configs/edminiv2.h | 148 ++++++++++++++++
9 files changed, 724 insertions(+), 0 deletions(-)
create mode 100644 board/LaCie/edminiv2/Makefile
create mode 100644 board/LaCie/edminiv2/config.mk
create mode 100644 board/LaCie/edminiv2/edminiv2.c
create mode 100644 board/LaCie/edminiv2/edminiv2.h
create mode 100644 board/LaCie/edminiv2/lowlevel_init.S
create mode 100644 include/configs/edminiv2.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d70a9d2..93e57f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -512,6 +512,10 @@ Unknown / orphaned boards:
# Board CPU #
#########################################################################
+Albert ARIBAUD <albert.aribaud at free.fr>
+
+ edminiv2 ARM926EJS (Orion5x SoC)
+
Rowel Atienza <rowel at diwalabs.com>
armadillo ARM720T
diff --git a/MAKEALL b/MAKEALL
index d63c5c2..f7b2a24 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -548,6 +548,7 @@ LIST_ARM9=" \
cp926ejs \
cp946es \
cp966 \
+ edminiv2 \
imx27lite \
lpd7a400 \
mv88f6281gtw_ge \
diff --git a/Makefile b/Makefile
index bcb3fe9..83b35b5 100644
--- a/Makefile
+++ b/Makefile
@@ -2951,6 +2951,9 @@ davinci_dm365evm_config : unconfig
davinci_dm6467evm_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci
+edminiv2_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm926ejs $(@:_config=) LaCie orion5x
+
imx27lite_config: unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
new file mode 100644
index 0000000..d2bb6fe
--- /dev/null
+++ b/board/LaCie/edminiv2/Makefile
@@ -0,0 +1,58 @@
+#
+# Copyright (C) 2009 Albert ARIBAUD <albrt.aribaud at free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := edminiv2.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/LaCie/edminiv2/config.mk b/board/LaCie/edminiv2/config.mk
new file mode 100644
index 0000000..e2477c9
--- /dev/null
+++ b/board/LaCie/edminiv2/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2009 Albert ARIBAUD <albrt.aribaud at free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00600000
diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
new file mode 100644
index 0000000..31ecb11
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albrt.aribaud at free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+#include "edminiv2.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The ED Mini V2 is equipped with a Macronix MXLV400CB FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+ int sect;
+
+ if (base != CONFIG_SYS_FLASH_BASE)
+ return 0;
+
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+ info->start[sect] = base+info->size;
+ info->size += sectsz[sect];
+ }
+ info->flash_id = 0x01000000;
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->buffer_size = 0;
+ info->erase_blk_tout = 1000;
+ info->write_tout = 10;
+ info->buffer_write_tout = 300;
+ info->vendor = CFI_CMDSET_AMD_LEGACY;
+ info->cmd_reset = 0xF0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->manufacturer_id = 0x22;
+ info->device_id = 0xBA;
+ info->device_id2 = 0;
+ info->ext_addr = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->addr_unlock1 = 0x00000aaa;
+ info->addr_unlock2 = 0x00000555;
+ info->name = "MX29LV400CB";
+
+ return 1;
+}
+#endif /* CONFIG_SYS_FLASH_CFI */
+
+int board_init(void)
+{
+ /* arch number of board */
+ gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = orion5x_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
+ gd->bd->bi_dram[i].size = orion5x_sdram_bs(i);
+ }
+ return 0;
+}
+
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 0000000..0a294d2
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albrt.aribaud at free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_H
+#define __EDMINIV2_H
+
+/*
+ * Internal register base - Linux expects 0xf1000000
+ */
+
+#define EDMINIV2_INTERNAL_BASE 0xf1000000
+
+/*
+ * MPPs:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 0 for others
+ */
+
+#define EDMINIV2_MPP0_7 0x00000003
+#define EDMINIV2_MPP8_15 0x55550000
+#define EDMINIV2_MPP16_23 0x00000000
+
+/*
+ * GPIOs:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Default is LED ON
+ */
+
+#define EDMINIV2_OE 0x03fcffff
+#define EDMINIV2_OE_VAL 0x00020000
+
+#endif /* __EDMINIV2_H */
diff --git a/board/LaCie/edminiv2/lowlevel_init.S b/board/LaCie/edminiv2/lowlevel_init.S
new file mode 100644
index 0000000..891423f
--- /dev/null
+++ b/board/LaCie/edminiv2/lowlevel_init.S
@@ -0,0 +1,324 @@
+/*******************************************************************************
+Copyright (c) Albert ARIBAUD <albert.aribaud at free.fr>
+Redistributed under GPLv2, pursuant to the licensing terms
+if the original Marvell U-boot code which is:
+Copyright (C) Marvell International Ltd. and its affiliates
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+
+*******************************************************************************/
+
+#include "edminiv2.h"
+
+/*
+ * Configuration values for SDRAM access setup
+ */
+
+#define SDRAM_CONFIG 0x3148400
+#define SDRAM_MODE 0x62
+#define SDRAM_CONTROL 0x4041000
+#define SDRAM_TIME_CTRL_LOW 0x11602220
+#define SDRAM_TIME_CTRL_HI 0x40c
+#define SDRAM_OPEN_PAGE_EN 0x0
+/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
+#define SDRAM_BANK0_SIZE 0x3ff0001
+#define SDRAM_ADDR_CTRL 0x10
+
+#define SDRAM_OP_NOP 0x05
+#define SDRAM_OP_SETMODE 0x03
+
+#define SDRAM_PAD_CTRL_WR_EN 0x80000000
+#define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
+#define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
+#define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
+
+/*
+ * For Guideline MEM-3 - Drive Strength value
+ */
+
+#define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
+#define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
+
+/*
+ * For Guideline MEM-4 - DQS Reference Delay Tuning
+ */
+
+#define MSAR_ARMDDRCLCK_MASK 0x000000f0
+#define MSAR_ARMDDRCLCK_H_MASK 0x00000100
+
+#define MSAR_ARMDDRCLCK_333_167 0x00000000
+#define MSAR_ARMDDRCLCK_500_167 0x00000030
+#define MSAR_ARMDDRCLCK_667_167 0x00000060
+#define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
+#define MSAR_ARMDDRCLCK_400_200 0x00000010
+#define MSAR_ARMDDRCLCK_600_200 0x00000050
+#define MSAR_ARMDDRCLCK_800_200 0x00000070
+
+#define FTDLL_DDR1_166MHZ 0x0047F001
+
+#define FTDLL_DDR1_200MHZ 0x0044D001
+
+/*
+ * MPPs:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ * MPP16 to MPP19, mode 0 for others
+ */
+
+#define EDMINIV2_MPP0_7 0x00000003
+#define EDMINIV2_MPP8_15 0x55550000
+#define EDMINIV2_MPP16_19 0x00005555
+
+/*
+ * GPIOs:
+ * All GPIOs are inputs except:
+ * - MPP16: Power LED control (0 = On, 1 = Off)
+ * - MPP17: Power LED control select (0 = CPLD, 1 = GPIO16)
+ * Default setting puts LED under CPLD control.
+ */
+
+#define EDMINIV2_GPIO_OUT_ENABLE 0x03FCFFFF
+
+/*
+ * Low-level init happens right after start.S has switched to SVC32,
+ * flushed and disabled caches and disabled MMU. We're still running
+ * from the boot chip select, so the first thing we should do is set
+ * up RAM for us to relocate into.
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+ /* Use 'r4 as the base for internal register accesses */
+ ldr r4, =EDMINIV2_INTERNAL_BASE
+
+ /* move internal registers from the default 0xD0000000
+ * to their intended location of 0xf1000000 */
+ ldr r3, =0xD0000000
+ add r3, r3, #0x20000
+ str r4, [r3, #0x80]
+
+ /* Use R3 as the base for Device Bus registers */
+ add r3, r4, #0x10000
+
+ /* init MPPs */
+ ldr r6, =EDMINIV2_MPP0_7
+ str r6, [r3, #0x000]
+ ldr r6, =EDMINIV2_MPP8_15
+ str r6, [r3, #0x004]
+ ldr r6, =EDMINIV2_MPP16_23
+ str r6, [r3, #0x050]
+
+ /* init GPIOs */
+ ldr r6, =EDMINIV2_GPIO_OUT_ENABLE
+ str r6, [r3, #0x104]
+
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =0x00000001
+ str r6, [r3, #0x480]
+
+ /* Use R3 as the base for PCI registers */
+ add r3, r4, #0x31000
+
+ /* Disable arbiter */
+ ldr r6, =0x00000030
+ str r6, [r3, #0xd00]
+
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ str r6, [r3, #0x504]
+ str r6, [r3, #0x50C]
+ str r6, [r3, #0x514]
+ str r6, [r3, #0x51C]
+
+ /* 1) Configure SDRAM */
+ ldr r6, =SDRAM_CONFIG
+ str r6, [r3, #0x400]
+
+ /* 2) Set SDRAM Control reg */
+ ldr r6, =SDRAM_CONTROL
+ str r6, [r3, #0x404]
+
+ /* 3) Write SDRAM address control register */
+ ldr r6, =SDRAM_ADDR_CTRL
+ str r6, [r3, #0x410]
+
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r6, =SDRAM_BANK0_SIZE
+ str r6, [r3, #0x504]
+ /* keep other banks disabled */
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r6, =SDRAM_OPEN_PAGE_EN
+ str r6, [r3, #0x414]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r6, =SDRAM_TIME_CTRL_LOW
+ str r6, [r3, #0x408]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r6, =SDRAM_TIME_CTRL_HI
+ str r6, [r3, #0x40C]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to its new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ ldr r6, =SDRAM_OP_NOP
+ str r6, [r3, #0x418]
+
+ /* 8.2 poll SDRAM operation until back in 'normal' mode. */
+1:
+ ldr r6, [r3, #0x418]
+ cmp r6, #0
+ bne 1b
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r6, =SDRAM_MODE
+ str r6, [r3, #0x41C]
+
+ /* 8.4 Set new mode */
+ ldr r6, =SDRAM_OP_SETMODE
+ str r6, [r3, #0x418]
+
+ /* 8.5 poll SDRAM operation until back in 'normal' mode. */
+2:
+ ldr r6, [r3, #0x418]
+ cmp r6, #0
+ bne 2b
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ ldr r6, [r3, #0x4C0]
+
+ /* Set Bit [31] to make the register writable */
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C0]
+
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r1
+ str r6, [r3, #0x4C0]
+
+ /* DDR SDRAM Data Pads Calibration */
+ ldr r6, [r3, #0x4C4]
+
+ /* Set Bit [31] to make the register writable */
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C4]
+
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r6
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26
+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r1
+
+ str r6, [r3, #0x4C4]
+
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
+
+ /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
+ ldr r6, [r3, #0x4C0]
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C0]
+
+ /* Correct strength and disable writes again */
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+ orr r6, r6, r1
+ str r6, [r3, #0x4C0]
+
+ /* Enable writes to DDR SDRAM Data Pads Calibration register */
+ ldr r6, [r3, #0x4C4]
+ orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ str r6, [r3, #0x4C4]
+
+ /* Correct strength and disable writes again */
+ bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
+ bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
+ orr r6, r6, r1
+ str r6, [r3, #0x4C4]
+
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ /* Get the "sample on reset" register for the DDR frequancy */
+ ldr r3, =0x10000
+ ldr r6, [r3, #0x010]
+ ldr r1, =MSAR_ARMDDRCLCK_MASK
+ and r1, r6, r1
+
+ ldr r6, =FTDLL_DDR1_166MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_333_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_500_167
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_667_167
+ beq 3f
+
+ ldr r6, =FTDLL_DDR1_200MHZ
+ cmp r1, #MSAR_ARMDDRCLCK_400_200_1
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_400_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_600_200
+ beq 3f
+ cmp r1, #MSAR_ARMDDRCLCK_800_200
+ beq 3f
+
+ ldr r6, =0
+
+3:
+ /* Use R3 as the base for DRAM registers */
+ add r3, r4, #0x01000
+
+ ldr r2, [r3, #0x484]
+ orr r2, r2, r6
+ str r2, [r3, #0x484]
+
+ /* Return to U-boot via saved link register */
+ mov pc, lr
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
new file mode 100644
index 0000000..6da594f
--- /dev/null
+++ b/include/configs/edminiv2.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_EDMINIV2_H
+#define _CONFIG_EDMINIV2_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING " EDMiniV2"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON 1 /* CPU Core subversion */
+#define CONFIG_ORION5X 1 /* SOC Family Name */
+#define CONFIG_88F5182 1 /* SOC Name */
+#define CONFIG_MACH_EDMINIV2 1 /* Machine type */
+
+/*
+ * CLKs configurations
+ */
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_LEGACY
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_BASE 0xfff80000
+#define CONFIG_SYS_FLASH_SECTSZ \
+ {16384, 8192, 8192, 32768, \
+ 65536, 65536, 65536, 65536, 65536, 65536, 65536}
+
+/* auto boot */
+#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "EDMiniV2> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+/*
+ * Disabling some default commands for staggered bring-up
+ */
+#undef CONFIG_CMD_BOOTD /* no bootd since no net */
+#undef CONFIG_CMD_NET /* no net since no eth */
+#undef CONFIG_CMD_NFS /* no NFS since no net */
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_DRAM_BANK0_SIZE (64*1024*1024)
+
+#define CONFIG_STACKSIZE 0x00100000
+#define CONFIG_SYS_LOAD_ADDR 0x00800000
+#define CONFIG_SYS_MEMTEST_START 0x00400000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
+#define CONFIG_SYS_MAXARGS 16
+
+#endif /* _CONFIG_EDMINIV2_H */
--
1.6.4.4
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