[U-Boot] [PATCH] NAND: DaVinci: Update 4 bit ECC correction

[s-paulraj at ti.com]

From: Sandeep Paulraj <s-paulraj at ti.com>

There was a bug in the 4 bit ECC calculation routine
in the DaVinci NAND driver. This becomes prominent
when we use 4K page size NAND devices.
This is a fix for the issue.

Signed-off-by: Sandeep Paulraj <s-paulraj at ti.com>
---
 drivers/mtd/nand/davinci_nand.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 41a9568..68a0e15 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -388,6 +388,17 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	emif_regs->NANDFCR |= 1 << 13;
 
 	/*
+	 * ECC_STATE in NANDFSR register reads 0x3 (Error correction complete)
+	 * immediately after setting the 4BITECC_ADD_CALC_START bit. So if we
+	 * begin trying to poll for the state, we may fall right out of your
+	 * loop without any of the correction calculations having taken place.
+	 * So wait till ECC_STATE reads less than 4.
+	 */
+	do {
+		val = ((emif_regs->NANDFSR >> 8) & 0xf);
+	} while (val < 4);
+
+	/*
 	 * Wait for the corr_state field (bits 8 to 11)in the
 	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
 	 */
-- 
1.6.0.4