[U-Boot] [PATCH] ARM: Add support for edb93xx boards

Matthias Kaehlcke matthias at kaehlcke.net
Sun Dec 6 15:54:44 CET 2009


Add support for the Cirrus EP93xx platform and EDB93xx boards

Signed-off-by: Matthias Kaehlcke <matthias at kaehlcke.net>

---

This work is based on the patch from Dominic Rath for the Olimex
CS-E9301 board
(http://article.gmane.org/gmane.linux.ports.arm.cirrus/722) and some
input from a patch for EDB93xx boards from Herbert Valerio Riedel
(http://stud3.tuwien.ac.at/~e9725348/Projects/ep93xx/u-boot-1.2.0-edb93xx_support.diff)

For now it has been tested on boards based on the EDB9301 and
EDB9307A design.

 Makefile                             |   36 ++
 board/edb93xx/Makefile               |   51 ++
 board/edb93xx/config.mk              |    1 +
 board/edb93xx/edb93xx.c              |  120 +++++
 board/edb93xx/flash_cfg.S            |   42 ++
 board/edb93xx/pll_cfg.S              |   93 ++++
 board/edb93xx/sdram_cfg.S            |  217 +++++++++
 board/edb93xx/u-boot.lds             |   59 +++
 cpu/arm920t/ep93xx/Makefile          |   55 +++
 cpu/arm920t/ep93xx/cpu.c             |  125 +++++
 cpu/arm920t/ep93xx/eth.c             |  876 ++++++++++++++++++++++++++++++++++
 cpu/arm920t/ep93xx/lowlevel_init.S   |   74 +++
 cpu/arm920t/ep93xx/speed.c           |  120 +++++
 cpu/arm920t/ep93xx/timer.c           |  163 +++++++
 include/asm-arm/arch-ep93xx/ep93xx.h |  868 +++++++++++++++++++++++++++++++++
 include/common.h                     |    6 +
 include/configs/edb93xx.h            |  235 +++++++++
 17 files changed, 3141 insertions(+), 0 deletions(-)

diff --git a/Makefile b/Makefile
index bcb3fe9..8ddd19d 100644
--- a/Makefile
+++ b/Makefile
@@ -2429,6 +2429,42 @@ TQM834x_config:	unconfig
 vme8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
 
+edb93xx_config \
+edb9301_config \
+edb9302_config \
+edb9302a_config \
+edb9307_config \
+edb9307a_config \
+edb9315a_config: unconfig
+	@if [ "$(findstring 01_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9301" >> $(obj)include/config.h ; \
+	elif [ "$(findstring 02_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9302"  >> $(obj)include/config.h ; \
+	elif [ "$(findstring 02a_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9302A" >> $(obj)include/config.h ; \
+	elif [ "$(findstring 07_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9307"  >> $(obj)include/config.h ; \
+	elif [ "$(findstring 07a_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9307A" >> $(obj)include/config.h ; \
+	elif [ "$(findstring 12_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9312"  >> $(obj)include/config.h ; \
+	elif [ "$(findstring 15_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9315"  >> $(obj)include/config.h ; \
+	elif [ "$(findstring 15a_,$@)" ] ; then \
+		echo "#define        CONFIG_EDB9315A" >> $(obj)include/config.h ; \
+	fi ;
+
+	@$(MKCONFIG) -a edb93xx arm arm920t edb93xx NULL ep93xx
+	@if [ "$(findstring 01_,$@)" ] || [ "$(findstring 02_,$@)" ]; then \
+		echo "TEXT_BASE = 0x05400000" >> $(obj)include/config.mk ; \
+	elif [ "$(findstring 02a_,$@)" ]; then \
+		echo "TEXT_BASE = 0xc5400000" >> $(obj)include/config.mk ; \
+	elif [ "$(findstring 07_,$@)" ] || [ "$(findstring 12_,$@)" ] || [ "$(findstring 15_,$@)" ]; then \
+		echo "TEXT_BASE = 0x01f00000" >> $(obj)include/config.mk ; \
+	elif [ "$(findstring 07a_,$@)" ] || [ "$(findstring 15a_,$@)" ]; then \
+		echo "TEXT_BASE = 0xc1f00000" >> $(obj)include/config.mk ; \
+	fi ;
+
 #########################################################################
 ## MPC85xx Systems
 #########################################################################
diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile
new file mode 100644
index 0000000..57c109d
--- /dev/null
+++ b/board/edb93xx/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= edb93xx.o
+SOBJS	:= flash_cfg.o pll_cfg.o sdram_cfg.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk
new file mode 100644
index 0000000..dffa83e
--- /dev/null
+++ b/board/edb93xx/config.mk
@@ -0,0 +1 @@
+LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds
\ No newline at end of file
diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c
new file mode 100644
index 0000000..fdbb956
--- /dev/null
+++ b/board/edb93xx/edb93xx.c
@@ -0,0 +1,120 @@
+/*
+ * vim: set ts=4 sw=4 noet:
+ */
+/*
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * (C) Copyright 2002 2003
+ * Network Audio Technologies, Inc. <www.netaudiotech.com>
+ * Adam Bezanson <bezanson at netaudiotech.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	icache_enable();
+
+#ifdef USE_920T_MMU
+	dcache_enable();
+#endif
+
+	/* set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
+	 * 14.7456/2 MHz
+	 */
+	uint32_t value = readl(SYSCON_PWRCNT);
+	value |= SYSCON_PWRCNT_UART_BAUD;
+	writel(value, SYSCON_PWRCNT);
+
+	/* Machine number, as defined in linux/arch/arm/tools/mach-types
+	 */
+#ifdef CONFIG_EDB9301
+	gd->bd->bi_arch_number = 462;
+#elif defined(CONFIG_EDB9302)
+	gd->bd->bi_arch_number = 538;
+#elif defined(CONFIG_EDB9302A)
+	gd->bd->bi_arch_number = 1127;
+#elif (defined CONFIG_EDB9307)
+	gd->bd->bi_arch_number = 607;
+#elif (defined CONFIG_EDB9307A)
+	gd->bd->bi_arch_number = 1128;
+#elif defined(CONFIG_EDB9312)
+	gd->bd->bi_arch_number = 451;
+#elif defined(CONFIG_EDB9315)
+	gd->bd->bi_arch_number = 463;
+#elif defined(CONFIG_EDB9315A)
+	gd->bd->bi_arch_number = 772;
+#endif
+
+	/* adress of boot parameters
+	 */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* We have a console
+	 */
+	gd->have_console = 1;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+	unsigned int *src, *dst;
+	int i;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE_1;
+
+#ifdef PHYS_SDRAM_2
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_SIZE_2;
+#endif
+
+#ifdef PHYS_SDRAM_3
+	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
+	gd->bd->bi_dram[2].size = PHYS_SDRAM_SIZE_3;
+#endif
+
+#ifdef PHYS_SDRAM_4
+	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
+	gd->bd->bi_dram[3].size = PHYS_SDRAM_SIZE_4;
+#endif
+
+#ifdef CONFIG_EDB93XX_SDCS3
+	dst = (unsigned int *)0x00000000;
+#else
+	dst = (unsigned int *)0xc0000000;
+#endif
+
+	/* copy exception vectors */
+	src = (unsigned int *)_armboot_start;
+
+	for (i = 0; i < 16; i++)
+		*dst++ = *src++;
+
+	return 0;
+}
diff --git a/board/edb93xx/flash_cfg.S b/board/edb93xx/flash_cfg.S
new file mode 100644
index 0000000..aa61a3c
--- /dev/null
+++ b/board/edb93xx/flash_cfg.S
@@ -0,0 +1,42 @@
+/*
+ * Flash setup for Olimex CS-E9302 board
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath at gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <asm/arch/ep93xx.h>
+
+.globl flash_cfg
+flash_cfg:
+	/* configure smc bank 6 (Intel TE28F128J3D75 Strata Flash)
+	 * ebibrkdis: 0, mw: 0x1 (16 bit), pme: 0, wp: 0, wst2: 2(+1),
+	 * wst1: 5(+1), rble: 1, idcy: 2(+1)
+	 * TODO: we don't enable page mode for now
+	 */
+	ldr r0, =SMC_BCR6
+
+	ldr r1, =(2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
+		  SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | 1 << SMC_BCR_MW_SHIFT)
+
+	str r1, [r0]
+
+	mov pc, lr
diff --git a/board/edb93xx/pll_cfg.S b/board/edb93xx/pll_cfg.S
new file mode 100644
index 0000000..ae69a7d
--- /dev/null
+++ b/board/edb93xx/pll_cfg.S
@@ -0,0 +1,93 @@
+/*
+ * PLL setup for Cirrus EDB93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath at gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+.globl pll_cfg
+pll_cfg:
+	/* configure PLL1 */
+	ldr r0, =SYSCON_CLKSET1
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \
+	defined(CONFIG_EDB9302A)
+	/* fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
+	 * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
+	 * pll1_x2: 331776000.000000, pll1_out: 331776000.000000
+	 */
+	ldr r1, =(7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+		  8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+		  19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+		  1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+		  3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+		  SYSCON_CLKSET1_NBYP1 | \
+		  1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+	defined(CONFIG_EDB9315A)
+	/* fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2
+	 * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000,
+	 * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000
+	 */
+	ldr r1, =(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+		  30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+		  20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+		  1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \
+		  2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \
+		  SYSCON_CLKSET1_NBYP1 | \
+		  1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
+#endif
+	str r1, [r0]
+
+	/* flush the pipeline
+	 * writing to CLKSET1 causes the EP9302 to enter standby for between
+	 * 8 ms to 16 ms, until PLL1 stabilizes
+	 */
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	/* configure PLL2
+	 * usb_div: 4, nbyp2: 1, pll2_en: 1
+	 * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
+	 * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
+	 */
+	ldr r0, =SYSCON_CLKSET2
+	ldr r1, =(23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \
+		  24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \
+		  24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \
+		  1 << SYSCON_CLKSET_PLL_PS_SHIFT | \
+		  SYSCON_CLKSET2_PLL2_EN | \
+		  SYSCON_CLKSET2_NBYP2 | \
+		  3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
+	str r1, [r0]
+
+	/* the user's guide recommends to wait at least 1 ms for PLL2 to
+	 * stabilize, but Cirrus' Redboot doesn't do that, either
+	 */
+
+	mov pc, lr
diff --git a/board/edb93xx/sdram_cfg.S b/board/edb93xx/sdram_cfg.S
new file mode 100644
index 0000000..752bb72
--- /dev/null
+++ b/board/edb93xx/sdram_cfg.S
@@ -0,0 +1,217 @@
+/*
+ * SDRAM setup for edb93xx boards
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath at gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <asm/arch/ep93xx.h>
+
+/* delay for 200us
+ * loop takes 4 cycles at 5.0ns (worst case, running at 200MHz)
+ * per cycle = 20ns, 0x3000 (12288) gives us 246us to be safe
+ */
+.macro delay200
+	ldr r0, =0x3000
+200:
+	subs r0, r0, #1
+	bne 200b
+.endm
+
+.globl sdram_cfg
+sdram_cfg:
+
+#ifdef CONFIG_EDB93XX_SDCS0
+	ldr r1, =SDRAM_DEVCFG0
+#elif defined(CONFIG_EDB93XX_SDCS3)
+	ldr r1, =SDRAM_DEVCFG3
+#else
+#error "SDRAM bank configuration"
+#endif
+
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+	defined(CONFIG_EDB9302A)
+	/* 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+	 *
+	 * CLK cycle time min:
+	 *	@ CAS latency = 3: 7.5ns
+	 *	@ CAS latency = 2: 10ns
+	 * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
+	 * so it's safe to use CAS latency = 2
+	 *
+	 * RAS-to-CAS delay min:
+	 *	20ns
+	 * At 15ns cycle time, we use RAS-to-CAS delay = 2
+	 *
+	 * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
+	 * as four blocks of 8MB size, instead of eight blocks of 4MB size:
+	 *
+	 * EDB9301/EDB9302:
+ 	 *
+	 * 0x00000000 - 0x007fffff
+	 * 0x01000000 - 0x017fffff
+	 * 0x04000000 - 0x047fffff
+	 * 0x05000000 - 0x057fffff
+	 *
+	 *
+	 * EDB9302a:
+ 	 *
+	 * 0xc0000000 - 0xc07fffff
+	 * 0xc1000000 - 0xc17fffff
+	 * 0xc4000000 - 0xc47fffff
+	 * 0xc5000000 - 0xc57fffff
+	 *
+	 * BANKCOUNT = 1: This is a device with four banks
+	 */
+
+	ldr r0, =(SDRAM_DEVCFG_BANKCOUNT | SDRAM_DEVCFG_SROMLL |\
+		  SDRAM_DEVCFG_CASLAT_2 | SDRAM_DEVCFG_RASTOCAS_2 |\
+		  SDRAM_DEVCFG_EXTBUSWIDTH)
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||\
+	defined(CONFIG_EDB9315A)
+	/* 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM
+	 *
+	 * CLK cycle time min:
+	 *	@ CAS latency = 3: 7.5ns
+	 *	@ CAS latency = 2: 10ns
+	 * We're running at 100MHz (10ns cycle time) external bus speed (HCLK),
+	 * so it's safe to use CAS latency = 2
+	 *
+	 * RAS-to-CAS delay min:
+	 *	20ns
+	 * At 10ns cycle time, we use RAS-to-CAS delay = 2
+	 *
+	 * EDB9307, EDB9312, EDB9315:
+	 *
+	 * 0x00000000 - 0x01ffffff
+	 * 0x04000000 - 0x05ffffff
+	 *
+	 *
+	 * EDB9307a, EDB9315a:
+	 *
+	 * 0xc0000000 - 0xc1ffffff
+	 * 0xc4000000 - 0xc5ffffff
+	 *
+	 */
+	ldr r0, =(SDRAM_DEVCFG_BANKCOUNT | SDRAM_DEVCFG_SROMLL |\
+		  SDRAM_DEVCFG_CASLAT_2 | SDRAM_DEVCFG_RASTOCAS_2)
+#endif
+	str r0, [r1]
+
+	/* Issue continous NOP commands */
+	ldr r1, =SDRAM_GLCONFIG
+	ldr r0, =(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE)
+	str r0, [r1]
+
+	delay200
+
+#if defined(CONFIG_EP9301) || defined(CONFIG_EP9302)
+	/* Errata for EP9301/2 rev. E0 says that PRECHARGE ALL isn't always
+	 * issued.
+	 * Do a read from each bank to make sure they're precharged
+	 * Logical address bits A[22:21] map to BA[1:0] (SROMLL is set)
+	 * The errata further says that this isn't going to be fixed,
+	 * therefor do it for all revisions
+	 */
+	ldr r0, =(GLCONFIG_CKE)
+	str r0, [r1] /* SDRAM_GLCONFIG */
+
+	ldr r0, =0x00000000 /* A[22:21] = b00 */
+	str r0, [r0]
+	ldr r0, =0x00200000 /* A[22:21] = b01 */
+	str r0, [r0]
+	ldr r0, =0x00400000 /* A[22:21] = b10 */
+	str r0, [r0]
+	ldr r0, =0x00600000 /* A[22:21] = b11 */
+	str r0, [r0]
+#endif
+
+	/* Load refresh timer with 10 to issue refresh every 10 cycles */
+	ldr r1, =SDRAM_REFRSHTIMR
+	ldr r0, =0x0a
+	str r0, [r1]
+
+	/* Wait at least 80 clock cycles to provide 8 refresh cycles
+	   to all SDRAMs */
+	delay200 /* we wait 200us, which is a lot more than necessary */
+
+	/* Program refresh timer with normal value
+	 * We need 8192 refresh cycles every 64ms
+	 * at 15ns (HCLK >= 66MHz) per cycle:
+	 * 64ms / 8192 = 7.8125us
+	 * 7.8125us / 15ns = 520 (0x208)
+	 */
+	/* TODO: redboot uses 0x1e0 for the slowest possible device
+		 but i don't understand how this value is calculated */
+	ldr r0, =0x208
+	str r0, [r1]
+
+
+	/* Select mode register update mode */
+	ldr r1, =SDRAM_GLCONFIG
+	ldr r0, =(GLCONFIG_CKE | GLCONFIG_MRS)
+	str r0, [r1]
+
+#if defined(CONFIG_EP9301) || defined(CONFIG_EP9302)
+	/* Program mode register
+	 * A[22:09] is output as SYA[13:0] on a 16 bit ext. bus
+	 * CAS latency: 2
+	 * Burst type: sequential
+	 * Burst length: 8 (required for 16 bit ext. bus)
+	 * SYA[13:0] = 0x0023
+	 */
+	ldr r0, =0x00004600
+	ldr r0, [r0]
+#elif defined(CONFIG_EDB93XX_SDCS3)
+	ldr r0, =0x00008800
+	ldr r0, [r0]
+
+	ldr r0, =0x00400000
+	ldr r0, [r0]
+
+	ldr r0, =0x00808800
+	ldr r0, [r0]
+
+	ldr r0, =0x00c08800
+	ldr r0, [r0]
+#else
+	ldr r0, =0x00008800
+	ldr r0, [r0]
+
+	ldr r0, =0xc0400000
+	ldr r0, [r0]
+
+	ldr r0, =0xc0808800
+	ldr r0, [r0]
+
+	ldr r0, =0xc0c08800
+	ldr r0, [r0]
+#endif
+
+	/* Select normal operation mode */
+	ldr r1, =SDRAM_GLCONFIG
+	ldr r0, =(GLCONFIG_CKE)
+	str r0, [r1]
+
+	mov pc, lr
diff --git a/board/edb93xx/u-boot.lds b/board/edb93xx/u-boot.lds
new file mode 100644
index 0000000..76caef3
--- /dev/null
+++ b/board/edb93xx/u-boot.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj at denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+	  cpu/arm920t/start.o	(.text)
+	  . = 0x1000;
+	  LONG(0x53555243)
+	  *(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
diff --git a/cpu/arm920t/ep93xx/Makefile b/cpu/arm920t/ep93xx/Makefile
new file mode 100644
index 0000000..9763e15
--- /dev/null
+++ b/cpu/arm920t/ep93xx/Makefile
@@ -0,0 +1,55 @@
+# vim: set ts=8 sw=8 noet:
+#
+# Cirrus Logic EP93xx CPU-specific Makefile
+#
+# Copyright (C) 2004, 2005
+# Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+#
+# Copyright (C) 2006
+# Dominic Rath <Dominic.Rath at gmx.de>
+#
+# Based on an original Makefile, which is
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+COBJS   = cpu.o eth.o timer.o speed.o
+SOBJS   = lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS    := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:    $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+
diff --git a/cpu/arm920t/ep93xx/cpu.c b/cpu/arm920t/ep93xx/cpu.c
new file mode 100644
index 0000000..3989ee8
--- /dev/null
+++ b/cpu/arm920t/ep93xx/cpu.c
@@ -0,0 +1,125 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx CPU-specific support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+
+#if defined(CONFIG_EP93XX)
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+
+/* The errata for silicon revision E1 states that the PartID of the
+ * ExtensionID register is not programmed, and that this feature has been
+ * removed from the chip.
+ *
+ * Note also that the chip revision indication found in the CHIP_ID register
+ * (0x80930094) has proven reliable for determining a particular core's
+ * silicon version.
+ */
+extern int checkcpu(void)
+{
+	const uint32_t chip_id = readl(SYSCON_CHIPID);
+
+	printf("CPU: Cirrus Logic EP93xx");
+	printf(" - Rev. ");
+	switch (chip_id & SYSCON_CHIPID_REV_MASK) {
+	case 0x00000000:
+		printf("A");
+		break;
+
+	case 0x10000000:
+		printf("B");
+		break;
+
+	case 0x20000000:
+		printf("C");
+		break;
+
+	case 0x30000000:
+		printf("D0");
+		break;
+
+	case 0x40000000:
+		printf("D1");
+		break;
+
+	case 0x50000000:
+		printf("E0");
+		break;
+
+	default:
+		printf("?");
+		break;
+	}
+
+	return 0;
+}
+
+
+/* All EP93xx variants have 16 KiB I-cache. */
+extern int checkicache(void)
+{
+	return 16 << 10;
+}
+
+
+/* All EP93xx variants have 16 KiB D-cache. */
+extern int checkdcache(void)
+{
+	return 16 << 10;
+}
+
+
+/* This is a nop on ARM, and is included here for completeness only. */
+extern void upmconfig(unsigned int upm, unsigned int *table, unsigned int size)
+{
+	/* nop */
+}
+
+
+/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
+extern void reset_cpu(ulong addr)
+{
+	uint32_t value;
+
+	/* Unlock DeviceCfg and set SWRST */
+	writel(0xAA, SYSCON_SYSSWLOCK);
+	value = readl(SYSCON_DEVICECFG);
+	value |= SYSCON_DEVICECFG_SWRST;
+	writel(value, SYSCON_DEVICECFG);
+
+	/* Unlock DeviceCfg and clear SWRST */
+	writel(0xAA, SYSCON_SYSSWLOCK);
+	value = readl(SYSCON_DEVICECFG);
+	value &= ~SYSCON_DEVICECFG_SWRST;
+	writel(value, SYSCON_DEVICECFG);
+
+	/* Dying... */
+	while (1)
+		; /* nop */
+}
+
+
+#endif	/* defined(CONFIG_EP93XX) */
diff --git a/cpu/arm920t/ep93xx/eth.c b/cpu/arm920t/ep93xx/eth.c
new file mode 100644
index 0000000..513c221
--- /dev/null
+++ b/cpu/arm920t/ep93xx/eth.c
@@ -0,0 +1,876 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx ethernet MAC / MII driver.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+ *
+ * Based on the original eth.[ch] Cirrus Logic EP93xx Rev D. Ethernet Driver,
+ * which is
+ *
+ * (C) Copyright 2002 2003
+ * Adam Bezanson, Network Audio Technologies, Inc.
+ * <bezanson at netaudiotech.com>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <command.h>
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <net.h>
+#include <linux/types.h>
+
+
+/**
+ * Send an error message to the terminal.
+ */
+#define ERROR(x)							\
+	do {								\
+		char *__foo = strrchr(__FILE__, '/');			\
+									\
+		printf("%s: %d: %s(): ",				\
+			(__foo == NULL ? __FILE__ : (__foo + 1)),	\
+			__LINE__, __func__);				\
+		printf x; printf("\n");					\
+	} while (0);
+
+
+/**
+ * Send a trace message to the terminal.
+ */
+#if 0
+#define TRACE(x)							\
+	do {								\
+		char *__foo = strrchr(__FILE__, '/');			\
+									\
+		printf("%s: %d: %s(): ",				\
+			(__foo == NULL ? __FILE__ : (__foo + 1)),	\
+			__LINE__, __func__);				\
+		printf x; printf("\n");					\
+	} while (0);
+
+#else
+#define TRACE(x)
+#endif
+
+
+/* -----------------------------------------------------------------------------
+ * EP93xx ethernet MAC functionality
+ */
+#if defined(CONFIG_DRIVER_EP93XX_MAC)
+
+/**
+ * #define this to dump device status and queue info during initialization and
+ * following errors.
+ */
+#undef EP93XX_MAC_DEBUG
+
+/**
+ * Number of descriptor and status entries in our RX queues.
+ * It must be power of 2 !
+ */
+#define NUMRXDESC		PKTBUFSRX
+
+/**
+ * Number of descriptor and status entries in our TX queues.
+ */
+#define NUMTXDESC		1
+
+/**
+ * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
+ */
+#define TXSTARTMAX		944
+
+
+/**
+ * Ethernet MAC interface return values for public functions.
+ */
+enum eth_status {
+	ETH_STATUS_SUCCESS = 0,
+	ETH_STATUS_FAILURE = 1,
+};
+
+
+/**
+ * Receive descriptor queue entry
+ */
+struct rx_descriptor {
+	union {
+		uint32_t word1;
+
+		struct {
+			unsigned buffer_address:32;
+		};
+	};
+
+	union {
+		uint32_t word2;
+
+		struct {
+			unsigned buffer_length:16;
+			unsigned buffer_index:15;
+			unsigned not_sof:1;
+		};
+	};
+} __attribute__((packed));
+
+
+/**
+ * Receive status queue entry
+ */
+struct rx_status {
+	union {
+		uint32_t word1;
+
+		struct {
+			unsigned:8;
+			unsigned hti:6;
+			unsigned:1;
+			unsigned crci:1;
+			unsigned crce:1;
+			unsigned edata:1;
+			unsigned runt:1;
+			unsigned fe:1;
+			unsigned oe:1;
+			unsigned rx_err:1;
+			unsigned am:2;
+			unsigned:4;
+			unsigned eob:1;
+			unsigned eof:1;
+			unsigned rwe:1;
+			unsigned rfp:1;
+		};
+	};
+
+	union {
+		uint32_t word2;
+
+		struct {
+			unsigned frame_length:16;
+			unsigned buffer_index:15;
+			unsigned rfp:1;
+		};
+	};
+} __attribute__((packed));
+
+
+/**
+ * Transmit descriptor queue entry
+ */
+struct tx_descriptor {
+	union {
+		uint32_t word1;
+
+		struct {
+			unsigned buffer_address:32;
+		};
+	};
+
+	union {
+		uint32_t word2;
+
+		struct {
+			unsigned buffer_length:12;
+			unsigned:3;
+			unsigned abort_frame:1;
+			unsigned buffer_index:15;
+			unsigned eof:1;
+		};
+	};
+} __attribute__((packed));
+
+
+/**
+ * Transmit status queue entry
+ */
+struct tx_status {
+	union {
+		uint32_t word1;
+
+		struct {
+			unsigned tbi:15;
+			unsigned:1;
+			unsigned ncoll:5;
+			unsigned:3;
+			unsigned ecoll:1;
+			unsigned txu:1;
+			unsigned ow:1;
+			unsigned:1;
+			unsigned lcrs:1;
+			unsigned fa:1;
+			unsigned txwe:1;
+			unsigned txfp:1;
+		};
+	};
+} __attribute__((packed));
+
+
+/**
+ * Transmit descriptor queue
+ */
+struct tx_descriptor_queue {
+	struct tx_descriptor *base;
+	struct tx_descriptor *current;
+	struct tx_descriptor *end;
+};
+
+
+/**
+ * Transmit status queue
+ */
+struct tx_status_queue {
+	struct tx_status *base;
+	struct tx_status *current;
+	struct tx_status *end;
+};
+
+
+/**
+ * Receive descriptor queue
+ */
+struct rx_descriptor_queue {
+	struct rx_descriptor *base;
+	struct rx_descriptor *current;
+	struct rx_descriptor *end;
+};
+
+
+/**
+ * Receive status queue
+ */
+struct rx_status_queue {
+	struct rx_status *base;
+	struct rx_status *current;
+	struct rx_status *end;
+};
+
+
+/**
+ * EP93xx MAC private data structure
+ */
+struct ep93xx_mac {
+	int				is_initialized;
+
+	struct rx_descriptor_queue	rx_dq;
+	struct rx_status_queue		rx_sq;
+	void				*rx_buffer[NUMRXDESC];
+
+	struct tx_descriptor_queue	tx_dq;
+	struct tx_status_queue		tx_sq;
+};
+
+
+/* ep93xx_miiphy ops forward declarations */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short * const value);
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short const value);
+
+
+/* Reserve memory for the MAC's private data */
+static struct ep93xx_mac dev = { 0 };
+
+
+/**
+ * Dump ep93xx_mac values to the terminal.
+ */
+inline void dump_dev(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+	int i;
+
+	printf("\ndump_dev()\n");
+	printf("  is_initialized     %02X\n", dev.is_initialized);
+	printf("  rx_dq.base	     %08X\n", dev.rx_dq.base);
+	printf("  rx_dq.current	     %08X\n", dev.rx_dq.current);
+	printf("  rx_dq.end	     %08X\n", dev.rx_dq.end);
+	printf("  rx_sq.base	     %08X\n", dev.rx_sq.base);
+	printf("  rx_sq.current	     %08X\n", dev.rx_sq.current);
+	printf("  rx_sq.end	     %08X\n", dev.rx_sq.end);
+
+	for (i = 0; i < NUMRXDESC; i++)
+		printf("  rx_buffer[%2.d]      %08X\n", i, NetRxPackets[i]);
+
+	printf("  tx_dq.base	     %08X\n", dev.tx_dq.base);
+	printf("  tx_dq.current	     %08X\n", dev.tx_dq.current);
+	printf("  tx_dq.end	     %08X\n", dev.tx_dq.end);
+	printf("  tx_sq.base	     %08X\n", dev.tx_sq.base);
+	printf("  tx_sq.current	     %08X\n", dev.tx_sq.current);
+	printf("  tx_sq.end	     %08X\n", dev.tx_sq.end);
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX descriptor queue entries to the terminal.
+ */
+inline void dump_rx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+	int i;
+
+	printf("\ndump_rx_descriptor_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMRXDESC; i++) {
+		printf("  [ %08X ]	     %08X	 %08X\n",
+			(dev.rx_dq.base + i),
+			(dev.rx_dq.base + i)->word1,
+			(dev.rx_dq.base + i)->word2);
+	}
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all RX status queue entries to the terminal.
+ */
+inline void dump_rx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+	int i;
+
+	printf("\ndump_rx_status_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMRXDESC; i++) {
+		printf("  [ %08X ]	     %08X	 %08X\n",
+			(dev.rx_sq.base + i),
+			(dev.rx_sq.base + i)->word1,
+			(dev.rx_sq.base + i)->word2);
+	}
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX descriptor queue entries to the terminal.
+ */
+inline void dump_tx_descriptor_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+	int i;
+
+	printf("\ndump_tx_descriptor_queue()\n");
+	printf("  descriptor address	 word1		 word2\n");
+	for (i = 0; i < NUMTXDESC; i++) {
+		printf("  [ %08X ]	     %08X	 %08X\n",
+			(dev.tx_dq.base + i),
+			(dev.tx_dq.base + i)->word1,
+			(dev.tx_dq.base + i)->word2);
+	}
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Dump all TX status queue entries to the terminal.
+ */
+inline void dump_tx_status_queue(void)
+{
+#if defined(EP93XX_MAC_DEBUG)
+	int i;
+
+	printf("\ndump_tx_status_queue()\n");
+	printf("  descriptor address	 word1\n");
+	for (i = 0; i < NUMTXDESC; i++) {
+		printf("  [ %08X ]	     %08X\n",
+			(dev.rx_sq.base + i),
+			(dev.rx_sq.base + i)->word1);
+	}
+#endif	/* defined(EP93XX_MAC_DEBUG) */
+}
+
+
+/**
+ * Reset the EP93xx MAC by twiddling the soft reset bit and spinning until
+ * it's cleared.
+ */
+static void ep93xx_mac_reset(void)
+{
+	TRACE(("+ep93xx_mac_reset"));
+
+	uint32_t value = readl(MAC_SELFCTL);
+	value |= SELFCTL_RESET;
+	writel(value, MAC_SELFCTL);
+
+	while (readl(MAC_SELFCTL) & SELFCTL_RESET)
+		; /* nop */
+
+	TRACE(("-ep93xx_mac_reset"));
+}
+
+
+/**
+ * Halt EP93xx MAC transmit and receive by clearing the TxCTL and RxCTL
+ * registers.
+ */
+extern void eth_halt(void)
+{
+	TRACE(("+eth_halt"));
+
+	writel(0x00000000, MAC_RXCTL);
+	writel(0x00000000, MAC_TXCTL);
+
+	TRACE(("-eth_halt"));
+}
+
+#if defined(CONFIG_MII)
+int ep93xx_miiphy_initialize(bd_t * const bd)
+{
+	miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write);
+	return 0;
+}
+#endif
+
+/**
+ * Initialize the EP93xx MAC.  The MAC hardware is reset.  Buffers are
+ * allocated, if necessary, for the TX and RX descriptor and status queues,
+ * as well as for received packets.  The EP93XX MAC hardware is initialized.
+ * Transmit and receive operations are enabled.
+ */
+extern int eth_init(bd_t * const bd)
+{
+	int ret = ETH_STATUS_FAILURE;
+	int i;
+	uchar enetaddr[6];
+
+	TRACE(("+eth_init"));
+
+	/* Parameter check */
+	if (bd == NULL) {
+		ERROR(("NULL bd"));
+		goto eth_init_failed_0;
+	}
+
+	/* Reset the MAC */
+	ep93xx_mac_reset();
+
+	/* Allocate space for the queues and RX packet buffers if we're not
+	 * already initialized */
+	if (!dev.is_initialized) {
+		dev.tx_dq.base = calloc(NUMTXDESC,
+					sizeof(struct tx_descriptor));
+		if (dev.tx_dq.base == NULL) {
+			ERROR(("calloc() failed"));
+			goto eth_init_failed_0;
+		}
+
+		dev.tx_sq.base = calloc(NUMTXDESC,
+					sizeof(struct tx_status));
+		if (dev.tx_sq.base == NULL) {
+			ERROR(("calloc() failed"));
+			goto eth_init_failed_1;
+		}
+
+		dev.rx_dq.base = calloc(NUMRXDESC,
+					sizeof(struct rx_descriptor));
+		if (dev.rx_dq.base == NULL) {
+			ERROR(("calloc() failed"));
+			goto eth_init_failed_2;
+		}
+
+		dev.rx_sq.base = calloc(NUMRXDESC,
+					sizeof(struct rx_status));
+		if (dev.rx_sq.base == NULL) {
+			ERROR(("calloc() failed"));
+			goto eth_init_failed_3;
+		}
+
+		/* Set is_initialized flag so we don't go through allocation
+		 * portion of init again. */
+		dev.is_initialized = 1;
+	}
+
+	/* Reset the descriptor queues' current and end address values */
+	dev.tx_dq.current = dev.tx_dq.base;
+	dev.tx_dq.end = (dev.tx_dq.base + NUMTXDESC);
+
+	dev.tx_sq.current = dev.tx_sq.base;
+	dev.tx_sq.end = (dev.tx_sq.base + NUMTXDESC);
+
+	dev.rx_dq.current = dev.rx_dq.base;
+	dev.rx_dq.end = (dev.rx_dq.base + NUMRXDESC);
+
+	dev.rx_sq.current = dev.rx_sq.base;
+	dev.rx_sq.end = (dev.rx_sq.base + NUMRXDESC);
+
+	/* Set the transmit descriptor and status queues' base address,
+	 * current address, and length registers.  Set the maximum frame
+	 * length and threshold. Enable the transmit descriptor processor. */
+	writel((uint32_t)dev.tx_dq.base, MAC_TXDQBADD);
+	writel((uint32_t)dev.tx_dq.base, MAC_TXDQCURADD);
+	writel(sizeof(struct tx_descriptor) * NUMTXDESC, MAC_TXDQBLEN);
+
+	writel((uint32_t)dev.tx_sq.base, MAC_TXSTSQBADD);
+	writel((uint32_t)dev.tx_sq.base, MAC_TXSTSQCURADD);
+	writel(sizeof(struct tx_status) * NUMTXDESC, MAC_TXSTSQBLEN);
+
+	writel(0x00040000, MAC_TXDTHRSHLD);
+
+	writel(0x00040000, MAC_TXSTSTHRSHLD);
+
+	writel((TXSTARTMAX << 0) | (PKTSIZE_ALIGN << 16), MAC_MAXFRMLEN);
+	writel(BMCTL_TXEN, MAC_BMCTL);
+
+	/* Set the receive descriptor and status queues' base address,
+	 * current address, and length registers.  Enable the receive
+	 * descriptor processor. */
+	writel((uint32_t)dev.rx_dq.base, MAC_RXDQBADD);
+	writel((uint32_t)dev.rx_dq.base, MAC_RXDQCURADD);
+	writel(sizeof(struct rx_descriptor) * NUMRXDESC, MAC_RXDQBLEN);
+
+	writel((uint32_t)dev.rx_sq.base, MAC_RXSTSQBADD);
+	writel((uint32_t)dev.rx_sq.base, MAC_RXSTSQCURADD);
+	writel(sizeof(struct rx_status) * NUMRXDESC, MAC_RXSTSQBLEN);
+
+	writel(0x00040000, MAC_RXDTHRSHLD);
+
+	writel(BMCTL_RXEN, MAC_BMCTL);
+
+	writel(0x00040000, MAC_RXSTSTHRSHLD);
+
+	/* Wait until the receive descriptor processor is active */
+	while (!(readl(MAC_BMSTS) & BMSTS_RXACT))
+		; /* nop */
+
+	/* Initialize the RX descriptor queue.  Clear the TX descriptor queue.
+	 * Clear the RX and TX status queues.  Enqueue the RX descriptor and
+	 * status entries to the MAC. */
+	for (i = 0; i < NUMRXDESC; i++) {
+		(dev.rx_dq.base + i)->buffer_address =
+			(uint32_t)NetRxPackets[i];
+		(dev.rx_dq.base + i)->buffer_length = PKTSIZE_ALIGN;
+		(dev.rx_dq.base + i)->buffer_index = 0;
+	}
+
+	memset(dev.tx_dq.base, 0, (sizeof(struct tx_descriptor) * NUMTXDESC));
+	memset(dev.rx_sq.base, 0, (sizeof(struct rx_status) * NUMRXDESC));
+	memset(dev.tx_sq.base, 0, (sizeof(struct tx_status) * NUMTXDESC));
+
+	writel(NUMRXDESC, MAC_RXDENQ);
+	writel(NUMRXDESC, MAC_RXSTSENQ);
+
+	/* Set the primary MAC address */
+	writel(AFP_IAPRIMARY, MAC_AFP);
+	eth_getenv_enetaddr("ethaddr", enetaddr);
+	writel(enetaddr[0] | (enetaddr[1] << 8) |
+		(enetaddr[2] << 16) | (enetaddr[3] << 24),
+		MAC_INDAD);
+	writel(enetaddr[4] | (enetaddr[5] << 8), MAC_INDAD_UPPER);
+
+	/* Turn on RX and TX */
+	writel(RXCTL_IA0 | RXCTL_BA | RXCTL_SRXON |
+		RXCTL_RCRCA | RXCTL_MA, MAC_RXCTL);
+	writel(TXCTL_STXON, MAC_TXCTL);
+
+	/* Dump data structures if we're debugging */
+	dump_dev();
+	dump_rx_descriptor_queue();
+	dump_rx_status_queue();
+	dump_tx_descriptor_queue();
+	dump_tx_status_queue();
+
+	/* Done! */
+	ret = ETH_STATUS_SUCCESS;
+	goto eth_init_done;
+
+	free(dev.rx_sq.base);
+	/* Fall through */
+
+eth_init_failed_3:
+	free(dev.rx_dq.base);
+	/* Fall through */
+
+eth_init_failed_2:
+	free(dev.tx_sq.base);
+	/* Fall through */
+
+eth_init_failed_1:
+	free(dev.tx_dq.base);
+	/* Fall through */
+
+eth_init_failed_0:
+eth_init_done:
+	TRACE(("-eth_init %d", ret));
+	return ret;
+}
+
+
+/**
+ * Copy a frame of data from the MAC into the protocol layer for further
+ * processing.
+ *
+ * TODO: Enhance this to deal with as many packets as are available at
+ * the MAC at one time? */
+extern int eth_rx(void)
+{
+	int ret = ETH_STATUS_FAILURE;
+
+	TRACE(("+eth_rx"));
+
+	if (dev.rx_sq.current->rfp) {
+		if (dev.rx_sq.current->rwe) {
+			/* We have a good frame.  Extract the frame's length
+			 * from the current rx_status_queue entry, and copy
+			 * the frame's data into NetRxPackets[] of the
+			 * protocol stack.  We track the total number of
+			 * bytes in the frame (nbytes_frame) which will be
+			 * used when we pass the data off to the protocol
+			 * layer via NetReceive(). */
+			NetReceive((uchar *)dev.rx_dq.current->buffer_address,
+				dev.rx_sq.current->frame_length);
+			TRACE(("reporting %d bytes...\n",
+					dev.rx_sq.current->frame_length));
+
+			ret = ETH_STATUS_SUCCESS;
+
+		} else {
+			/* Do we have an erroneous packet? */
+			ERROR(("packet rx error, status %08X %08X",
+					dev.rx_sq.current->word1,
+					dev.rx_sq.current->word2));
+			dump_rx_descriptor_queue();
+			dump_rx_status_queue();
+		}
+
+		/* Clear the associated status queue entry, and
+		 * increment our current pointers to the next RX
+		 * descriptor and status queue entries (making sure
+		 * we wrap properly). */
+		memset(dev.rx_sq.current, 0, sizeof(struct rx_status));
+
+		dev.rx_sq.current++;
+		if (dev.rx_sq.current >= dev.rx_sq.end)
+			dev.rx_sq.current = dev.rx_sq.base;
+
+		dev.rx_dq.current++;
+		if (dev.rx_dq.current >= dev.rx_dq.end)
+			dev.rx_dq.current = dev.rx_dq.base;
+
+		/* Finally, return the RX descriptor and status entries
+		 * back to the MAC engine, and loop again, checking for
+		 * more descriptors to process. */
+		writel(1, MAC_RXDENQ);
+		writel(1, MAC_RXSTSENQ);
+	} else {
+		ret = ETH_STATUS_SUCCESS;
+	}
+
+	TRACE(("-eth_rx %d", ret));
+	return ret;
+}
+
+
+/**
+ * Send a block of data via ethernet.
+ *
+ * TODO: Enhance this to deal with as much data as are available at one time? */
+extern int eth_send(volatile void * const packet, int const length)
+{
+	int ret = ETH_STATUS_FAILURE;
+
+	TRACE(("+eth_send"));
+
+	/* Parameter check */
+	if (packet == NULL) {
+		ERROR(("NULL packet"));
+		goto eth_send_failed_0;
+	}
+
+	/* Initialize the TX descriptor queue with the new packet's info.
+	 * Clear the associated status queue entry.  Enqueue the packet
+	 * to the MAC for transmission. */
+	dev.tx_dq.current->buffer_address = (uint32_t)packet;
+	dev.tx_dq.current->buffer_length = length;
+	dev.tx_dq.current->buffer_index = 0;
+	dev.tx_dq.current->eof = 1;
+
+	dev.tx_sq.current->word1 = 0;
+
+	writel(1, MAC_TXDENQ);
+
+	/* Wait for TX to complete, and check status entry for errors. */
+	while (!(readl(MAC_INTSTSC) & INTSTS_TXSQ))
+		; /* nop */
+
+	if (!dev.tx_sq.current->txfp || !dev.tx_sq.current->txwe) {
+		ERROR(("packet tx error, status %08X",
+				dev.tx_sq.current->word1));
+		dump_tx_descriptor_queue();
+		dump_tx_status_queue();
+
+		/* TODO: Add better error handling? */
+		goto eth_send_failed_0;
+	}
+
+	ret = ETH_STATUS_SUCCESS;
+	/* Fall through */
+
+eth_send_failed_0:
+	TRACE(("-eth_send %d", ret));
+	return ret;
+}
+#endif	/* defined(CONFIG_DRIVER_EP93XX_MAC) */
+
+
+/* -----------------------------------------------------------------------------
+ * EP93xx ethernet MII functionality.
+ */
+#if defined(CONFIG_MII)
+
+/**
+ * Maximum MII address we support
+ */
+#define MII_ADDRESS_MAX			(31)
+
+/**
+ * Maximum MII register address we support
+ */
+#define MII_REGISTER_MAX		(31)
+
+
+/**
+ * Ethernet MII interface return values for public functions.
+ */
+enum mii_status {
+	MII_STATUS_SUCCESS = 0,
+	MII_STATUS_FAILURE = 1,
+};
+
+
+/**
+ * Read a 16-bit value from an MII register.
+ */
+static int ep93xx_miiphy_read(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short * const value)
+{
+	int ret = MII_STATUS_FAILURE;
+	uint32_t self_ctl;
+
+	TRACE(("+ep93xx_miiphy_read"));
+
+	/* Parameter checks */
+	if (dev == NULL) {
+		ERROR(("NULL dev"));
+		goto ep93xx_miiphy_read_failed_0;
+	}
+
+	if (addr > MII_ADDRESS_MAX) {
+		ERROR(("invalid addr, 0x%02X", addr));
+		goto ep93xx_miiphy_read_failed_0;
+	}
+
+	if (reg > MII_REGISTER_MAX) {
+		ERROR(("invalid reg, 0x%02X", reg));
+		goto ep93xx_miiphy_read_failed_0;
+	}
+
+	if (value == NULL) {
+		ERROR(("NULL value"));
+		goto ep93xx_miiphy_read_failed_0;
+	}
+
+	/* Save the current SelfCTL register value.  Set MAC to suppress
+	 * preamble bits.  Wait for any previous MII command to complete
+	 * before issuing the new command. */
+	self_ctl = MAC_SELFCTL;
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+	writel(self_ctl & ~(1 << 8), MAC_SELFCTL);
+#endif	/* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+	while (readl(MAC_MIISTS) & MIISTS_BUSY)
+		; /* nop */
+
+	/* Issue the MII 'read' command.  Wait for the command to complete.
+	 * Read the MII data value. */
+	writel(MIICMD_OPCODE_READ | ((uint32_t)addr << 5) | (uint32_t)reg,
+		MAC_MIICMD);
+	while (readl(MAC_MIISTS) & MIISTS_BUSY)
+		; /* nop */
+
+	*value = (unsigned short)readl(MAC_MIIDATA);
+
+	/* Restore the saved SelfCTL value and return. */
+	writel(self_ctl, MAC_SELFCTL);
+
+	ret = MII_STATUS_SUCCESS;
+	/* Fall through */
+
+ep93xx_miiphy_read_failed_0:
+	TRACE(("-ep93xx_miiphy_read"));
+	return ret;
+}
+
+
+/**
+ * Write a 16-bit value to an MII register.
+ */
+static int ep93xx_miiphy_write(char * const dev, unsigned char const addr,
+			unsigned char const reg, unsigned short const value)
+{
+	int ret = MII_STATUS_FAILURE;
+	uint32_t self_ctl;
+
+	TRACE(("+ep93xx_miiphy_write"));
+
+	/* Parameter checks */
+	if (dev == NULL) {
+		ERROR(("NULL dev"));
+		goto ep93xx_miiphy_write_failed_0;
+	}
+
+	if (addr > MII_ADDRESS_MAX) {
+		ERROR(("invalid addr, 0x%02X", addr));
+		goto ep93xx_miiphy_write_failed_0;
+	}
+
+	if (reg > MII_REGISTER_MAX) {
+		ERROR(("invalid reg, 0x%02X", reg));
+		goto ep93xx_miiphy_write_failed_0;
+	}
+
+	/* Save the current SelfCTL register value.  Set MAC to suppress
+	 * preamble bits.  Wait for any previous MII command to complete
+	 * before issuing the new command. */
+	self_ctl = readl(MAC_SELFCTL);
+#if defined(CONFIG_MII_SUPPRESS_PREAMBLE)
+	writel(self_ctl & ~(1 << 8), MAC_SELFCTL);
+#endif	/* defined(CONFIG_MII_SUPPRESS_PREAMBLE) */
+
+	while (readl(MAC_MIISTS) & MIISTS_BUSY)
+		; /* nop */
+
+	/* Issue the MII 'write' command.  Wait for the command to complete. */
+	writel((uint32_t)value, MAC_MIIDATA);
+	writel(MIICMD_OPCODE_WRITE | ((uint32_t)addr << 5) | (uint32_t)reg,
+		MAC_MIICMD);
+	while (readl(MAC_MIISTS) & MIISTS_BUSY)
+		; /* nop */
+
+	/* Restore the saved SelfCTL value and return. */
+	writel(self_ctl, MAC_SELFCTL);
+
+	ret = MII_STATUS_SUCCESS;
+	/* Fall through */
+
+ep93xx_miiphy_write_failed_0:
+	TRACE(("-ep93xx_miiphy_write"));
+	return ret;
+}
+#endif	/* defined(CONFIG_MII) */
diff --git a/cpu/arm920t/ep93xx/lowlevel_init.S b/cpu/arm920t/ep93xx/lowlevel_init.S
new file mode 100644
index 0000000..34a2100
--- /dev/null
+++ b/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -0,0 +1,74 @@
+/*
+ * Low-level initialization for EP93xx
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2006 Dominic Rath <Dominic.Rath at gmx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <version.h>
+#include <asm/arch/ep93xx.h>
+
+.globl lowlevel_init
+lowlevel_init:
+
+	/* Turn on both LEDs */
+	ldr r1, =GPIO_PEDR
+	ldr r0, [r1]
+	orr r0, r0, #(0x1 | 0x2)
+	str r0, [r1]
+
+	/* backup return address */
+	ldr r1, =SYSCON_SCRATCH0
+	str lr, [r1]
+
+	/* Configure flash wait states before we switch to the PLL */
+	bl flash_cfg
+
+	/* Set up PLL */
+	bl pll_cfg
+
+	/* Turn off the Green LED and leave the Red LED on */
+	ldr r1, =GPIO_PEDR
+	ldr r0, [r1]
+	bic r0, r0, #(0x1)
+	str r0, [r1]
+
+	/* Setup SDRAM */
+	bl sdram_cfg
+
+	/* Turn on Green LED, Turn off the Red LED */
+	ldr r1, =GPIO_PEDR
+	ldr r0, [r1]
+	bic r0, r0, #(0x2)
+	orr r0, r0, #(0x1)
+	str r0, [r1]
+
+	/* FIXME: we use async mode for now */
+	mrc p15, 0, r0, c1, c0, 0
+	orr r0, r0, #0xc0000000
+	mcr p15, 0, r0, c1, c0, 0
+
+	/* restore return address */
+	ldr r1, =SYSCON_SCRATCH0
+	ldr lr, [r1]
+
+	mov pc, lr
diff --git a/cpu/arm920t/ep93xx/speed.c b/cpu/arm920t/ep93xx/speed.c
new file mode 100644
index 0000000..cc32ec7
--- /dev/null
+++ b/cpu/arm920t/ep93xx/speed.c
@@ -0,0 +1,120 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx PLL support.
+ *
+ * Copyright (C) 2009 Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+ *
+ * Based on the S3C24x0 speed.c, which is
+ *
+ * (C) Copyright 2001-2002
+ * Wolfgang Denk, DENX Software Engineering, <wd at denx.de>
+ *
+ * (C) Copyright 2002
+ * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+#include <div64.h>
+
+/* ------------------------------------------------------------------------- */
+/* NOTE: This describes the proper use of this file.
+ *
+ * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
+ *
+ * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
+ * the specified bus in HZ.
+ */
+/* ------------------------------------------------------------------------- */
+
+static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
+static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
+static char pclk_divisors[] = { 1, 2, 4, 8 };
+
+
+/* return the PLL output frequency */
+/* PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
+ * / (X2IPD + 1) / 2^PS
+ */
+static ulong get_PLLCLK(int pllreg)
+{
+	uint8_t i;
+	const uint32_t clkset = readl(pllreg);
+	uint64_t rate = CONFIG_SYS_CLK_FREQ;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
+	rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
+	do_div(rate, (clkset  & 0x1f) + 1);			/* X2IPD */
+	for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
+		rate >>= 1;
+
+	return rate;
+}
+
+/* return FCLK frequency */
+ulong get_FCLK()
+{
+	const uint32_t clkset1 = readl(SYSCON_CLKSET1);
+	const uint8_t fclk_div =
+		fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 0x7];
+	const ulong fclk_rate = get_PLLCLK(SYSCON_CLKSET1) / fclk_div;
+
+	return fclk_rate;
+}
+
+
+/* return HCLK frequency */
+ulong get_HCLK(void)
+{
+	const uint32_t clkset1 = readl(SYSCON_CLKSET1);
+	const uint8_t hclk_div =
+		hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 0x7];
+	const ulong hclk_rate = get_PLLCLK(SYSCON_CLKSET1) / hclk_div;
+
+	return hclk_rate;
+}
+
+
+/* return PCLK frequency */
+ulong get_PCLK(void)
+{
+	const uint32_t clkset1 = readl(SYSCON_CLKSET1);
+	const uint8_t pclk_div =
+		pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 0x3];
+	const ulong pclk_rate = get_HCLK() / pclk_div;
+
+	return pclk_rate;
+}
+
+
+/* return UCLK frequency */
+ulong get_UCLK(void)
+{
+	ulong uclk_rate;
+
+	const uint32_t value = readl(SYSCON_PWRCNT);
+	if (value & SYSCON_PWRCNT_UART_BAUD)
+		uclk_rate = CONFIG_SYS_CLK_FREQ;
+	else
+		uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
+
+	return uclk_rate;
+}
diff --git a/cpu/arm920t/ep93xx/timer.c b/cpu/arm920t/ep93xx/timer.c
new file mode 100644
index 0000000..28660d0
--- /dev/null
+++ b/cpu/arm920t/ep93xx/timer.c
@@ -0,0 +1,163 @@
+/* vim: set ts=8 sw=8 noet:
+ *
+ * Cirrus Logic EP93xx interrupt support.
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+ *
+ * Based on the original intr.c Cirrus Logic EP93xx Rev D. interrupt support,
+ * author unknown.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <common.h>
+
+#if defined(CONFIG_EP93XX)
+#include <linux/types.h>
+#include <asm/arch/ep93xx.h>
+#include <asm/io.h>
+
+
+static int timer_load_val;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+	return readl(TIMER1_VALUE) & 0xffff;
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+
+int timer_init(void)
+{
+	/* use timer 1 with 2KHz and free running */
+	writel(0x00, TIMER1_CONTROL);
+	if (timer_load_val == 0) {
+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+		 * (default) and prescaler = 16. Should be 10390
+		 * @33.25MHz and 15625 @ 50 MHz
+		 */
+
+		/* set to constant just now, until I resolve clocking issues */
+		timer_load_val = 21;
+	}
+	/* auto load, manual update of Timer 1 */
+	lastdec = timer_load_val;
+	writel(timer_load_val, TIMER1_LOAD);
+
+	/* Enable the timer and periodic mode */
+	writel(0xC0, TIMER1_CONTROL);
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+void udelay(unsigned long usec)
+{
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= (timer_load_val * 100);
+	tmo /= 1000;
+
+	tmo += get_timer(0);
+
+	while (get_timer_masked() < tmo)
+		/*NOP*/;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = READ_TIMER();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= (timer_load_val * 100);
+	tmo /= 1000;
+
+	reset_timer_masked();
+
+	while (get_timer_masked() < tmo)
+		/*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = timer_load_val * 100;
+	return tbclk;
+}
+
+
+#endif  /* defined(CONFIG_EP93XX) */
diff --git a/include/asm-arm/arch-ep93xx/ep93xx.h b/include/asm-arm/arch-ep93xx/ep93xx.h
new file mode 100644
index 0000000..47e2a21
--- /dev/null
+++ b/include/asm-arm/arch-ep93xx/ep93xx.h
@@ -0,0 +1,868 @@
+/* -----------------------------------------------------------------------------
+ * Cirrus Logic EP93xx register definitions.
+ *
+ * Copyright (C) 2009
+ * Matthias Kaehlcke <matthias at kaehlcke.net>
+ *
+ * Copyright (C) 2006
+ * Dominic Rath <Dominic.Rath at gmx.de>
+ *
+ * Copyright (C) 2004, 2005
+ * Cory T. Tusar, Videon Central, Inc., <ctusar at videon-central.com>
+ *
+ * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
+ *
+ * Copyright (C) 2004 Ray Lehtiniemi
+ * Copyright (C) 2003 Cirrus Logic, Inc
+ * Copyright (C) 1999 ARM Limited.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.	 See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#define EP93XX_AHB_BASE			0x80000000
+#define EP93XX_APB_BASE			0x80800000
+
+/* -----------------------------------------------------------------------------
+ * 0x80000000 - 0x8000FFFF: DMA
+ */
+#define DMA_OFFSET			0x000000
+#define DMA_BASE			(EP93XX_AHB_BASE | DMA_OFFSET)
+
+#define DMAMP_TX_0_CONTROL		(DMA_BASE + 0x0000)
+#define DMAMP_TX_0_INTERRUPT		(DMA_BASE + 0x0004)
+#define DMAMP_TX_0_PPALLOC		(DMA_BASE + 0x0008)
+#define DMAMP_TX_0_STATUS		(DMA_BASE + 0x000C)
+#define DMAMP_TX_0_REMAIN		(DMA_BASE + 0x0014)
+#define DMAMP_TX_0_MAXCNT0		(DMA_BASE + 0x0020)
+#define DMAMP_TX_0_BASE0		(DMA_BASE + 0x0024)
+#define DMAMP_TX_0_CURRENT0		(DMA_BASE + 0x0028)
+#define DMAMP_TX_0_MAXCNT1		(DMA_BASE + 0x0030)
+#define DMAMP_TX_0_BASE1		(DMA_BASE + 0x0034)
+#define DMAMP_TX_0_CURRENT1		(DMA_BASE + 0x0038)
+
+#define DMAMP_RX_1_CONTROL		(DMA_BASE + 0x0040)
+#define DMAMP_RX_1_INTERRUPT		(DMA_BASE + 0x0044)
+#define DMAMP_RX_1_PPALLOC		(DMA_BASE + 0x0048)
+#define DMAMP_RX_1_STATUS		(DMA_BASE + 0x004C)
+#define DMAMP_RX_1_REMAIN		(DMA_BASE + 0x0054)
+#define DMAMP_RX_1_MAXCNT0		(DMA_BASE + 0x0060)
+#define DMAMP_RX_1_BASE0		(DMA_BASE + 0x0064)
+#define DMAMP_RX_1_CURRENT0		(DMA_BASE + 0x0068)
+#define DMAMP_RX_1_MAXCNT1		(DMA_BASE + 0x0070)
+#define DMAMP_RX_1_BASE1		(DMA_BASE + 0x0074)
+#define DMAMP_RX_1_CURRENT1		(DMA_BASE + 0x0078)
+
+#define DMAMP_TX_2_CONTROL		(DMA_BASE + 0x0080)
+#define DMAMP_TX_2_INTERRUPT		(DMA_BASE + 0x0084)
+#define DMAMP_TX_2_PPALLOC		(DMA_BASE + 0x0088)
+#define DMAMP_TX_2_STATUS		(DMA_BASE + 0x008C)
+#define DMAMP_TX_2_REMAIN		(DMA_BASE + 0x0094)
+#define DMAMP_TX_2_MAXCNT0		(DMA_BASE + 0x00A0)
+#define DMAMP_TX_2_BASE0		(DMA_BASE + 0x00A4)
+#define DMAMP_TX_2_CURRENT0		(DMA_BASE + 0x00A8)
+#define DMAMP_TX_2_MAXCNT1		(DMA_BASE + 0x00B0)
+#define DMAMP_TX_2_BASE1		(DMA_BASE + 0x00B4)
+#define DMAMP_TX_2_CURRENT1		(DMA_BASE + 0x00B8)
+
+#define DMAMP_RX_3_CONTROL		(DMA_BASE + 0x00C0)
+#define DMAMP_RX_3_INTERRUPT		(DMA_BASE + 0x00C4)
+#define DMAMP_RX_3_PPALLOC		(DMA_BASE + 0x00C8)
+#define DMAMP_RX_3_STATUS		(DMA_BASE + 0x00CC)
+#define DMAMP_RX_3_REMAIN		(DMA_BASE + 0x00D4)
+#define DMAMP_RX_3_MAXCNT0		(DMA_BASE + 0x00E0)
+#define DMAMP_RX_3_BASE0		(DMA_BASE + 0x00E4)
+#define DMAMP_RX_3_CURRENT0		(DMA_BASE + 0x00E8)
+#define DMAMP_RX_3_MAXCNT1		(DMA_BASE + 0x00F0)
+#define DMAMP_RX_3_BASE1		(DMA_BASE + 0x00F4)
+#define DMAMP_RX_3_CURRENT1		(DMA_BASE + 0x00F8)
+
+#define DMAMM_0_CONTROL			(DMA_BASE + 0x0100)
+#define DMAMM_0_INTERRUPT		(DMA_BASE + 0x0104)
+#define DMAMM_0_STATUS			(DMA_BASE + 0x010C)
+#define DMAMM_0_BCR0			(DMA_BASE + 0x0110)
+#define DMAMM_0_BCR1			(DMA_BASE + 0x0114)
+#define DMAMM_0_SAR_BASE0		(DMA_BASE + 0x0118)
+#define DMAMM_0_SAR_BASE1		(DMA_BASE + 0x011C)
+#define DMAMM_0_SAR_CURRENT0		(DMA_BASE + 0x0124)
+#define DMAMM_0_SAR_CURRENT1		(DMA_BASE + 0x0128)
+#define DMAMM_0_DAR_BASE0		(DMA_BASE + 0x012C)
+#define DMAMM_0_DAR_BASE1		(DMA_BASE + 0x0130)
+#define DMAMM_0_DAR_CURRENT0		(DMA_BASE + 0x0134)
+#define DMAMM_0_DAR_CURRENT1		(DMA_BASE + 0x013C)
+
+#define DMAMM_1_CONTROL			(DMA_BASE + 0x0140)
+#define DMAMM_1_INTERRUPT		(DMA_BASE + 0x0144)
+#define DMAMM_1_STATUS			(DMA_BASE + 0x014C)
+#define DMAMM_1_BCR0			(DMA_BASE + 0x0150)
+#define DMAMM_1_BCR1			(DMA_BASE + 0x0154)
+#define DMAMM_1_SAR_BASE0		(DMA_BASE + 0x0158)
+#define DMAMM_1_SAR_BASE1		(DMA_BASE + 0x015C)
+#define DMAMM_1_SAR_CURRENT0		(DMA_BASE + 0x0164)
+#define DMAMM_1_SAR_CURRENT1		(DMA_BASE + 0x0168)
+#define DMAMM_1_DAR_BASE0		(DMA_BASE + 0x016C)
+#define DMAMM_1_DAR_BASE1		(DMA_BASE + 0x0170)
+#define DMAMM_1_DAR_CURRENT0		(DMA_BASE + 0x0174)
+#define DMAMM_1_DAR_CURRENT1		(DMA_BASE + 0x017C)
+
+#define DMAMP_RX_5_CONTROL		(DMA_BASE + 0x0200)
+#define DMAMP_RX_5_INTERRUPT		(DMA_BASE + 0x0204)
+#define DMAMP_RX_5_PPALLOC		(DMA_BASE + 0x0208)
+#define DMAMP_RX_5_STATUS		(DMA_BASE + 0x020C)
+#define DMAMP_RX_5_REMAIN		(DMA_BASE + 0x0214)
+#define DMAMP_RX_5_MAXCNT0		(DMA_BASE + 0x0220)
+#define DMAMP_RX_5_BASE0		(DMA_BASE + 0x0224)
+#define DMAMP_RX_5_CURRENT0		(DMA_BASE + 0x0228)
+#define DMAMP_RX_5_MAXCNT1		(DMA_BASE + 0x0230)
+#define DMAMP_RX_5_BASE1		(DMA_BASE + 0x0234)
+#define DMAMP_RX_5_CURRENT1		(DMA_BASE + 0x0238)
+
+#define DMAMP_TX_4_CONTROL		(DMA_BASE + 0x0240)
+#define DMAMP_TX_4_INTERRUPT		(DMA_BASE + 0x0244)
+#define DMAMP_TX_4_PPALLOC		(DMA_BASE + 0x0248)
+#define DMAMP_TX_4_STATUS		(DMA_BASE + 0x024C)
+#define DMAMP_TX_4_REMAIN		(DMA_BASE + 0x0254)
+#define DMAMP_TX_4_MAXCNT0		(DMA_BASE + 0x0260)
+#define DMAMP_TX_4_BASE0		(DMA_BASE + 0x0264)
+#define DMAMP_TX_4_CURRENT0		(DMA_BASE + 0x0268)
+#define DMAMP_TX_4_MAXCNT1		(DMA_BASE + 0x0270)
+#define DMAMP_TX_4_BASE1		(DMA_BASE + 0x0274)
+#define DMAMP_TX_4_CURRENT1		(DMA_BASE + 0x0278)
+
+#define DMAMP_RX_7_CONTROL		(DMA_BASE + 0x0280)
+#define DMAMP_RX_7_INTERRUPT		(DMA_BASE + 0x0284)
+#define DMAMP_RX_7_PPALLOC		(DMA_BASE + 0x0288)
+#define DMAMP_RX_7_STATUS		(DMA_BASE + 0x028C)
+#define DMAMP_RX_7_REMAIN		(DMA_BASE + 0x0294)
+#define DMAMP_RX_7_MAXCNT0		(DMA_BASE + 0x02A0)
+#define DMAMP_RX_7_BASE0		(DMA_BASE + 0x02A4)
+#define DMAMP_RX_7_CURRENT0		(DMA_BASE + 0x02A8)
+#define DMAMP_RX_7_MAXCNT1		(DMA_BASE + 0x02B0)
+#define DMAMP_RX_7_BASE1		(DMA_BASE + 0x02B4)
+#define DMAMP_RX_7_CURRENT1		(DMA_BASE + 0x02B8)
+
+#define DMAMP_TX_6_CONTROL		(DMA_BASE + 0x02C0)
+#define DMAMP_TX_6_INTERRUPT		(DMA_BASE + 0x02C4)
+#define DMAMP_TX_6_PPALLOC		(DMA_BASE + 0x02C8)
+#define DMAMP_TX_6_STATUS		(DMA_BASE + 0x02CC)
+#define DMAMP_TX_6_REMAIN		(DMA_BASE + 0x02D4)
+#define DMAMP_TX_6_MAXCNT0		(DMA_BASE + 0x02E0)
+#define DMAMP_TX_6_BASE0		(DMA_BASE + 0x02E4)
+#define DMAMP_TX_6_CURRENT0		(DMA_BASE + 0x02E8)
+#define DMAMP_TX_6_MAXCNT1		(DMA_BASE + 0x02F0)
+#define DMAMP_TX_6_BASE1		(DMA_BASE + 0x02F4)
+#define DMAMP_TX_6_CURRENT1		(DMA_BASE + 0x02F8)
+
+#define DMAMP_RX_9_CONTROL		(DMA_BASE + 0x0300)
+#define DMAMP_RX_9_INTERRUPT		(DMA_BASE + 0x0304)
+#define DMAMP_RX_9_PPALLOC		(DMA_BASE + 0x0308)
+#define DMAMP_RX_9_STATUS		(DMA_BASE + 0x030C)
+#define DMAMP_RX_9_REMAIN		(DMA_BASE + 0x0314)
+#define DMAMP_RX_9_MAXCNT0		(DMA_BASE + 0x0320)
+#define DMAMP_RX_9_BASE0		(DMA_BASE + 0x0324)
+#define DMAMP_RX_9_CURRENT0		(DMA_BASE + 0x0328)
+#define DMAMP_RX_9_MAXCNT1		(DMA_BASE + 0x0330)
+#define DMAMP_RX_9_BASE1		(DMA_BASE + 0x0334)
+#define DMAMP_RX_9_CURRENT1		(DMA_BASE + 0x0338)
+
+#define DMAMP_TX_8_CONTROL		(DMA_BASE + 0x0340)
+#define DMAMP_TX_8_INTERRUPT		(DMA_BASE + 0x0344)
+#define DMAMP_TX_8_PPALLOC		(DMA_BASE + 0x0348)
+#define DMAMP_TX_8_STATUS		(DMA_BASE + 0x034C)
+#define DMAMP_TX_8_REMAIN		(DMA_BASE + 0x0354)
+#define DMAMP_TX_8_MAXCNT0		(DMA_BASE + 0x0360)
+#define DMAMP_TX_8_BASE0		(DMA_BASE + 0x0364)
+#define DMAMP_TX_8_CURRENT0		(DMA_BASE + 0x0368)
+#define DMAMP_TX_8_MAXCNT1		(DMA_BASE + 0x0370)
+#define DMAMP_TX_8_BASE1		(DMA_BASE + 0x0374)
+#define DMAMP_TX_8_CURRENT1		(DMA_BASE + 0x0378)
+
+#define DMA_ARBITRATION			(DMA_BASE + 0x0380)
+#define DMA_INTERRUPT			(DMA_BASE + 0x03C0)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80010000 - 0x8001FFFF: Ethernet MAC
+ */
+#define MAC_OFFSET			0x010000
+#define MAC_BASE			(EP93XX_AHB_BASE | MAC_OFFSET)
+
+#define MAC_RXCTL			(MAC_BASE + 0x0000)
+#define MAC_TXCTL			(MAC_BASE + 0x0004)
+#define MAC_TESTCTL			(MAC_BASE + 0x0008)
+#define MAC_MIICMD			(MAC_BASE + 0x0010)
+#define MAC_MIIDATA			(MAC_BASE + 0x0014)
+#define MAC_MIISTS			(MAC_BASE + 0x0018)
+#define MAC_SELFCTL			(MAC_BASE + 0x0020)
+#define MAC_INTEN			(MAC_BASE + 0x0024)
+#define MAC_INTSTSP			(MAC_BASE + 0x0028)
+#define MAC_INTSTSC			(MAC_BASE + 0x002C)
+#define MAC_DIAGAD			(MAC_BASE + 0x0038)
+#define MAC_DIAGDATA			(MAC_BASE + 0x003C)
+#define MAC_GT				(MAC_BASE + 0x0040)
+#define MAC_FCT				(MAC_BASE + 0x0044)
+#define MAC_FCF				(MAC_BASE + 0x0048)
+#define MAC_AFP				(MAC_BASE + 0x004C)
+#define MAC_HASHTBL			(MAC_BASE + 0x0050)
+#define MAC_INDAD			(MAC_BASE + 0x0050)
+#define MAC_INDAD_UPPER			(MAC_BASE + 0x0054)
+#define MAC_GIINTSTS			(MAC_BASE + 0x0060)
+#define MAC_GIINTMSK			(MAC_BASE + 0x0064)
+#define MAC_GIINTROSTS			(MAC_BASE + 0x0068)
+#define MAC_GIINTFRC			(MAC_BASE + 0x006C)
+#define MAC_TXCOLLCNT			(MAC_BASE + 0x0070)
+#define MAC_RXMISSCNT			(MAC_BASE + 0x0074)
+#define MAC_RXRUNTCNT			(MAC_BASE + 0x0078)
+#define MAC_BMCTL			(MAC_BASE + 0x0080)
+#define MAC_BMSTS			(MAC_BASE + 0x0084)
+#define MAC_RXBCA			(MAC_BASE + 0x0088)
+#define MAC_RXDQBADD			(MAC_BASE + 0x0090)
+#define MAC_RXDQBLEN			(MAC_BASE + 0x0094)
+#define MAC_RXDQCURLEN			(MAC_BASE + 0x0096)
+#define MAC_RXDQCURADD			(MAC_BASE + 0x0098)
+#define MAC_RXDENQ			(MAC_BASE + 0x009C)
+#define MAC_RXSTSQBADD			(MAC_BASE + 0x00A0)
+#define MAC_RXSTSQBLEN			(MAC_BASE + 0x00A4)
+#define MAC_RXSTSQCURLEN		(MAC_BASE + 0x00A6)
+#define MAC_RXSTSQCURADD		(MAC_BASE + 0x00A8)
+#define MAC_RXSTSENQ			(MAC_BASE + 0x00AC)
+#define MAC_TXDQBADD			(MAC_BASE + 0x00B0)
+#define MAC_TXDQBLEN			(MAC_BASE + 0x00B4)
+#define MAC_TXDQCURLEN			(MAC_BASE + 0x00B6)
+#define MAC_TXDQCURADD			(MAC_BASE + 0x00B8)
+#define MAC_TXDENQ			(MAC_BASE + 0x00BC)
+#define MAC_TXSTSQBADD			(MAC_BASE + 0x00C0)
+#define MAC_TXSTSQBLEN			(MAC_BASE + 0x00C4)
+#define MAC_TXSTSQCURLEN		(MAC_BASE + 0x00C6)
+#define MAC_TXSTSQCURADD		(MAC_BASE + 0x00C8)
+#define MAC_RXBUFTHRSHLD		(MAC_BASE + 0x00D0)
+#define MAC_TXBUFTHRSHLD		(MAC_BASE + 0x00D4)
+#define MAC_RXSTSTHRSHLD		(MAC_BASE + 0x00D8)
+#define MAC_TXSTSTHRSHLD		(MAC_BASE + 0x00DC)
+#define MAC_RXDTHRSHLD			(MAC_BASE + 0x00E0)
+#define MAC_TXDTHRSHLD			(MAC_BASE + 0x00E4)
+#define MAC_MAXFRMLEN			(MAC_BASE + 0x00E8)
+#define MAC_RXHDRLEN			(MAC_BASE + 0x00EC)
+
+#define SELFCTL_RWP		(1 << 7)
+#define SELFCTL_GPO0		(1 << 5)
+#define SELFCTL_PUWE		(1 << 4)
+#define SELFCTL_PDWE		(1 << 3)
+#define SELFCTL_MIIL		(1 << 2)
+#define SELFCTL_RESET		(1 << 0)
+
+#define INTSTS_RWI		(1 << 30)
+#define INTSTS_RXMI		(1 << 29)
+#define INTSTS_RXBI		(1 << 28)
+#define INTSTS_RXSQI		(1 << 27)
+#define INTSTS_TXLEI		(1 << 26)
+#define INTSTS_ECIE		(1 << 25)
+#define INTSTS_TXUHI		(1 << 24)
+#define INTSTS_MOI		(1 << 18)
+#define INTSTS_TXCOI		(1 << 17)
+#define INTSTS_RXROI		(1 << 16)
+#define INTSTS_MIII		(1 << 12)
+#define INTSTS_PHYI		(1 << 11)
+#define INTSTS_TI		(1 << 10)
+#define INTSTS_AHBE		(1 << 8)
+#define INTSTS_OTHER		(1 << 4)
+#define INTSTS_TXSQ		(1 << 3)
+#define INTSTS_RXSQ		(1 << 2)
+
+#define BMCTL_MT		(1 << 13)
+#define BMCTL_TT		(1 << 12)
+#define BMCTL_UNH		(1 << 11)
+#define BMCTL_TXCHR		(1 << 10)
+#define BMCTL_TXDIS		(1 << 9)
+#define BMCTL_TXEN		(1 << 8)
+#define BMCTL_EH2		(1 << 6)
+#define BMCTL_EH1		(1 << 5)
+#define BMCTL_EEOB		(1 << 4)
+#define BMCTL_RXCHR		(1 << 2)
+#define BMCTL_RXDIS		(1 << 1)
+#define BMCTL_RXEN		(1 << 0)
+
+#define BMSTS_TXACT		(1 << 7)
+#define BMSTS_TP		(1 << 4)
+#define BMSTS_RXACT		(1 << 3)
+#define BMSTS_QID_MASK		0x07
+#define BMSTS_QID_RXDATA	0x00
+#define BMSTS_QID_TXDATA	0x01
+#define BMSTS_QID_RXSTS		0x02
+#define BMSTS_QID_TXSTS		0x03
+#define BMSTS_QID_RXDESC	0x04
+#define BMSTS_QID_TXDESC	0x05
+
+#define AFP_MASK		0x07
+#define AFP_IAPRIMARY		0x00
+#define AFP_IASECONDARY1	0x01
+#define AFP_IASECONDARY2	0x02
+#define AFP_IASECONDARY3	0x03
+#define AFP_TX			0x06
+#define AFP_HASH		0x07
+
+#define RXCTL_PAUSEA		(1 << 20)
+#define RXCTL_RXFCE1		(1 << 19)
+#define RXCTL_RXFCE0		(1 << 18)
+#define RXCTL_BCRC		(1 << 17)
+#define RXCTL_SRXON		(1 << 16)
+#define RXCTL_RCRCA		(1 << 13)
+#define RXCTL_RA		(1 << 12)
+#define RXCTL_PA		(1 << 11)
+#define RXCTL_BA		(1 << 10)
+#define RXCTL_MA		(1 << 9)
+#define RXCTL_IAHA		(1 << 8)
+#define RXCTL_IA3		(1 << 3)
+#define RXCTL_IA2		(1 << 2)
+#define RXCTL_IA1		(1 << 1)
+#define RXCTL_IA0		(1 << 0)
+
+#define TXCTL_DEFDIS		(1 << 7)
+#define TXCTL_MBE		(1 << 6)
+#define TXCTL_ICRC		(1 << 5)
+#define TXCTL_TPD		(1 << 4)
+#define TXCTL_OCOLL		(1 << 3)
+#define TXCTL_SP		(1 << 2)
+#define TXCTL_PB		(1 << 1)
+#define TXCTL_STXON		(1 << 0)
+
+#define MIICMD_REGAD_MASK	(0x001F)
+#define MIICMD_PHYAD_MASK	(0x03E0)
+#define MIICMD_OPCODE_MASK	(0xC000)
+#define MIICMD_PHYAD_8950	(0x0000)
+#define MIICMD_OPCODE_READ	(0x8000)
+#define MIICMD_OPCODE_WRITE	(0x4000)
+
+#define MIISTS_BUSY		(1 << 0)
+
+/* -----------------------------------------------------------------------------
+ * 0x80020000 - 0x8002FFFF: USB OHCI
+ */
+#define USB_OFFSET			0x020000
+#define USB_BASE			(EP93XX_AHB_BASE | USB_OFFSET)
+
+#define USB_HCREVISION			(USB_BASE + 0x0000)
+#define USB_HCCONTROL			(USB_BASE + 0x0004)
+#define USB_HCCOMMANDSTATUS		(USB_BASE + 0x0008)
+#define USB_HCINTERRUPTSTATUS		(USB_BASE + 0x000C)
+#define USB_HCINTERRUPTENABLE		(USB_BASE + 0x0010)
+#define USB_HCINTERRUPTDISABLE		(USB_BASE + 0x0014)
+#define USB_HCHCCA			(USB_BASE + 0x0018)
+#define USB_HCPERIODCURRENTED		(USB_BASE + 0x001C)
+#define USB_HCCONTROLHEADED		(USB_BASE + 0x0020)
+#define USB_HCCONTROLCURRENTED		(USB_BASE + 0x0024)
+#define USB_HCBULKHEADED		(USB_BASE + 0x0028)
+#define USB_HCBULKCURRENTED		(USB_BASE + 0x002C)
+#define USB_HCDONEHEAD			(USB_BASE + 0x0030)
+#define USB_HCFMINTERVAL		(USB_BASE + 0x0034)
+#define USB_HCFMREMAINING		(USB_BASE + 0x0038)
+#define USB_HCFMNUMBER			(USB_BASE + 0x003C)
+#define USB_HCPERIODICSTART		(USB_BASE + 0x0040)
+#define USB_HCLSTHRESHOLD		(USB_BASE + 0x0044)
+#define USB_HCRHDESCRIPTORA		(USB_BASE + 0x0048)
+#define USB_HCRHDESCRIPTORB		(USB_BASE + 0x004C)
+#define USB_HCRHSTATUS			(USB_BASE + 0x0050)
+#define USB_HCRHPORTSTATUS0		(USB_BASE + 0x0054)
+#if (defined(CONFIG_EP9302) || defined(CONFIG_EP9307) ||\
+	defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define USB_HCRHPORTSTATUS1		(USB_BASE + 0x0058)
+#endif
+#define USB_HCRHPORTSTATUS2		(USB_BASE + 0x005C)
+#define USB_CFGCTRL			(USB_BASE + 0x0080)
+#define USB_HCISTS			(USB_BASE + 0x0084)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80030000 - 0x8003FFFF: Raster engine
+ */
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
+#define RASTER_OFFSET			0x030000
+#define RASTER_BASE			(EP93XX_AHB_BASE | RASTER_OFFSET)
+
+#define RASTER_VLINESTOTAL		(RASTER_BASE + 0x0000)
+#define RASTER_VSYNCSTRTSTOP		(RASTER_BASE + 0x0004)
+#define RASTER_VACTIVESTRTSTOP		(RASTER_BASE + 0x0008)
+#define RASTER_VCLKSTRTSTOP		(RASTER_BASE + 0x000C)
+#define RASTER_HCLKSTOTAL		(RASTER_BASE + 0x0010)
+#define RASTER_HSYNCSTRTSTOP		(RASTER_BASE + 0x0014)
+#define RASTER_HACTIVESTRTSTOP		(RASTER_BASE + 0x0018)
+#define RASTER_HCLKSTRTSTOP		(RASTER_BASE + 0x001C)
+#define RASTER_BRIGHTNESS		(RASTER_BASE + 0x0020)
+#define RASTER_VIDEOATTRIBS		(RASTER_BASE + 0x0024)
+#define RASTER_VIDSCRNPAGE		(RASTER_BASE + 0x0028)
+#define RASTER_VIDSCRNHPG		(RASTER_BASE + 0x002C)
+#define RASTER_SCRNLINES		(RASTER_BASE + 0x0030)
+#define RASTER_LINELENGTH		(RASTER_BASE + 0x0034)
+#define RASTER_VLINESTEP		(RASTER_BASE + 0x0038)
+#define RASTER_LINECARRY		(RASTER_BASE + 0x003C)
+#define RASTER_BLINKRATE		(RASTER_BASE + 0x0040)
+#define RASTER_BLINKMASK		(RASTER_BASE + 0x0044)
+#define RASTER_BLINKPATTRN		(RASTER_BASE + 0x0048)
+#define RASTER_PATTRNMASK		(RASTER_BASE + 0x004C)
+#define RASTER_BG_OFFSET		(RASTER_BASE + 0x0050)
+#define RASTER_PIXELMODE		(RASTER_BASE + 0x0054)
+#define RASTER_PARLLIFOUT		(RASTER_BASE + 0x0058)
+#define RASTER_PARLLIFIN		(RASTER_BASE + 0x005C)
+#define RASTER_CURSOR_ADR_START		(RASTER_BASE + 0x0060)
+#define RASTER_CURSOR_ADR_RESET		(RASTER_BASE + 0x0064)
+#define RASTER_CURSORSIZE		(RASTER_BASE + 0x0068)
+#define RASTER_CURSORCOLOR1		(RASTER_BASE + 0x006C)
+#define RASTER_CURSORCOLOR2		(RASTER_BASE + 0x0070)
+#define RASTER_CURSORXYLOC		(RASTER_BASE + 0x0074)
+#define RASTER_CURSOR_DHSCAN_LH_YLOC	(RASTER_BASE + 0x0078)
+#define RASTER_REALITI_SWLOCK		(RASTER_BASE + 0x007C)
+#define RASTER_GS_LUT			(RASTER_BASE + 0x0080)
+#define RASTER_REALITI_TCR		(RASTER_BASE + 0x0100)
+#define RASTER_REALITI_TISRA		(RASTER_BASE + 0x0104)
+#define RASTER_REALITI_TISRB		(RASTER_BASE + 0x0108)
+#define RASTER_CURSOR_TISR		(RASTER_BASE + 0x010C)
+#define RASTER_REALITI_TOCRA		(RASTER_BASE + 0x0110)
+#define RASTER_REALITI_TOCRB		(RASTER_BASE + 0x0114)
+#define RASTER_FIFO_TOCRA		(RASTER_BASE + 0x0118)
+#define RASTER_FIFO_TOCRB		(RASTER_BASE + 0x011C)
+#define RASTER_BLINK_TISR		(RASTER_BASE + 0x0120)
+#define RASTER_DAC_TISRA		(RASTER_BASE + 0x0124)
+#define RASTER_DAC_TISRB		(RASTER_BASE + 0x0128)
+#define RASTER_SHIFT_TISR		(RASTER_BASE + 0x012C)
+#define RASTER_DACMUX_TOCRA		(RASTER_BASE + 0x0130)
+#define RASTER_DACMUX_TOCRB		(RASTER_BASE + 0x0134)
+#define RASTER_PELMUX_TOCR		(RASTER_BASE + 0x0138)
+#define RASTER_VIDEO_TOCRA		(RASTER_BASE + 0x013C)
+#define RASTER_VIDEO_TOCRB		(RASTER_BASE + 0x0140)
+#define RASTER_YCRCB_TOCR		(RASTER_BASE + 0x0144)
+#define RASTER_CURSOR_TOCR		(RASTER_BASE + 0x0148)
+#define RASTER_VIDEO_TOCRC		(RASTER_BASE + 0x014C)
+#define RASTER_SHIFT_TOCR		(RASTER_BASE + 0x0150)
+#define RASTER_BLINK_TOCR		(RASTER_BASE + 0x0154)
+#define RASTER_REALITI_TCER		(RASTER_BASE + 0x0180)
+#define RASTER_SIGVAL			(RASTER_BASE + 0x0200)
+#define RASTER_SIGCTL			(RASTER_BASE + 0x0204)
+#define RASTER_VSIGSTRTSTOP		(RASTER_BASE + 0x0208)
+#define RASTER_HSIGSTRTSTOP		(RASTER_BASE + 0x020C)
+#define RASTER_SIGCLR			(RASTER_BASE + 0x0210)
+#define RASTER_ACRATE			(RASTER_BASE + 0x0214)
+#define RASTER_LUTCONT			(RASTER_BASE + 0x0218)
+#define RASTER_VBLANKSTRTSTOP		(RASTER_BASE + 0x0228)
+#define RASTER_HBLANKSTRTSTOP		(RASTER_BASE + 0x022C)
+#define RASTER_LUT			(RASTER_BASE + 0x0400)
+#define RASTER_CURSORBLINK1		(RASTER_BASE + 0x021C)
+#define RASTER_CURSORBLINK2		(RASTER_BASE + 0x0220)
+#define RASTER_CURSORBLINK		(RASTER_BASE + 0x0224)
+#define RASTER_EOLOFFSET		(RASTER_BASE + 0x0230)
+#define RASTER_FIFOLEVEL		(RASTER_BASE + 0x0234)
+#define RASTER_GS_LUT2			(RASTER_BASE + 0x0280)
+#define RASTER_GS_LUT3			(RASTER_BASE + 0x0300)
+#define RASTER_COLOR_LUT		(RASTER_BASE + 0x0400)
+#endif
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80040000 - 0x8004FFFF: Graphics accelerator
+ */
+#if defined(CONFIG_EP9315)
+#define GFX_OFFSET			0x040000
+#define GFX_BASE			(EP93XX_AHB_BASE | GFX_OFFSET)
+#endif
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80050000 - 0x8005FFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80060000 - 0x8006FFFF: SDRAM controller
+ */
+#define SDRAM_OFFSET			0x060000
+#define SDRAM_BASE			(EP93XX_AHB_BASE | SDRAM_OFFSET)
+
+#define SDRAM_GLCONFIG			(SDRAM_BASE + 0x0004)
+#define SDRAM_REFRSHTIMR		(SDRAM_BASE + 0x0008)
+#define SDRAM_BOOTSTS			(SDRAM_BASE + 0x000C)
+#define SDRAM_DEVCFG0			(SDRAM_BASE + 0x0010)
+#define SDRAM_DEVCFG1			(SDRAM_BASE + 0x0014)
+#define SDRAM_DEVCFG2			(SDRAM_BASE + 0x0018)
+#define SDRAM_DEVCFG3			(SDRAM_BASE + 0x001C)
+
+#define SDRAM_DEVCFG_EXTBUSWIDTH	(1 << 2)
+#define SDRAM_DEVCFG_BANKCOUNT		(1 << 3)
+#define SDRAM_DEVCFG_SROMLL		(1 << 5)
+#define SDRAM_DEVCFG_CASLAT_2		0x00010000
+#define SDRAM_DEVCFG_RASTOCAS_2		0x00200000
+
+#define GLCONFIG_INIT			(1 << 0)
+#define GLCONFIG_MRS			(1 << 1)
+#define GLCONFIG_SMEMBUSY		(1 << 5)
+#define GLCONFIG_LCR			(1 << 6)
+#define GLCONFIG_REARBEN		(1 << 7)
+#define GLCONFIG_CLKSHUTDOWN		(1 << 30)
+#define GLCONFIG_CKE			(1 << 31)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80070000 - 0x8007FFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
+ */
+#define SMC_OFFSET			0x080000
+#define SMC_BASE			(EP93XX_AHB_BASE | SMC_OFFSET)
+
+#define SMC_BCR0			(SMC_BASE + 0x0000)
+#define SMC_BCR1			(SMC_BASE + 0x0004)
+#define SMC_BCR2			(SMC_BASE + 0x0008)
+#define SMC_BCR3			(SMC_BASE + 0x000C)
+#define SMC_BCR6			(SMC_BASE + 0x0018)
+#define SMC_BCR7			(SMC_BASE + 0x001C)
+#if (defined(CONFIG_EP9307) || defined(CONFIG_EP9315))
+#define SMC_PCATTRIBUTE			(SMC_BASE + 0x0020)
+#define SMC_PCCOMMON			(SMC_BASE + 0x0024)
+#define SMC_PCIO			(SMC_BASE + 0x0028)
+#define SMC_PCMCIACTRL			(SMC_BASE + 0x0040)
+#endif
+
+#define SMC_BCR_IDCY_SHIFT	0
+#define SMC_BCR_WST1_SHIFT	5
+#define SMC_BCR_BLE		(1 << 10)
+#define SMC_BCR_WST2_SHIFT	11
+#define SMC_BCR_MW_SHIFT	28
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80090000 - 0x8009FFFF: Boot ROM
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x800A0000 - 0x800AFFFF: IDE interface
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x800B0000 - 0x800BFFFF: VIC1
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x800C0000 - 0x800CFFFF: VIC2
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x800D0000 - 0x800FFFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80800000 - 0x8080FFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80810000 - 0x8081FFFF: Timers
+ */
+#define TIMER_OFFSET		0x010000
+#define TIMER_BASE		(EP93XX_APB_BASE | TIMER_OFFSET)
+
+#define TIMER1_LOAD		(TIMER_BASE + 0x0000)
+#define TIMER1_VALUE		(TIMER_BASE + 0x0004)
+#define TIMER1_CONTROL		(TIMER_BASE + 0x0008)
+#define TIMER1_CLEAR		(TIMER_BASE + 0x000c)
+
+#define TIMER2_LOAD		(TIMER_BASE + 0x0020)
+#define TIMER2_VALUE		(TIMER_BASE + 0x0024)
+#define TIMER2_CONTROL		(TIMER_BASE + 0x0028)
+#define TIMER2_CLEAR		(TIMER_BASE + 0x002c)
+
+#define TIMER3_LOAD		(TIMER_BASE + 0x0080)
+#define TIMER3_VALUE		(TIMER_BASE + 0x0084)
+#define TIMER3_CONTROL		(TIMER_BASE + 0x0088)
+#define TIMER3_CLEAR		(TIMER_BASE + 0x008c)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80820000 - 0x8082FFFF: I2S
+ */
+#define I2S_OFFSET		0x020000
+#define I2S_BASE		(EP93XX_APB_BASE | I2S_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80830000 - 0x8083FFFF: Security
+ */
+#define SECURITY_OFFSET		0x030000
+#define SECURITY_BASE		(EP93XX_APB_BASE | SECURITY_OFFSET)
+
+#define EXTENSIONID		(SECURITY_BASE + 0x2714)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80840000 - 0x8084FFFF: GPIO
+ */
+#define GPIO_OFFSET		0x040000
+#define GPIO_BASE		(EP93XX_APB_BASE | GPIO_OFFSET)
+
+#define GPIO_PADR		(GPIO_BASE + 0x0000)
+#define GPIO_PBDR		(GPIO_BASE + 0x0004)
+#define GPIO_PCDR		(GPIO_BASE + 0x0008)
+#define GPIO_PDDR		(GPIO_BASE + 0x000c)
+
+#define GPIO_PADDR		(GPIO_BASE + 0x0010)
+#define GPIO_PBDDR		(GPIO_BASE + 0x0014)
+#define GPIO_PCDDR		(GPIO_BASE + 0x0018)
+#define GPIO_PDDDR		(GPIO_BASE + 0x001c)
+
+#define GPIO_PEDR		(GPIO_BASE + 0x0020)
+#define GPIO_PEDDR		(GPIO_BASE + 0x0024)
+#define GPIO_PFDR		(GPIO_BASE + 0x0030)
+#define GPIO_PFDDR		(GPIO_BASE + 0x0034)
+#define GPIO_PGDR		(GPIO_BASE + 0x0038)
+#define GPIO_PGDDR		(GPIO_BASE + 0x003c)
+#define GPIO_PHDR		(GPIO_BASE + 0x0040)
+#define GPIO_PHDDR		(GPIO_BASE + 0x0044)
+
+#define GPIO_FINTTYPE1		(GPIO_BASE + 0x004c)
+#define GPIO_FINTTYPE2		(GPIO_BASE + 0x0050)
+#define GPIO_FEOI		(GPIO_BASE + 0x0054)
+#define GPIO_FINTEN		(GPIO_BASE + 0x0058)
+#define GPIO_INTSTSF		(GPIO_BASE + 0x005c)
+#define GPIO_RAWINTSTSF		(GPIO_BASE + 0x0060)
+#define GPIO_FDB		(GPIO_BASE + 0x0064)
+
+#define GPIO_AINTTYPE1		(GPIO_BASE + 0x0090)
+#define GPIO_AINTTYPE2		(GPIO_BASE + 0x0094)
+#define GPIO_AEOI		(GPIO_BASE + 0x0098)
+#define GPIO_AINTEN		(GPIO_BASE + 0x009c)
+#define GPIO_INTSTSA		(GPIO_BASE + 0x00a0)
+#define GPIO_RAWINTSTSA		(GPIO_BASE + 0x00a4)
+#define GPIO_ADB		(GPIO_BASE + 0x00a8)
+
+#define GPIO_BINTTYPE1		(GPIO_BASE + 0x00ac)
+#define GPIO_BINTTYPE2		(GPIO_BASE + 0x00b0)
+#define GPIO_BEOI		(GPIO_BASE + 0x00b4)
+#define GPIO_BINTEN		(GPIO_BASE + 0x00b8)
+#define GPIO_INTSTSB		(GPIO_BASE + 0x00bc)
+#define GPIO_RAWINTSTSB		(GPIO_BASE + 0x00c0)
+#define GPIO_BDB		(GPIO_BASE + 0x00c4)
+
+#define GPIO_EEDRIVE		(GPIO_BASE + 0x00c8)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80850000 - 0x8087FFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80880000 - 0x8088FFFF: AAC
+ */
+#define AAC_OFFSET		0x080000
+#define AAC_BASE		(EP93XX_APB_BASE | AAC_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80890000 - 0x8089FFFF: Reserved
+ */
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808A0000 - 0x808AFFFF: SPI
+ */
+#define SPI_OFFSET		0x0A0000
+#define SPI_BASE		(EP93XX_APB_BASE | SPI_OFFSET)
+
+#define SPI_SSP1CR0		(SPI_BASE + 0x0000)
+#define SPI_SSP1CR1		(SPI_BASE + 0x0004)
+#define SPI_SSP1DR		(SPI_BASE + 0x0008)
+#define SPI_SSP1SR		(SPI_BASE + 0x000c)
+#define SPI_SSP1CPSR		(SPI_BASE + 0x0010)
+#define SPI_SSP1IIR		(SPI_BASE + 0x0014)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808B0000 - 0x808BFFFF: IrDA
+ */
+#define IRDA_OFFSET		0x0B0000
+#define IRDA_BASE		(EP93XX_APB_BASE | IRDA_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808C0000 - 0x808CFFFF: UART1
+ */
+#define UART1_OFFSET		0x0C0000
+#define UART1_BASE		(EP93XX_APB_BASE | UART1_OFFSET)
+
+#define UART1_DATA		(UART1_BASE + 0x0000)
+#define UART1_RXSTS		(UART1_BASE + 0x0004)
+#define UART1_LIN_CTRLHIGH	(UART1_BASE + 0x0008)
+#define UART1_LIN_CTRLMID	(UART1_BASE + 0x000c)
+#define UART1_LIN_CTRLLOW	(UART1_BASE + 0x0010)
+#define UART1_CTRL		(UART1_BASE + 0x0014)
+#define UART1_FLAG		(UART1_BASE + 0x0018)
+#define UART1_INTIDINTCLR	(UART1_BASE + 0x001c)
+
+#define UART1_DMA_CTRL		(UART1_BASE + 0x0028)
+
+#define UART1_MODEM_CTRL	(UART1_BASE + 0x0100)
+#define UART1_MODEM_STS		(UART1_BASE + 0x0104)
+
+#define UART1_HDLC_CTRL		(UART1_BASE + 0x020c)
+#define UART1_HDLC_ADDMTCHVAL	(UART1_BASE + 0x0210)
+#define UART1_HDLC_ADDMASK	(UART1_BASE + 0x0214)
+#define UART1_HDLC_RXINFOBUF	(UART1_BASE + 0x0218)
+#define UART1_HDLC_STS		(UART1_BASE + 0x021c)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808D0000 - 0x808DFFFF: UART2
+ */
+#define UART2_OFFSET		0x0D0000
+#define UART2_BASE		(EP93XX_APB_BASE | UART2_OFFSET)
+
+#define UART2_DATA		(UART2_BASE + 0x0000)
+#define UART2_RXSTS		(UART2_BASE + 0x0004)
+#define UART2_LIN_CTRLHIGH	(UART2_BASE + 0x0008)
+#define UART2_LIN_CTRLMID	(UART2_BASE + 0x000c)
+#define UART2_LIN_CTRLLOW	(UART2_BASE + 0x0010)
+#define UART2_CTRL		(UART2_BASE + 0x0014)
+#define UART2_FLAG		(UART2_BASE + 0x0018)
+#define UART2_INTIDINTCLR	(UART2_BASE + 0x001c)
+#define UART2_IRLOWPWRCNTR	(UART2_BASE + 0x0020)
+
+#define UART2_DMA_CTRL		(UART2_BASE + 0x0028)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808E0000 - 0x808EFFFF: UART3
+ */
+#define UART3_OFFSET		0x0E0000
+#define UART3_BASE		(EP93XX_APB_BASE | UART3_OFFSET)
+
+#define UART3_DATA		(UART3_BASE + 0x0000)
+#define UART3_RXSTS		(UART3_BASE + 0x0004)
+#define UART3_LIN_CTRLHIGH	(UART3_BASE + 0x0008)
+#define UART3_LIN_CTRLMID	(UART3_BASE + 0x000c)
+#define UART3_LIN_CTRLLOW	(UART3_BASE + 0x0010)
+#define UART3_CTRL		(UART3_BASE + 0x0014)
+#define UART3_FLAG		(UART3_BASE + 0x0018)
+#define UART3_INTIDINTCLR	(UART3_BASE + 0x001c)
+#define UART3_IRLOWPWRCNTR	(UART3_BASE + 0x0020)
+
+#define UART3_DMA_CTRL		(UART3_BASE + 0x0028)
+
+#define UART3_MODEM_CTRL	(UART3_BASE + 0x0100)
+#define UART3_MODEM_STS		(UART3_BASE + 0x0104)
+#define UART2_MODEM_TSTCTRL	(UART2_BASE + 0x0108)
+
+#define UART3_HDLC_CTRL		(UART3_BASE + 0x020c)
+#define UART3_HDLC_ADDMTCHVAL	(UART3_BASE + 0x0210)
+#define UART3_HDLC_ADDMASK	(UART3_BASE + 0x0214)
+#define UART3_HDLC_RXINFOBUF	(UART3_BASE + 0x0218)
+#define UART3_HDLC_STS		(UART3_BASE + 0x021c)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x808F0000 - 0x808FFFFF: Key Matrix
+ */
+#define KEY_OFFSET		0x0F0000
+#define KEY_BASE		(EP93XX_APB_BASE | KEY_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80900000 - 0x8090FFFF: Touchscreen
+ */
+#define TOUCH_OFFSET		0x900000
+#define TOUCH_BASE		(EP93XX_APB_BASE | TOUCH_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
+ */
+#define PWM_OFFSET		0x910000
+#define PWM_BASE		(EP93XX_APB_BASE | PWM_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80920000 - 0x8092FFFF: Real time clock
+ */
+#define RTC_OFFSET		0x920000
+#define RTC_BASE		(EP93XX_APB_BASE | RTC_OFFSET)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80930000 - 0x8093FFFF: Syscon
+ */
+#define SYSCON_OFFSET		0x930000
+#define SYSCON_BASE		(EP93XX_APB_BASE | SYSCON_OFFSET)
+
+#define SYSCON_PWRSTS		(SYSCON_BASE + 0x0000)
+#define SYSCON_PWRCNT		(SYSCON_BASE + 0x0004)
+#define SYSCON_HALT		(SYSCON_BASE + 0x0008)
+#define SYSCON_STBY		(SYSCON_BASE + 0x000c)
+#define SYSCON_TEOI		(SYSCON_BASE + 0x0018)
+#define SYSCON_STFCLR		(SYSCON_BASE + 0x001c)
+#define SYSCON_CLKSET1		(SYSCON_BASE + 0x0020)
+#define SYSCON_CLKSET2		(SYSCON_BASE + 0x0024)
+#define SYSCON_SCRATCH0		(SYSCON_BASE + 0x0040)
+#define SYSCON_SCRATCH1		(SYSCON_BASE + 0x0044)
+#define SYSCON_APBWAIT		(SYSCON_BASE + 0x0050)
+#define SYSCON_BUSMSTRARB	(SYSCON_BASE + 0x0054)
+#define SYSCON_BOOTMODECLR	(SYSCON_BASE + 0x0058)
+#define SYSCON_DEVICECFG	(SYSCON_BASE + 0x0080)
+#define SYSCON_VIDCLKDIV	(SYSCON_BASE + 0x0084)
+#define SYSCON_MIRCLKDIV	(SYSCON_BASE + 0x0088)
+#define SYSCON_I2SCLKDIV	(SYSCON_BASE + 0x008c)
+#define SYSCON_KEYTCHCLKDIV	(SYSCON_BASE + 0x0090)
+#define SYSCON_CHIPID		(SYSCON_BASE + 0x0094)
+#define SYSCON_SYSCFG		(SYSCON_BASE + 0x009c)
+#define SYSCON_SYSSWLOCK	(SYSCON_BASE + 0x00c0)
+
+#define SYSCON_PWRCNT_UART_BAUD			(1 << 29)
+
+#define SYSCON_CLKSET_PLL_X2IPD_SHIFT		0
+#define SYSCON_CLKSET_PLL_X2FBD2_SHIFT		5
+#define SYSCON_CLKSET_PLL_X1FBD1_SHIFT		11
+#define SYSCON_CLKSET_PLL_PS_SHIFT		16
+#define SYSCON_CLKSET1_PCLK_DIV_SHIFT		18
+#define SYSCON_CLKSET1_HCLK_DIV_SHIFT		20
+#define SYSCON_CLKSET1_NBYP1			(1 << 23)
+#define SYSCON_CLKSET1_FCLK_DIV_SHIFT		25
+
+#define SYSCON_CLKSET2_PLL2_EN			(1 << 18)
+#define SYSCON_CLKSET2_NBYP2			(1 << 19)
+#define SYSCON_CLKSET2_USB_DIV_SHIFT		28
+
+
+#define SYSCON_CHIPID_REV_MASK			0xF0000000
+#define SYSCON_DEVICECFG_SWRST			(1 << 31)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80930000 - 0x8093FFFF: Watchdog Timer
+ */
+#define WATCHDOG_OFFSET		0x940000
+#define WATCHDOG_BASE		(EP93XX_APB_BASE | WATCHDOG_OFFSET)
+
+#define WATCHDOG_TIMER		(WATCHDOG_BASE + 0x0000)
+#define WATCHDOG_STATUS		(WATCHDOG_BASE + 0x0004)
+
+
+/* -----------------------------------------------------------------------------
+ * 0x80950000 - 0x9000FFFF: Reserved
+ */
+
diff --git a/include/common.h b/include/common.h
index f7c93bf..eec225c 100644
--- a/include/common.h
+++ b/include/common.h
@@ -502,6 +502,12 @@ ulong	get_HCLK (void);
 ulong	get_PCLK (void);
 ulong	get_UCLK (void);
 #endif
+#ifdef CONFIG_EP93XX
+ulong	get_FCLK(void);
+ulong	get_HCLK(void);
+ulong	get_PCLK(void);
+ulong	get_UCLK(void);
+#endif
 #if defined(CONFIG_LH7A40X)
 ulong	get_PLLCLK (void);
 #endif
diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h
new file mode 100644
index 0000000..6c4576b
--- /dev/null
+++ b/include/configs/edb93xx.h
@@ -0,0 +1,235 @@
+/*
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Initial environment and monitor configuration options. */
+#define CONFIG_ETHADDR			08:00:3E:26:0A:5B
+#define CONFIG_NETMASK			255.255.255.0
+#define CONFIG_IPADDR			192.168.99.225
+#define CONFIG_SERVERIP			192.168.99.1
+#define CONFIG_GATEWAYIP		192.168.99.1
+
+#define CONFIG_BOOTDELAY		5
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_BOOTARGS			"root=/dev/nfs console=ttyAM0,115200 ip=dhcp"
+#define CONFIG_BOOTFILE			"edb93xx.img"
+
+#define CONFIG_SYS_HUSH_PARSER		1
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_EP9301
+#elif defined(CONFIG_EDB9302) || defined(CONFIG_EDB9302A)
+#define CONFIG_EP9302
+#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A)
+#define CONFIG_EP9307
+#elif defined(CONFIG_EDB9312)
+#define CONFIG_EP9312
+#elif defined(CONFIG_EDB9315) || defined(CONFIG_EDB9315A)
+#define CONFIG_EP9315
+#endif
+
+/* High-level configuration options */
+#define CONFIG_ARM920T		1		/* This is an ARM920T core...  */
+#define CONFIG_EP93XX 		1		/* in a Cirrus Logic 93xx SoC  */
+
+#define CONFIG_SYS_CLK_FREQ	14745600	/* EP93xx has a 14.7456 clock  */
+#define CONFIG_SYS_HZ		2048		/* Timer 3 set for 2KHz        */
+#define CONFIG_SYS_CLKS_IN_HZ			/* Everything in Hz            */
+#undef  CONFIG_USE_IRQ				/* Don't need IRQ/FIQ          */
+
+/* Monitor configuration */
+#include <config_cmd_default.h>
+#if 0
+#undef CONFIG_CMD_BDI
+#endif
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#undef CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+
+#if !defined USE_920T_MMU
+#undef CONFIG_CMD_CACHE
+#endif
+
+#ifdef CONFIG_EDB9301
+#define CONFIG_SYS_PROMPT		"EDB9301> "
+#elif (defined CONFIG_EDB9302)
+#define CONFIG_SYS_PROMPT		"EDB9302> "
+#elif (defined CONFIG_EDB9302A)
+#define CONFIG_SYS_PROMPT		"EDB9302a> "
+#elif (defined CONFIG_EDB9307)
+#define CONFIG_SYS_PROMPT		"EDB9307> "
+#elif (defined CONFIG_EDB9307A)
+#define CONFIG_SYS_PROMPT		"EDB9307a> "
+#elif (defined CONFIG_EDB9312)
+#define CONFIG_SYS_PROMPT		"EDB9312> "
+#elif (defined CONFIG_EDB9315)
+#define CONFIG_SYS_PROMPT		"EDB9315> "
+#elif (defined CONFIG_EDB9315A)
+#define CONFIG_SYS_PROMPT		"EDB9315a> "
+#endif
+
+#define CONFIG_SYS_LONGHELP				/* Enable "long" help in mon	*/
+#define CONFIG_SYS_CBSIZE		1024		/* Console I/O buffer size	*/
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print buffer size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot argument buffer size	*/
+#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
+
+/* Serial port hardware configuration */
+#define CONFIG_PL010_SERIAL
+#define CONFIG_CONS_INDEX		0
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_SERIAL0		0x808C0000
+#define CONFIG_SYS_SERIAL1		0x808D0000
+#define CONFIG_PL01x_PORTS	{(void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1}
+
+/* Network hardware configuration */
+#define CONFIG_DRIVER_EP93XX_MAC
+#define CONFIG_MII_SUPPRESS_PREAMBLE
+#define CONFIG_MII
+#define CONFIG_PHY_ADDR		1
+#undef  CONFIG_NETCONSOLE
+
+
+/* SDRAM configuration */
+#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302)
+#define CONFIG_NR_DRAM_BANKS	4		/* EDB9301/2 has 1 bank of SDRAM  */
+#define PHYS_SDRAM_1		0x00000000	/* consisting of 1x Samsung       */
+#define PHYS_SDRAM_SIZE_1	0x00800000	/* K4S561632E-TC75 256 Mbit       */
+#define PHYS_SDRAM_2		0x01000000	/* SDRAM on a 16-bit data bus,    */
+#define PHYS_SDRAM_SIZE_2	0x00800000	/* for a total of 32MB of SDRAM.  */
+#define PHYS_SDRAM_3		0x04000000	/* We set the SROMLL bit on the   */
+#define PHYS_SDRAM_SIZE_3	0x00800000	/* processor, resulting in this   */
+#define PHYS_SDRAM_4		0x05000000	/* non-contiguous memory map.	  */
+#define PHYS_SDRAM_SIZE_4	0x00800000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x00800000
+
+#elif defined(CONFIG_EDB9302A)
+#define CONFIG_NR_DRAM_BANKS	4		/* EDB9302a has 4 banks of SDRAM  */
+#define PHYS_SDRAM_1		0xc0000000	/* consisting of 1x Samsung       */
+#define PHYS_SDRAM_SIZE_1	0x00800000	/* K4S561632E-TC75 256 Mbit       */
+#define PHYS_SDRAM_2		0xc1000000	/* SDRAM on a 16-bit data bus,    */
+#define PHYS_SDRAM_SIZE_2	0x00800000	/* for a total of 32MB of SDRAM.  */
+#define PHYS_SDRAM_3		0xc4000000	/* We set the SROMLL bit on the   */
+#define PHYS_SDRAM_SIZE_3	0x00800000	/* processor, resulting in this   */
+#define PHYS_SDRAM_4		0xc5000000	/* non-contiguous memory map.	  */
+#define PHYS_SDRAM_SIZE_4	0x00800000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START	0xc0000000
+#define CONFIG_SYS_MEMTEST_END		0xc0800000
+
+#elif defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || defined(CONFIG_EDB9315)
+#define CONFIG_NR_DRAM_BANKS		2		/* The EDB9307, EDB9312, and EDB9315 have    */
+#define PHYS_SDRAM_1			0x00000000	/* 2 banks of SDRAM consisting of 2x Samsung */
+#define PHYS_SDRAM_SIZE_1		0x02000000	/* K4S561632E-TC75 256 Mbit on a 32-bit data */
+#define PHYS_SDRAM_2			0x04000000	/* bus, for a total of 64 MB of SDRAM.       */
+#define PHYS_SDRAM_SIZE_2		0x02000000
+#define CONFIG_EDB93XX_SDCS3
+#define CONFIG_SYS_MEMTEST_START	0x00000000
+#define CONFIG_SYS_MEMTEST_END		0x02000000
+
+#elif defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A)
+#define CONFIG_NR_DRAM_BANKS		2		/* The EDB9307A and EDB9315A have */
+#define PHYS_SDRAM_1			0xc0000000	/* 2 banks of SDRAM consisting of 2x Samsung */
+#define PHYS_SDRAM_SIZE_1		0x02000000	/* K4S561632E-TC75 256 Mbit on a 32-bit data */
+#define PHYS_SDRAM_2			0xc4000000	/* bus, for a total of 64 MB of SDRAM.       */
+#define PHYS_SDRAM_SIZE_2		0x02000000
+#define CONFIG_EDB93XX_SDCS0
+#define CONFIG_SYS_MEMTEST_START	0xc0000000
+#define CONFIG_SYS_MEMTEST_END		0xc2000000
+#endif
+
+#if defined(CONFIG_EDB93XX_SDCS3)
+#define CONFIG_SYS_LOAD_ADDR		0x01000000	/* Default load address		*/
+#elif defined(CONFIG_EDB93XX_SDCS0)
+#define CONFIG_SYS_LOAD_ADDR		0xc1000000	/* Default load address		*/
+#endif
+
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)		/* Must match kernel config */
+
+/* Run-time memory allocatons  */
+#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_STACKSIZE		(128 * 1024)
+
+#if defined(CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ	(4 * 1024)
+#define CONFIG_STACKSIZE_FIQ	(4 * 1024)
+#endif
+
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/* -----------------------------------------------------------------------------
+ * FLASH and environment organization
+ *
+ * The EDB9301 and EDB9302(a) have 1 bank of flash memory at 0x60000000
+ * consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit data bus,
+ * for a total of 16 MB of CFI-compatible flash.
+ *
+ * The EDB9307(a), EDB9312, and EDB9315(a) have 1 bank of flash memory at
+ * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit
+ * data bus, for a total of 32 MB of CFI-compatible flash.
+ *
+ *                            EDB9301/02(a)          EDB9307(a)/12/15(a)
+ * 0x00000000 - 0x0003FFFF    u-boot                 u-boot
+ * 0x00040000 - 0x0005FFFF    environment #1         environment #1
+ * 0x00060000 - 0x0007FFFF    unused                 environment #1 (continued)
+ * 0x00080000 - 0x0009FFFF    environment #2         environment #2
+ * 0x000A0000 - 0x000BFFFF    unused                 environment #2 (continued)
+ * 0x000C0000 - 0x000FFFFF    unused                 unused
+ * 0x00100000 - 0x002FFFFF    kernel image #1        kernel image #1
+ * 0x00300000 - 0x004FFFFF    kernel image #2        kernel image #2
+ * 0x00500000 - 0x00FFFFFF    JFFS2                  JFFS2
+ * 0x01000000 - 0x01FFFFFF    not present            JFFS2 (continued)
+ */
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	128
+
+#define PHYS_FLASH_1		0x60000000
+#define CONFIG_SYS_FLASH_BASE	(PHYS_FLASH_1)
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+
+#define CONFIG_ENV_OVERWRITE			/* Vendor params unprotected	*/
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		0x60040000
+#if (defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+     defined(CONFIG_EDB9302A))
+#define CONFIG_ENV_SECT_SIZE	0x00020000
+#elif (defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+       defined(CONFIG_EDB9312) || defined(CONFIG_EDB9315) ||\
+       defined(CONFIG_EDB9315A))
+#define CONFIG_ENV_SECT_SIZE	0x00040000
+#endif
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+
+#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_SYS_JFFS2_FIRST_BANK	0
+#if (defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||\
+     defined(CONFIG_EDB9302A))
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	28
+#elif (defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||\
+       defined(CONFIG_EDB9312) || defined(CONFIG_EDB9315) ||\
+       defined(CONFIG_EDB9315A))
+#define CONFIG_SYS_JFFS2_FIRST_SECTOR	14
+#endif
+
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#endif /* !defined (__CONFIG_H) */

-- 
Matthias Kaehlcke
Embedded Linux Developer
Barcelona

     La guerra es un acto abominable en el que se matan personas que no
      se conocen, dirigidas por personas que se conocen y no se matan
                                                                 .''`.
    using free software / Debian GNU/Linux | http://debian.org  : :'  :
                                                                `. `'`
gpg --keyserver pgp.mit.edu --recv-keys 47D8E5D4                  `-


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