[U-Boot] [PATCH 5/5] p2020ds: use common code to initialize serdes ports
Li Yang
leoli at freescale.com
Thu Dec 10 08:41:25 CET 2009
Setting up LAWs, PCIE, SRIO, SGMII intelligently
based on the power-on serdes configuration.
Signed-off-by: Li Yang <leoli at freescale.com>
---
board/freescale/p2020ds/law.c | 6 --
board/freescale/p2020ds/p2020ds.c | 126 ++-----------------------------------
include/configs/P2020DS.h | 21 ++++++
3 files changed, 27 insertions(+), 126 deletions(-)
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
index 28ed2ed..c90c9ae 100644
--- a/board/freescale/p2020ds/law.c
+++ b/board/freescale/p2020ds/law.c
@@ -29,12 +29,6 @@
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
- SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
- SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
- SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3),
- SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
};
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index e38c014..64db0c1 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -27,7 +27,6 @@
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
@@ -37,6 +36,7 @@
#include <asm/fsl_law.h>
#include <asm/mp.h>
#include <netdev.h>
+#include <asm/fsl_serdes.h>
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
@@ -180,120 +180,10 @@ phys_size_t fixed_sdram(void)
#endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
#ifdef CONFIG_PCI
void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- struct fsl_pci_info pci_info[3];
- u32 devdisr, pordevsr, io_sel, host_agent;
- int first_free_busno = 0;
- int num = 0;
-
- int pcie_ep, pcie_configured;
-
- devdisr = in_be32(&gur->devdisr);
- pordevsr = in_be32(&gur->pordevsr);
- io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
-
- debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
-
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
- printf(" eTSEC2 is in sgmii mode.\n");
- if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf(" eTSEC3 is in sgmii mode.\n");
-
- puts("\n");
-#ifdef CONFIG_PCIE2
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent);
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
- SET_STD_PCIE_INFO(pci_info[num], 2);
- printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
-
- /*
- * The workaround doesn't work on p2020 because the location
- * we try and read isn't valid on p2020, fix this later
- */
-#if 0
- /*
- * Activate ULI1575 legacy chip by performing a fake
- * memory access. Needed to make ULI RTC work.
- * Device 1d has the first on-board memory BAR.
- */
-
- pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
- PCI_BASE_ADDRESS_1, &temp32);
- if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
- void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
- temp32, 4, 0);
- debug(" uli1575 read to %p\n", p);
- in_be32(p);
- }
-#endif
- } else {
- printf(" PCIE2: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE3
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
- SET_STD_PCIE_INFO(pci_info[num], 3);
- printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
- } else {
- printf(" PCIE3: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
- pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
- pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
- SET_STD_PCIE_INFO(pci_info[num], 1);
- printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
- pcie_ep ? "End Point" : "Root Complex",
- pci_info[num].regs);
- first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
- } else {
- printf(" PCIE1: disabled\n");
- }
- puts("\n");
-#else
- setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
-#endif
+ mpc85xx_serdes_board_init();
}
#endif
@@ -523,6 +413,8 @@ int board_eth_init(bd_t *bis)
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 devdisr = in_be32(&gur->devdisr);
phys_addr_t base;
phys_size_t size;
@@ -533,14 +425,8 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_PCIE3
- ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
-#endif
-#ifdef CONFIG_PCIE2
- ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
-#endif
-#ifdef CONFIG_PCIE1
- ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#ifdef CONFIG_FSL_SERDES
+ ft_mpc85xx_serdes_board_setup(blob);
#endif
#ifdef CONFIG_FSL_SGMII_RISER
fsl_sgmii_riser_fdt_fixup(blob);
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
index b48c199..406afc7 100644
--- a/include/configs/P2020DS.h
+++ b/include/configs/P2020DS.h
@@ -39,6 +39,7 @@
#define CONFIG_P2020DS 1
#define CONFIG_MP 1 /* support multiple processors */
+#define CONFIG_FSL_SERDES 1 /* Use common serdes init code */
#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
@@ -519,6 +520,26 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
+#define CONFIG_SRIO
+
+/* SRIO1 uses the same window as PCIE2 mem window */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
+
+/* SRIO2 uses the same window as PCIE1 mem window */
+#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */
+
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
--
1.6.4
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