[U-Boot] [PATCH 4/4] OMAP3, AM35x: Update the checks for CPU revision

[Sanjeev Premi]

The usage of get_cpu_rev() to check for cpu revision
is no longer appropriate - after updates in previous
patches.

This patch ensures correct usage.

Signed-off-by: Sanjeev Premi <premi at ti.com>
---
 cpu/arm_cortexa8/omap3/cache.S |   30 ++++++++++++++++++++++++++++--
 cpu/arm_cortexa8/omap3/clock.c |    3 ++-
 2 files changed, 30 insertions(+), 3 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/cache.S b/cpu/arm_cortexa8/omap3/cache.S
index 0f63815..8e985d8 100644
--- a/cpu/arm_cortexa8/omap3/cache.S
+++ b/cpu/arm_cortexa8/omap3/cache.S
@@ -131,10 +131,23 @@ finished_inval:
 
 l2_cache_enable:
 	push	{r0, r1, r2, lr}
-	@ ES2 onwards we can disable/enable L2 ourselves
+	@ We can disable/enable L2 ourselves for these devices
+	@ - OMAP3430/OMAP35xx (ES2 onwards)
+	@ - AM35xx
+	mov	r0, #CPU_AM35XX
+	bl	is_cpu_family
+	cmp	r0, #1
+	beq	l2_cache_enable_LATER_THAN_ES2	@ family is AM35xx
+
+	mov	r0, #CPU_OMAP34XX
+	bl	is_cpu_family
+	cmp	r0, #1
+	bne	l2_cache_enable_END		@ Family isn't OMAP34xx/35xx
+
 	bl	get_cpu_rev
 	cmp	r0, #CPU_3XX_ES20
 	blt	l2_cache_disable_EARLIER_THAN_ES2
+l2_cache_enable_LATER_THAN_ES2:
 	mrc	15, 0, r3, cr1, cr0, 1
 	orr	r3, r3, #2
 	mcr	15, 0, r3, cr1, cr0, 1
@@ -162,10 +175,23 @@ l2_cache_enable_END:
 
 l2_cache_disable:
 	push	{r0, r1, r2, lr}
-	@ ES2 onwards we can disable/enable L2 ourselves
+	@ We can disable/enable L2 ourselves for these devices
+	@ - OMAP3430/OMAP35xx (ES2 onwards)
+	@ - AM35xx
+	mov	r0, #CPU_AM35XX
+	bl	is_cpu_family
+	cmp	r0, #1
+	beq	l2_cache_disable_LATER_THAN_ES2	@ family is AM35xx
+
+	mov	r0, #CPU_OMAP34XX
+	bl	is_cpu_family
+	cmp	r0, #1
+	bne	l2_cache_enable_END		@ Family isn't OMAP34xx/35xx
+
 	bl	get_cpu_rev
 	cmp	r0, #CPU_3XX_ES20
 	blt	l2_cache_disable_EARLIER_THAN_ES2
+l2_cache_disable_LATER_THAN_ES2:
 	mrc	15, 0, r3, cr1, cr0, 1
 	bic	r3, r3, #2
 	mcr	15, 0, r3, cr1, cr0, 1
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c
index 174c453..0a1e603 100644
--- a/cpu/arm_cortexa8/omap3/clock.c
+++ b/cpu/arm_cortexa8/omap3/clock.c
@@ -170,7 +170,8 @@ void prcm_init(void)
 	 * and sil_index will get the values for that SysClk for the
 	 * appropriate silicon rev.
 	 */
-	if (get_cpu_rev())
+	if ((is_cpu_family(CPU_OMAP34XX) && (get_cpu_rev() >= CPU_3XX_ES20)) ||
+		(is_cpu_family(CPU_AM35XX)))
 		sil_index = 1;
 
 	/* Unlock MPU DPLL (slows things down, and needed later) */
-- 
1.6.2.2