[U-Boot] [PATCH 1/4] fsl-ddr: Fix power-down timing settings

[Kumar Gala]

On Dec 16, 2009, at 10:24 AM, Kumar Gala wrote:

> From: Dave Liu <daveliu at freescale.com>
> 
> 1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
>   It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
> 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
>   It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
>   We are setting the mode register MR0[A12]='1'
> 
> Signed-off-by: Dave Liu <daveliu at freescale.com>
> ---
> cpu/mpc8xxx/ddr/ctrl_regs.c |    7 ++++---
> 1 files changed, 4 insertions(+), 3 deletions(-)

applied to 85xx

- k