[U-Boot] [Patch 3/8] add at91 SoC access with c structures
Jens Scharsig
js_at_ng at scharsoft.de
Sat Dec 19 21:08:48 CET 2009
* add new hardware header files for at91 emac, matrix, mc, pdc, st and tc controller
* add at91rm9200 definitions, need for join at91rm9200 into at91 arch
Signed-off-by: Jens Scharsig <js_at_ng at scharsoft.de>
---
include/asm-arm/arch-at91/at91_emac.h | 145 +++++++++++++++++++++++++++++++
include/asm-arm/arch-at91/at91_matrix.h | 125 ++++++++++++++++++++++++++
include/asm-arm/arch-at91/at91_mc.h | 89 +++++++++++++++++++
include/asm-arm/arch-at91/at91_pdc.h | 41 +++++++++
include/asm-arm/arch-at91/at91_st.h | 48 ++++++++++
include/asm-arm/arch-at91/at91_tc.h | 79 +++++++++++++++++
include/asm-arm/arch-at91/at91rm9200.h | 135 ++++++++++++++++++++++++++++
7 files changed, 662 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-at91/at91_emac.h
create mode 100644 include/asm-arm/arch-at91/at91_matrix.h
create mode 100644 include/asm-arm/arch-at91/at91_mc.h
create mode 100644 include/asm-arm/arch-at91/at91_pdc.h
create mode 100644 include/asm-arm/arch-at91/at91_st.h
create mode 100644 include/asm-arm/arch-at91/at91_tc.h
create mode 100644 include/asm-arm/arch-at91/at91rm9200.h
diff --git a/include/asm-arm/arch-at91/at91_emac.h b/include/asm-arm/arch-at91/at91_emac.h
new file mode 100644
index 0000000..a367ed8
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_emac.h
@@ -0,0 +1,145 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * based on AT91RM9200 datasheet revision I (36. Ethernet MAC (EMAC))
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_H
+#define AT91_H
+
+typedef struct at91_emac {
+ u32 ctl;
+ u32 cfg;
+ u32 sr;
+ u32 tar;
+ u32 tcr;
+ u32 tsr;
+ u32 rbqp;
+ u32 reserved0;
+ u32 rsr;
+ u32 isr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 man;
+ u32 reserved1[2];
+ u32 fra;
+ u32 scol;
+ u32 mocl;
+ u32 ok;
+ u32 seqe;
+ u32 ale;
+ u32 dte;
+ u32 lcol;
+ u32 ecol;
+ u32 cse;
+ u32 tue;
+ u32 cde;
+ u32 elr;
+ u32 rjb;
+ u32 usf;
+ u32 sqee;
+ u32 drfc;
+ u32 reserved2[3];
+ u32 hsh;
+ u32 hsl;
+ u32 sh1l;
+ u32 sa1h;
+ u32 sa2l;
+ u32 sa2h;
+ u32 sa3l;
+ u32 sa3h;
+ u32 sa4l;
+ u32 sa4h;
+} at91_emac_t;
+
+#define AT91_EMAC_CTL_LB 0x0001
+#define AT91_EMAC_CTL_LBL 0x0002
+#define AT91_EMAC_CTL_RE 0x0004
+#define AT91_EMAC_CTL_TE 0x0008
+#define AT91_EMAC_CTL_MPE 0x0010
+#define AT91_EMAC_CTL_CSR 0x0020
+#define AT91_EMAC_CTL_ISR 0x0040
+#define AT91_EMAC_CTL_WES 0x0080
+#define AT91_EMAC_CTL_BP 0x1000
+
+#define AT91_EMAC_CFG_SPD 0x0001
+#define AT91_EMAC_CFG_FD 0x0002
+#define AT91_EMAC_CFG_BR 0x0004
+#define AT91_EMAC_CFG_CAF 0x0010
+#define AT91_EMAC_CFG_NBC 0x0020
+#define AT91_EMAC_CFG_MTI 0x0040
+#define AT91_EMAC_CFG_UNI 0x0080
+#define AT91_EMAC_CFG_BIG 0x0100
+#define AT91_EMAC_CFG_EAE 0x0200
+#define AT91_EMAC_CFG_CLK_MASK 0xFFFFF3FF
+#define AT91_EMAC_CFG_MCLK_8 0x0000
+#define AT91_EMAC_CFG_MCLK_16 0x0400
+#define AT91_EMAC_CFG_MCLK_32 0x0800
+#define AT91_EMAC_CFG_MCLK_64 0x0C00
+#define AT91_EMAC_CFG_RTY 0x1000
+#define AT91_EMAC_CFG_RMII 0x2000
+
+#define AT91_EMAC_SR_LINK 0x0001
+#define AT91_EMAC_SR_MDIO 0x0002
+#define AT91_EMAC_SR_IDLE 0x0004
+
+#define AT91_EMAC_TCR_LEN(x) (x & 0x7FF)
+#define AT91_EMAC_TCR_NCRC 0x8000
+
+#define AT91_EMAC_TSR_OVR 0x0001
+#define AT91_EMAC_TSR_COL 0x0002
+#define AT91_EMAC_TSR_RLE 0x0004
+#define AT91_EMAC_TSR_TXIDLE 0x0008
+#define AT91_EMAC_TSR_BNQ 0x0010
+#define AT91_EMAC_TSR_COMP 0x0020
+#define AT91_EMAC_TSR_UND 0x0040
+
+#define AT91_EMAC_RSR_BNA 0x0001
+#define AT91_EMAC_RSR_REC 0x0002
+#define AT91_EMAC_RSR_OVR 0x0004
+
+/* ISR, IER, IDR, IMR use the same bits */
+#define AT91_EMAC_IxR_DONE 0x0001
+#define AT91_EMAC_IxR_RCOM 0x0002
+#define AT91_EMAC_IxR_RBNA 0x0004
+#define AT91_EMAC_IxR_TOVR 0x0008
+#define AT91_EMAC_IxR_TUND 0x0010
+#define AT91_EMAC_IxR_RTRY 0x0020
+#define AT91_EMAC_IxR_TBRE 0x0040
+#define AT91_EMAC_IxR_TCOM 0x0080
+#define AT91_EMAC_IxR_TIDLE 0x0100
+#define AT91_EMAC_IxR_LINK 0x0200
+#define AT91_EMAC_IxR_ROVR 0x0400
+#define AT91_EMAC_IxR_HRESP 0x0800
+
+#define AT91_EMAC_MAN_DATA_MASK 0xFFFF
+#define AT91_EMAC_MAN_CODE_802_3 0x00020000
+#define AT91_EMAC_MAN_REGA(reg) ((reg & 0x1F) << 18)
+#define AT91_EMAC_MAN_PHYA(phy) ((phy & 0x1F) << 23)
+#define AT91_EMAC_MAN_RW_R 0x20000000
+#define AT91_EMAC_MAN_RW_W 0x10000000
+#define AT91_EMAC_MAN_HIGH 0x40000000
+#define AT91_EMAC_MAN_LOW 0x80000000
+
+#endif
\ No newline at end of file
diff --git a/include/asm-arm/arch-at91/at91_matrix.h b/include/asm-arm/arch-at91/at91_matrix.h
new file mode 100644
index 0000000..8cbd2a2
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_matrix.h
@@ -0,0 +1,125 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_MATRIX_H
+#define AT91_MATRIX_H
+
+#ifdef __ASSEMBLY__
+
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x11C)
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x30)
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x120)
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_ASM_MATRIX_CSA0 (AT91_MATRIX_BASE + 0x128)
+#else
+#error AT91_ASM_MATRIX_CSA0 is not definied for current CPU
+#endif
+
+#define AT91_ASM_MATRIX_MCFG AT91_MATRIX_BASE
+
+#else
+#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#define AT91_MATRIX_MASTERS 6
+#define AT91_MATRIX_SLAVES 5
+#elif defined(CONFIG_AT91SAM9261)
+#define AT91_MATRIX_MASTERS 1
+#define AT91_MATRIX_SLAVES 5
+#elif defined(CONFIG_AT91SAM9263)
+#define AT91_MATRIX_MASTERS 9
+#define AT91_MATRIX_SLAVES 7
+#elif defined(CONFIG_AT91SAM9G45)
+#define AT91_MATRIX_MASTERS 11
+#define AT91_MATRIX_SLAVES 8
+#else
+#error CPU not supported. Please update at91_matrix.h
+#endif
+
+typedef struct at91_prority {
+ u32 a;
+ u32 b;
+} at91_prority_t;
+
+
+typedef struct at91_matrix {
+ u32 mcfg[AT91_MATRIX_MASTERS];
+#if defined(CONFIG_AT91SAM9261)
+ u32 scfg[AT91_MATRIX_SLAVES];
+ u32 res61_1[3];
+ u32 tcr;
+ u32 res61_2[2];
+ u32 csa;
+ u32 pucr;
+ u32 res61_3[114];
+#else
+#if (AT91_MATRIX_MASTERS < 16)
+ u32 reserve1[16 - AT91_MATRIX_MASTERS];
+#endif
+ u32 scfg[AT91_MATRIX_SLAVES];
+#if (AT91_MATRIX_SLAVES < 16)
+ u32 reserve2[16 - AT91_MATRIX_SLAVES];
+#endif
+ at91_prority_t pr[AT91_MATRIX_SLAVES];
+#if (AT91_MATRIX_SLAVES < 16)
+ u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
+#endif
+ u32 mrcr; /* 0x100 Master Remap Control */
+ u32 reserve4[3];
+#if defined(CONFIG_AT91SAM9G45)
+ u32 ccr[52] /* 0x110 - 0x1E0 Chip Configuration */
+ u32 womr; /* 0x1E4 Write Protect Mode */
+ u32 wpsr; /* 0x1E8 Write Protect Status */
+ u32 resg45_1[10];
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+ u32 res60_1[3];
+ u32 csa;
+ u32 res60_2[56];
+#elif defined(CONFIG_AT91SAM9263)
+ u32 res63_1;
+ u32 tcmr;
+ u32 res63_2[2];
+ u32 csa[2];
+ u32 res63_3[54];
+#else
+ u32 reserve5[60];
+#endif
+#endif
+} at91_matrix_t;
+
+#endif /* __ASSEMBLY__ */
+
+#define AT91_MATRIX_CSA_DBPUC 0x00000100
+#define AT91_MATRIX_CSA_VDDIOMSEL_1_8V 0x00000000
+#define AT91_MATRIX_CSA_VDDIOMSEL_3_3V 0x00010000
+
+#define AT91_MATRIX_CSA_EBI_CS1A 0x00000002
+#define AT91_MATRIX_CSA_EBI_CS3A 0x00000008
+#define AT91_MATRIX_CSA_EBI_CS4A 0x00000010
+#define AT91_MATRIX_CSA_EBI_CS5A 0x00000020
+
+#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008
+
+#endif
\ No newline at end of file
diff --git a/include/asm-arm/arch-at91/at91_mc.h b/include/asm-arm/arch-at91/at91_mc.h
new file mode 100644
index 0000000..3be00f5
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_mc.h
@@ -0,0 +1,89 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_MC_H
+#define AT91_MC_H
+
+typedef struct at91_ebi {
+ u32 csa; /* 0x00 Chip Select Assignment Register */
+ u32 cfgr; /* 0x04 Configuration Register */
+ u32 reserved[2];
+} at91_ebi_t;
+
+#define AT91_EBI_CSA_CS0A 0x0001
+#define AT91_EBI_CSA_CS1A 0x0002
+
+#define AT91_EBI_CSA_CS3A 0x0008
+#define AT91_EBI_CSA_CS4A 0x0010
+
+typedef struct at91_sdramc {
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+ u32 tr; /* 0x04 SDRAMC Refresh Timer Register */
+ u32 cr; /* 0x08 SDRAMC Configuration Register */
+ u32 ssr; /* 0x0C SDRAMC Self Refresh Register */
+ u32 lpr; /* 0x10 SDRAMC Low Power Register */
+ u32 ier; /* 0x14 SDRAMC Interrupt Enable Register */
+ u32 idr; /* 0x18 SDRAMC Interrupt Disable Register */
+ u32 imr; /* 0x1C SDRAMC Interrupt Mask Register */
+ u32 icr; /* 0x20 SDRAMC Interrupt Status Register */
+ u32 reserved[3];
+} at91_sdramc_t;
+
+typedef struct at91_smc {
+ u32 csr[8]; /* 0x00 SDRAMC Mode Register */
+} at91_smc_t;
+
+#define AT91_SMC_CSR_RWHOLD(x) ((x & 0x7) << 28)
+#define AT91_SMC_CSR_RWSETUP(x) ((x & 0x7) << 24)
+#define AT91_SMC_CSR_ACSS_STANDARD 0x00000000
+#define AT91_SMC_CSR_ACSS_1CYCLE 0x00010000
+#define AT91_SMC_CSR_ACSS_2CYCLE 0x00020000
+#define AT91_SMC_CSR_ACSS_3CYCLE 0x00030000
+#define AT91_SMC_CSR_DRP 0x00008000
+#define AT91_SMC_CSR_DBW_8 0x00004000
+#define AT91_SMC_CSR_DBW_16 0x00002000
+#define AT91_SMC_CSR_BAT_8 0x00000000
+#define AT91_SMC_CSR_BAT_16 0x00001000
+#define AT91_SMC_CSR_TDF(x) ((x & 0xF) << 8)
+#define AT91_SMC_CSR_WSEN 0x00000080
+#define AT91_SMC_CSR_NWS(x) (x & 0x7F)
+
+typedef struct at91_bfc {
+ u32 mr; /* 0x00 SDRAMC Mode Register */
+} at91_bfc_t;
+
+typedef struct at91_mc {
+ u32 rcr; /* 0x00 MC Remap Control Register */
+ u32 asr; /* 0x04 MC Abort Status Register */
+ u32 aasr; /* 0x08 MC Abort Address Status Reg */
+ u32 mpr; /* 0x0C MC Master Priority Register */
+ u32 reserved1[20]; /* 0x10-0x5C */
+ at91_ebi_t ebi; /* 0x60 - 0x6C EBI */
+ at91_smc_t smc; /* 0x70 - 0x8C SMC User Interface */
+ at91_sdramc_t sdramc; /* 0x90 - 0xBC SDRAMC User Interface */
+ at91_bfc_t bfc; /* 0xC0 BFC User Interface */
+ u32 reserved2[15];
+} at91_mc_t;
+
+#endif
\ No newline at end of file
diff --git a/include/asm-arm/arch-at91/at91_pdc.h b/include/asm-arm/arch-at91/at91_pdc.h
new file mode 100644
index 0000000..dd12587
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_pdc.h
@@ -0,0 +1,41 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_PDC_H
+#define AT91_PDC_H
+
+typedef struct at91_pdc {
+ u32 rpr; /* 0x100 Receive Pointer Register */
+ u32 rcr; /* 0x104 Receive Counter Register */
+ u32 tpr; /* 0x108 Transmit Pointer Register */
+ u32 tcr; /* 0x10C Transmit Counter Register */
+ u32 pnpr; /* 0x110 Receive Next Pointer Register */
+ u32 pncr; /* 0x114 Receive Next Counter Register */
+ u32 tnpr; /* 0x118 Transmit Next Pointer Register */
+ u32 tncr; /* 0x11C Transmit Next Counter Register */
+ u32 ptcr; /* 0x120 Transfer Control Register */
+ u32 ptsr; /* 0x124 Transfer Status Register */
+} at91_pdc_t;
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91_st.h b/include/asm-arm/arch-at91/at91_st.h
new file mode 100644
index 0000000..2b8d153
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_st.h
@@ -0,0 +1,48 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_ST_H
+#define AT91_ST_H
+
+typedef struct at91_st {
+
+ u32 cr;
+ u32 pimr;
+ u32 wdmr;
+ u32 rtmr;
+ u32 sr;
+ u32 ier;
+ u32 idr;
+ u32 imr;
+ u32 rtar;
+ u32 crtr;
+} at91_st_t;
+
+#define AT91_ST_CR_WDRST 1
+
+#define AT91_ST_WDMR_WDV(x) (x & 0xFFFF)
+#define AT91_ST_WDMR_RSTEN 0x00010000
+#define AT91_ST_WDMR_EXTEN 0x00020000
+
+#endif
\ No newline at end of file
diff --git a/include/asm-arm/arch-at91/at91_tc.h b/include/asm-arm/arch-at91/at91_tc.h
new file mode 100644
index 0000000..b40cd20
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_tc.h
@@ -0,0 +1,79 @@
+/*
+ * Memory Setup stuff - taken from blob memsetup.S
+ *
+ * Copyright (C) 2009 Jens Scharsig (js_at_ng at scharsoft.de)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef AT91_TC_H
+#define AT91_TC_H
+
+typedef struct at91_tcc {
+ u32 ccr; /* 0x00 Channel Control Register */
+ u32 cmr; /* 0x04 Channel Mode Register */
+ u32 reserved1[2];
+ u32 cv; /* 0x10 Counter Value */
+ u32 ra; /* 0x14 Register A */
+ u32 rb; /* 0x18 Register B */
+ u32 rc; /* 0x1C Register C */
+ u32 sr; /* 0x20 Status Register */
+ u32 ier; /* 0x24 Interrupt Enable Register */
+ u32 idr; /* 0x28 Interrupt Disable Register */
+ u32 imr; /* 0x2C Interrupt Mask Register */
+ u32 reserved3[4];
+} at91_tcc_t;
+
+#define AT91_TC_CCR_CLKEN 0x00000001
+#define AT91_TC_CCR_CLKDIS 0x00000002
+#define AT91_TC_CCR_SWTRG 0x00000004
+
+#define AT91_TC_CMR_CPCTRG 0x00004000
+
+#define AT91_TC_CMR_TCCLKS_CLOCK1 0x00000000
+#define AT91_TC_CMR_TCCLKS_CLOCK2 0x00000001
+#define AT91_TC_CMR_TCCLKS_CLOCK3 0x00000002
+#define AT91_TC_CMR_TCCLKS_CLOCK4 0x00000003
+#define AT91_TC_CMR_TCCLKS_CLOCK5 0x00000004
+#define AT91_TC_CMR_TCCLKS_XC0 0x00000005
+#define AT91_TC_CMR_TCCLKS_XC1 0x00000006
+#define AT91_TC_CMR_TCCLKS_XC2 0x00000007
+
+typedef struct at91_tc {
+ at91_tcc_t tc[3]; /* 0x00 TC Channel 0-2 */
+ u32 bcr; /* 0xC0 TC Block Control Register */
+ u32 bmr; /* 0xC4 TC Block Mode Register */
+} at91_tc_t;
+
+#define AT91_TC_BMR_TC0XC0S_TCLK0 0x00000000
+#define AT91_TC_BMR_TC0XC0S_NONE 0x00000001
+#define AT91_TC_BMR_TC0XC0S_TIOA1 0x00000002
+#define AT91_TC_BMR_TC0XC0S_TIOA2 0x00000003
+
+#define AT91_TC_BMR_TC1XC1S_TCLK1 0x00000000
+#define AT91_TC_BMR_TC1XC1S_NONE 0x00000004
+#define AT91_TC_BMR_TC1XC1S_TIOA0 0x00000008
+#define AT91_TC_BMR_TC1XC1S_TIOA2 0x0000000C
+
+#define AT91_TC_BMR_TC2XC2S_TCLK2 0x00000000
+#define AT91_TC_BMR_TC2XC2S_NONE 0x00000010
+#define AT91_TC_BMR_TC2XC2S_TIOA0 0x00000020
+#define AT91_TC_BMR_TC2XC2S_TIOA1 0x00000030
+
+#endif
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
new file mode 100644
index 0000000..da6843b
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -0,0 +1,135 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your optionany later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AT91RM9200_H__
+#define __AT91RM9200_H__
+
+/* Periperial Identifiers */
+
+#define AT91_ID_SYS 1 /* System Peripheral */
+#define AT91_ID_PIOA 2 /* PIO port A */
+#define AT91_ID_PIOB 3 /* PIO port B */
+#define AT91_ID_PIOC 4 /* PIO port C */
+#define AT91_ID_PIOD 5 /* PIO port D BGA only */
+#define AT91_ID_USART0 6 /* USART 0 */
+#define AT91_ID_USART1 7 /* USART 1 */
+#define AT91_ID_USART2 8 /* USART 2 */
+#define AT91_ID_USART3 9 /* USART 3 */
+#define AT91_ID_MCI 10 /* Multimedia Card Interface */
+#define AT91_ID_UDP 11 /* USB Device Port */
+#define AT91_ID_TWI 12 /* Two Wire Interface */
+#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
+#define AT91_ID_SSC0 14 /* Synch. Serial Controller 0 */
+#define AT91_ID_SSC1 15 /* Synch. Serial Controller 1 */
+#define AT91_ID_SSC2 16 /* Synch. Serial Controller 2 */
+#define AT91_ID_TC0 17 /* Timer Counter 0 */
+#define AT91_ID_TC1 18 /* Timer Counter 1 */
+#define AT91_ID_TC2 19 /* Timer Counter 2 */
+#define AT91_ID_TC3 20 /* Timer Counter 3 */
+#define AT91_ID_TC4 21 /* Timer Counter 4 */
+#define AT91_ID_TC5 22 /* Timer Counter 5 */
+#define AT91_ID_UHP 23 /* OHCI USB Host Port */
+#define AT91_ID_EMAC 24 /* Ethernet MAC */
+#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller */
+#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller */
+
+#define AT91_USB_HOST_BASE 0x00300000
+
+#define AT91_TC_BASE 0xFFFA0000
+#define AT91_UDP_BASE 0xFFFB0000
+#define AT91_MCI_BASE 0xFFFB4000
+#define AT91_TWI_BASE 0xFFFB8000
+#define AT91_EMAC_BASE 0xFFFBC000
+#define AT91_USART_BASE 0xFFFC0000 /* 4x 0x4000 Offset */
+#define AT91_SCC_BASE 0xFFFD0000 /* 4x 0x4000 Offset */
+#define AT91_SPI_BASE 0xFFFE0000
+
+#define AT91_AIC_BASE 0xFFFFF000
+#define AT91_DBGU_BASE 0xFFFFF200
+#define AT91_PIO_BASE 0xFFFFF400 /* 4x 0x200 Offset */
+#define AT91_PMC_BASE 0xFFFFFC00
+#define AT91_ST_BASE 0xFFFFFD00
+#define AT91_ST_BASE 0xFFFFFD00
+#define AT91_RTC_BASE 0xFFFFFE00
+#define AT91_MC_BASE 0xFFFFFF00
+
+
+/* AT91RM9200 Periperial Multiplexing A */
+/* Port A */
+#define AT91_PMX_AA_EREFCK 0x00000080
+#define AT91_PMX_AA_ETXCK 0x00000080
+#define AT91_PMX_AA_ETXEN 0x00000100
+#define AT91_PMX_AA_ETX0 0x00000200
+#define AT91_PMX_AA_ETX1 0x00000400
+#define AT91_PMX_AA_ECRS 0x00000800
+#define AT91_PMX_AA_ECRSDV 0x00000800
+#define AT91_PMX_AA_ERX0 0x00001000
+#define AT91_PMX_AA_ERX1 0x00002000
+#define AT91_PMX_AA_ERXER 0x00004000
+#define AT91_PMX_AA_EMDC 0x00008000
+#define AT91_PMX_AA_EMDIO 0x00010000
+
+#define AT91_PMX_AA_TXD2 0x00810000
+
+#define AT91_PMX_AA_TWD 0x02000000
+#define AT91_PMX_AA_TWCK 0x04000000
+
+/* Port B */
+#define AT91_PMX_BA_ERXCK 0x00080000
+#define AT91_PMX_BA_ECOL 0x00040000
+#define AT91_PMX_BA_ERXDV 0x00020000
+#define AT91_PMX_BA_ERX3 0x00010000
+#define AT91_PMX_BA_ERX2 0x00008000
+#define AT91_PMX_BA_ETXER 0x00004000
+#define AT91_PMX_BA_ETX3 0x00002000
+#define AT91_PMX_BA_ETX2 0x00001000
+
+/* Port B */
+
+#define AT91_PMX_CA_BFCK 0x00000001
+#define AT91_PMX_CA_BFRDY 0x00000002
+#define AT91_PMX_CA_SMOE 0x00000002
+#define AT91_PMX_CA_BFAVD 0x00000004
+#define AT91_PMX_CA_BFBAA 0x00000008
+#define AT91_PMX_CA_SMWE 0x00000008
+#define AT91_PMX_CA_BFOE 0x00000010
+#define AT91_PMX_CA_BFWE 0x00000020
+#define AT91_PMX_CA_NWAIT 0x00000040
+#define AT91_PMX_CA_A23 0x00000080
+#define AT91_PMX_CA_A24 0x00000100
+#define AT91_PMX_CA_A25 0x00000200
+#define AT91_PMX_CA_CFRNW 0x00000200
+#define AT91_PMX_CA_NCS4 0x00000400
+#define AT91_PMX_CA_CFCS 0x00000400
+#define AT91_PMX_CA_NCS5 0x00000800
+#define AT91_PMX_CA_CFCE1 0x00001000
+#define AT91_PMX_CA_NCS6 0x00001000
+#define AT91_PMX_CA_CFCE2 0x00002000
+#define AT91_PMX_CA_NCS7 0x00002000
+#define AT91_PMX_CA_D16_31 0xFFFF0000
+
+#define AT91_CPU_NAME "AT91RM9200"
+
+#endif
--
1.6.0.2
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