[U-Boot] [PATCH V3 1/3] Initial support for Marvell Orion5x SoC
Prafulla Wadaskar
prafulla at marvell.com
Wed Dec 23 10:27:33 CET 2009
> -----Original Message-----
> From: u-boot-bounces at lists.denx.de
> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Albert Aribaud
> Sent: Wednesday, December 02, 2009 1:57 AM
> To: u-boot at lists.denx.de
> Subject: [U-Boot] [PATCH V3 1/3] Initial support for Marvell
> Orion5x SoC
>
> This patch adds support for the Marvell Orion5x SoC.
> It has no use alone, and must be followed by a patch
> to add Orion5x support for serial, then support for
> the ED Mini V2, an Orion5x-based product from LaCie.
>
> Signed-off-by: Albert Aribaud <albert.aribaud at free.fr>
> ---
> V1 of the patch was monolithic
>
> V2 contains a number of fixes as a result of the V1 review,
> and notably:
> - is split in three patches : orion, serial, edmini;
> - has been checkpatch'ed, with only 6 errors, in patch 1/3,
> all 6 errors being false positives.
>
> V3 contains yet several fixes as a result of the V2 review,
> and notably:
> - removes most of the GPIO and MPP programming support;
> - adds low level init and removes CONFIG_SKIP_LOW_LEVEL_INIT.
>
> cpu/arm926ejs/orion5x/Makefile | 51 ++++++
> cpu/arm926ejs/orion5x/cpu.c | 258
> ++++++++++++++++++++++++++++++
> cpu/arm926ejs/orion5x/dram.c | 61 +++++++
> cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++++++++
> include/asm-arm/arch-orion5x/cpu.h | 205
> ++++++++++++++++++++++++
> include/asm-arm/arch-orion5x/mv88f5182.h | 40 +++++
> include/asm-arm/arch-orion5x/orion5x.h | 65 ++++++++
> 7 files changed, 861 insertions(+), 0 deletions(-)
> create mode 100644 cpu/arm926ejs/orion5x/Makefile
> create mode 100644 cpu/arm926ejs/orion5x/cpu.c
> create mode 100644 cpu/arm926ejs/orion5x/dram.c
> create mode 100644 cpu/arm926ejs/orion5x/timer.c
> create mode 100644 include/asm-arm/arch-orion5x/cpu.h
> create mode 100644 include/asm-arm/arch-orion5x/mv88f5182.h
> create mode 100644 include/asm-arm/arch-orion5x/orion5x.h
>
...snip...
> diff --git a/cpu/arm926ejs/orion5x/cpu.c b/cpu/arm926ejs/orion5x/cpu.c
> new file mode 100644
> index 0000000..deebf24
> --- /dev/null
> +++ b/cpu/arm926ejs/orion5x/cpu.c
> @@ -0,0 +1,258 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirkwood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <netdev.h>
> +#include <asm/cache.h>
> +#include <u-boot/md5.h>
> +#include <asm/arch/orion5x.h>
> +#include <hush.h>
> +
> +#define BUFLEN 16
> +
> +void reset_cpu(unsigned long ignored)
> +{
> + struct orion5x_cpu_registers *cpureg =
> + (struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
> +
> + writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
> + &cpureg->rstoutn_mask);
> + writel(readl(&cpureg->sys_soft_rst) | 1,
> + &cpureg->sys_soft_rst);
> + while (1)
> + ;
> +}
> +
> +/*
> + * Window Size
> + * Used with the Base register to set the address window
> size and location.
> + * Must be programmed from LSB to MSB as sequence of ones followed by
> + * sequence of zeros. The number of ones specifies the size
> of the window in
> + * 64 KByte granularity (e.g., a value of 0x00FF specifies
> 256 = 16 MByte).
> + * NOTE: A value of 0x0 specifies 64-KByte size.
> + */
Any data sheet reference for this description?
> +unsigned int orion5x_winctrl_calcsize(unsigned int sizeval)
> +{
> + int i;
> + unsigned int j = 0;
> + u32 val = sizeval >> 1;
> +
> + for (i = 0; val > 0x10000; i++) {
> + j |= (1 << i);
> + val = val >> 1;
> + }
> + return 0x0000ffff & j;
> +}
> +
> +/*
> + * orion5x_config_adr_windows - Configure address Windows
> + *
> + * There are 8 address windows supported by Orion5x Soc to
> addess different
> + * devices. Each window can be configured for size, BAR and
> remap addr
> + * Below configuration is standard for most of the cases
> + *
> + * If remap function not used, remap_lo must be set as base
> + *
> + * Reference Documentation:
> + * Mbus-L to Mbus Bridge Registers Configuration.
> + * (Sec 25.1 and 25.3 of Datasheet)
> + */
> +int orion5x_config_adr_windows(void)
> +{
> + struct orion5x_win_registers *winregs =
> + (struct orion5x_win_registers *)ORION5X_CPU_WIN_BASE;
> +
> + /* Window 0: PCIE MEM address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_MEM,
> + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_MEM,
> + ORION5X_WIN_ENABLE), &winregs[0].ctrl);
> + writel(ORION5X_DEFADR_PCIE_MEM, &winregs[0].base);
> + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_LO, &winregs[0].remap_lo);
> + writel(ORION5X_DEFADR_PCIE_MEM_REMAP_HI, &winregs[0].remap_hi);
> +
> + /* Window 1: PCIE IO address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCIE_IO,
> + ORION5X_TARGET_PCIE, ORION5X_ATTR_PCIE_IO,
> + ORION5X_WIN_ENABLE), &winregs[1].ctrl);
> + writel(ORION5X_DEFADR_PCIE_IO, &winregs[1].base);
> + writel(ORION5X_DEFADR_PCIE_IO_REMAP_LO, &winregs[1].remap_lo);
> + writel(ORION5X_DEFADR_PCIE_IO_REMAP_HI, &winregs[1].remap_hi);
> +
> + /* Window 2: PCI MEM address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_MEM,
> + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_MEM,
> + ORION5X_WIN_ENABLE), &winregs[2].ctrl);
> + writel(ORION5X_DEFADR_PCI_MEM, &winregs[2].base);
> +
> + /* Window 3: PCI IO address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_PCI_IO,
> + ORION5X_TARGET_PCI, ORION5X_ATTR_PCI_IO,
> + ORION5X_WIN_ENABLE), &winregs[3].ctrl);
> + writel(ORION5X_DEFADR_PCI_IO, &winregs[3].base);
> +
> + /* Window 4: DEV_CS0 address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS0,
> + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS0,
> + ORION5X_WIN_ENABLE), &winregs[4].ctrl);
> + writel(ORION5X_DEFADR_DEV_CS0, &winregs[4].base);
> +
> + /* Window 5: DEV_CS1 address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS1,
> + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS1,
> + ORION5X_WIN_ENABLE), &winregs[5].ctrl);
> + writel(ORION5X_DEFADR_DEV_CS1, &winregs[5].base);
> +
> + /* Window 6: DEV_CS2 address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_DEV_CS2,
> + ORION5X_TARGET_DEVICE, ORION5X_ATTR_DEV_CS2,
> + ORION5X_WIN_ENABLE), &winregs[6].ctrl);
> + writel(ORION5X_DEFADR_DEV_CS2, &winregs[6].base);
> +
> + /* Window 7: BOOT Memory address space */
> + writel(ORION5X_CPU_WIN_CTRL_DATA(ORION5X_DEFSZ_BOOTROM,
> + ORION5X_TARGET_DEVICE, ORION5X_ATTR_BOOTROM,
> + ORION5X_WIN_ENABLE), &winregs[7].ctrl);
> + writel(ORION5X_DEFADR_BOOTROM, &winregs[7].base);
> +
> + return 0;
> +}
> +
> +/*
> + * Orion5x identification is done through PCIE space.
> + */
> +#define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000)
> +#define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008)
> +u32 orion5x_device_id(void)
> +{
> + return readl(PCIE_DEV_ID_OFF) >> 16;
> +}
> +
> +u32 orion5x_device_rev(void)
> +{
> + return readl(PCIE_DEV_REV_OFF) & 0xff;
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +
> +int print_cpuinfo(void)
> +{
> + char dev_str[] = "0x0000";
> + char rev_str[] = "0x00";
> + char *dev_name = NULL;
> + char *rev_name = NULL;
> +
> + u32 dev = orion5x_device_id();
> + u32 rev = orion5x_device_rev();
> +
> + if (dev == MV88F5181_DEV_ID) {
> + dev_name = "MV88F5181";
> + if (rev == MV88F5181_REV_B1)
> + rev_name = "B1";
> + else if (rev == MV88F5181L_REV_A1) {
> + dev_name = "MV88F5181L";
> + rev_name = "A1";
> + } else if (rev == MV88F5181L_REV_A0) {
> + dev_name = "MV88F5181L";
> + rev_name = "A0";
> + }
> + } else if (dev == MV88F5182_DEV_ID) {
> + dev_name = "MV88F5182";
> + if (rev == MV88F5182_REV_A2)
> + rev_name = "A2";
> + } else if (dev == MV88F5281_DEV_ID) {
> + dev_name = "MV88F5281";
> + if (rev == MV88F5281_REV_D2)
> + rev_name = "D2";
> + else if (rev == MV88F5281_REV_D1)
> + rev_name = "D1";
> + else if (rev == MV88F5281_REV_D0)
> + rev_name = "D0";
> + } else if (dev == MV88F6183_DEV_ID) {
> + dev_name = "MV88F6183";
> + if (rev == MV88F6183_REV_B0)
> + rev_name = "B0";
> + }
> + if (dev_name == NULL) {
> + sprintf(dev_str, "0x%04x", dev);
> + dev_name = dev_str;
> + }
> + if (rev_name == NULL) {
> + sprintf(rev_str, "0x%02x", rev);
> + rev_name = rev_str;
> + }
> +
> + printf("SoC: Orion5x %s-%s\n", dev_name, rev_name);
> +
> + return 0;
> +}
> +#endif /* CONFIG_DISPLAY_CPUINFO */
> +
> +#ifdef CONFIG_ARCH_CPU_INIT
> +int arch_cpu_init(void)
> +{
> + /* Enable and invalidate L2 cache in write through mode */
> + invalidate_l2_cache();
> +
> + orion5x_config_adr_windows();
> +
> + return 0;
> +}
> +#endif /* CONFIG_ARCH_CPU_INIT */
> +
> +/*
> + * SOC specific misc init
> + */
> +#if defined(CONFIG_ARCH_MISC_INIT)
> +int arch_misc_init(void)
> +{
> + u32 temp;
> +
> + /*CPU streaming & write allocate */
> + temp = readfr_extra_feature_reg();
> + temp &= ~(1 << 28); /* disable wr alloc */
> + writefr_extra_feature_reg(temp);
> +
> + temp = readfr_extra_feature_reg();
> + temp &= ~(1 << 29); /* streaming disabled */
> + writefr_extra_feature_reg(temp);
> +
> + /* L2Cache settings */
> + temp = readfr_extra_feature_reg();
> + /* Disable L2C pre fetch - Set bit 24 */
> + temp |= (1 << 24);
> + /* enable L2C - Set bit 22 */
> + temp |= (1 << 22);
> + writefr_extra_feature_reg(temp);
> +
> + icache_enable();
> + /* Change reset vector to address 0x0 */
> + temp = get_cr();
> + set_cr(temp & ~CR_V);
> +
> + return 0;
> +}
> +#endif /* CONFIG_ARCH_MISC_INIT */
> diff --git a/cpu/arm926ejs/orion5x/dram.c
> b/cpu/arm926ejs/orion5x/dram.c
> new file mode 100644
> index 0000000..ba6dd91
> --- /dev/null
> +++ b/cpu/arm926ejs/orion5x/dram.c
> @@ -0,0 +1,61 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirkwood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <config.h>
> +#include <asm/arch/orion5x.h>
> +
> +#define ORION5X_REG_CPUCS_WIN_BAR(x)
> (ORION5X_REGISTER(0x1500) + (x * 0x08))
> +#define ORION5X_REG_CPUCS_WIN_SZ(x)
> (ORION5X_REGISTER(0x1504) + (x * 0x08))
As Suggested by Wolfgang
Please use c data structures to represent CPU registers
> +/*
> + * orion5x_sdram_bar - reads SDRAM Base Address Register
> + */
> +u32 orion5x_sdram_bar(enum memory_bank bank)
> +{
> + u32 result = 0;
> + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
> +
> + if ((!enable) || (bank > BANK3))
> + return 0;
> +
> + result = readl(ORION5X_REG_CPUCS_WIN_BAR(bank));
> + return result;
> +}
> +
> +/*
> + * orion5x_sdram_bs - reads SDRAM Bank size
> + */
> +u32 orion5x_sdram_bs(enum memory_bank bank)
> +{
> + u32 result = 0;
> + u32 enable = 0x01 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
> +
> + if ((!enable) || (bank > BANK3))
> + return 0;
> + result = 0xff000000 & readl(ORION5X_REG_CPUCS_WIN_SZ(bank));
> + result += 0x01000000;
> + return result;
> +}
...snip...
> diff --git a/include/asm-arm/arch-orion5x/cpu.h
> b/include/asm-arm/arch-orion5x/cpu.h
> new file mode 100644
> index 0000000..706c9c0
> --- /dev/null
> +++ b/include/asm-arm/arch-orion5x/cpu.h
> @@ -0,0 +1,205 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirorion5x_ood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
...snip...
> +/*
> + * Default Device Address MAP BAR values
> + */
> +#define ORION5X_DEFADR_PCIE_MEM 0x90000000
> +#define ORION5X_DEFADR_PCIE_MEM_REMAP_LO 0x90000000
> +#define ORION5X_DEFADR_PCIE_MEM_REMAP_HI 0
> +#define ORION5X_DEFSZ_PCIE_MEM (128*1024*1024)
> +
> +#define ORION5X_DEFADR_PCIE_IO 0xf0000000
> +#define ORION5X_DEFADR_PCIE_IO_REMAP_LO 0x90000000
> +#define ORION5X_DEFADR_PCIE_IO_REMAP_HI 0
> +#define ORION5X_DEFSZ_PCIE_IO (64*1024)
> +
> +#define ORION5X_DEFADR_PCI_MEM 0x98000000
> +#define ORION5X_DEFSZ_PCI_MEM (128*1024*1024)
> +
> +#define ORION5X_DEFADR_PCI_IO 0xf0100000
> +#define ORION5X_DEFSZ_PCI_IO (64*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS0 0xfa000000
> +#define ORION5X_DEFSZ_DEV_CS0 (2*1024*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS1 0xf8000000
> +#define ORION5X_DEFSZ_DEV_CS1 (32*1024*1024)
> +
> +#define ORION5X_DEFADR_DEV_CS2 0xfa800000
> +#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
> +
> +#define ORION5X_DEFADR_BOOTROM 0xFFF80000
> +#define ORION5X_DEFSZ_BOOTROM (512*1024)
> +
The above PCI declaration not required right now, then can be added latter with PCI support for this SoC
...snip..
> diff --git a/include/asm-arm/arch-orion5x/orion5x.h
> b/include/asm-arm/arch-orion5x/orion5x.h
> new file mode 100644
> index 0000000..7b8ed65
> --- /dev/null
> +++ b/include/asm-arm/arch-orion5x/orion5x.h
> @@ -0,0 +1,65 @@
> +/*
> + * Copyright (C) 2009 Albert ARIBAUD <albert.aribaud at free.fr>
> + *
> + * Based on original Kirkwood support which is
> + * (C) Copyright 2009
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla at marvell.com>
> + *
> + * Header file for Marvell's Orion SoC with Feroceon CPU core.
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ASM_ARCH_ORION5X_H
> +#define _ASM_ARCH_ORION5X_H
> +
> +#ifndef __ASSEMBLY__
> +#include <asm/types.h>
> +#include <asm/io.h>
> +#endif /* __ASSEMBLY__ */
> +
> +#if defined(CONFIG_FEROCEON)
> +#include <asm/arch/cpu.h>
> +
> +/* SOC specific definations */
> +#define ORION5X_REGISTER(x)
> (ORION5X_REGS_PHY_BASE + x)
> +
> +/* Documented registers */
> +#define ORION5X_TWSI_BASE
> (ORION5X_REGISTER(0x11000))
> +#define ORION5X_UART0_BASE
> (ORION5X_REGISTER(0x12000))
> +#define ORION5X_UART1_BASE
> (ORION5X_REGISTER(0x12100))
> +#define ORION5X_MPP_BASE
> (ORION5X_REGISTER(0x10000))
> +#define ORION5X_GPIO_BASE
> (ORION5X_REGISTER(0x10100))
> +#define ORION5X_CPU_WIN_BASE
> (ORION5X_REGISTER(0x20000))
> +#define ORION5X_CPU_REG_BASE
> (ORION5X_REGISTER(0x20100))
> +#define ORION5X_TIMER_BASE
> (ORION5X_REGISTER(0x20300))
> +#define ORION5X_REG_PCI_BASE
> (ORION5X_REGISTER(0x30000))
> +#define ORION5X_REG_PCIE_BASE
> (ORION5X_REGISTER(0x40000))
> +#define ORION5X_USB20_PORT0_BASE
> (ORION5X_REGISTER(0x50000))
> +#define ORION5X_USB20_PORT1_BASE
> (ORION5X_REGISTER(0xA0000))
> +#define ORION5X_EGIGA_BASE
> (ORION5X_REGISTER(0x72000))
As suggested by wolfgang, pls use c structures here.
(FYI: we need to modify it for kirkwood too)
Regards..
Prafulla . .
> +
> +#if defined(CONFIG_88F5182)
> +#include <asm/arch/mv88f5182.h>
> +#else
> +#error "SOC Name not defined"
> +#endif
> +#endif /* CONFIG_FEROCEON */
> +#endif /* _ASM_ARCH_ORION5X_H */
> --
> 1.6.4.4
>
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