[U-Boot] [PATCH] ppc4xx: Cleanup PMC405 board support

Stefan Roese sr at denx.de
Tue Feb 17 15:19:28 CET 2009


On Sunday 15 February 2009, Matthias Fuchs wrote:
> This patch fixes coding style for PMC405 board support.
> Also some unneeded features/code is removed.

Please find some comments below.

> Signed-off-by: Matthias Fuchs <matthias.fuchs at esd-electronics.com>
> ---
>  board/esd/pmc405/pmc405.c |   95 ++++-----------
>  include/configs/PMC405.h  |  285
> ++++++++++++++++++++++----------------------- 2 files changed, 165
> insertions(+), 215 deletions(-)
>
> diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
> index 975b6d6..dd58d01 100644
> --- a/board/esd/pmc405/pmc405.c
> +++ b/board/esd/pmc405/pmc405.c
> @@ -40,7 +40,6 @@ const unsigned char fpgadata[] =
>  };
>  int filesize = sizeof(fpgadata);
>
> -
>  int board_early_init_f (void)
>  {
>  	/*
> @@ -55,23 +54,23 @@ int board_early_init_f (void)
>  	 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
>  	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
>  	 */
> -	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
> -	mtdcr(uicer, 0x00000000);       /* disable all ints */
> -	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
> -	mtdcr(uicpr, 0xFFFFFF81);       /* set int polarities */
> -	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
> -	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest
> priority*/ -	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
> +	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
> +	mtdcr(uicer, 0x00000000); /* disable all ints */
> +	mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
> +	mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
> +	mtdcr(uictr, 0x10000000); /* set int trigger levels */
> +	mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */
> +	mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
>
>  	/*
> -	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca.
> 15 us +	 * EBC Configuration Register:
> +	 * set ready timeout to 512 ebc-clks -> ca. 15 us
>  	 */
>  	mtebc (epcr, 0xa8400000);
>
>  	/*
>  	 * Setup GPIO pins
>  	 */
> -
>  	mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
>  					CONFIG_SYS_FPGA_DONE | \
>  					CONFIG_SYS_XEREADY | \
> @@ -85,26 +84,26 @@ int board_early_init_f (void)
>  	}
>
>  	out32(GPIO0_OR, 0);
> -	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
> CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */ +	/*
> setup for output */
> +	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \
> +	      CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY);

I suggest to switch to using the out_be32()/in_be32() accessor functions 
instead. I am aware that many other 4xx boards still use the "wrong" accessor 
functions for initial GPIO configuration. I'll try to change this soon.

Thanks.

Best regards,
Stefan

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