[U-Boot] [PATCH] Fix mpc85xx ddr-gen3 ddr_sdram_cfg.

[Ed Swarthout]

Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other
sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set.

Signed-off-by: Ed Swarthout <Ed.Swarthout at freescale.com>
---

ECC and self refresh are broke for mpc8572ds in 2009.03-rc1.

=> md ffe02110 1
ffe02110: 83000000  (should be e3...)

 cpu/mpc85xx/ddr-gen3.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c
index 8dc2b3a..99c325a 100644
--- a/cpu/mpc85xx/ddr-gen3.c
+++ b/cpu/mpc85xx/ddr-gen3.c
@@ -79,8 +79,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
 
-	/* Do not enable the memory */
-	temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+	/* Set, but do not enable the memory */
+	temp_sdram_cfg = regs->ddr_sdram_cfg;
 	temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 	/*
-- 
1.5.6.5