[U-Boot] MPC8548 not able to detect Marvell 88E1145 PHY

[Ajeesh Kumar]

Hi Sir/Madam,
 
We were working on EP8548A board (MPC8548E silicon revision 2.0) which had a
u-boot 1.2.0. Also, MPC8548 eTSECn was connected to a Marvell PHY(D0
version) chip 88E1145(4 ports) and 2 ethernet ports are working fine.
 
Now we have a custom board which is similar to EP8548A. But with MPC8548E
silicon revision 2.1 and Marvell PHY with E0 version.
The eTSECn is conntected to Marvell PHY(4 ports) chip. I'm able to boot our
custom board using the same u-boot 1.2.0 which was used for EP8548 board.
But I'm not able to detect and configure my PHY chip. I have a board
configuration file with TSEC related macros as below
 
#define CONFIG_MII              1       /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1    1
#define CONFIG_MPC85XX_TSEC1_NAME       "eTSEC0"
#define CONFIG_MPC85XX_TSEC2    1
#define CONFIG_MPC85XX_TSEC2_NAME       "eTSEC1"
#define CONFIG_MPC85XX_TSEC3    1
#define CONFIG_MPC85XX_TSEC3_NAME       "eTSEC2"
#define CONFIG_MPC85XX_TSEC4    1
#define CONFIG_MPC85XX_TSEC4_NAME       "eTSEC3"
 
#define TSEC1_PHY_ADDR          0
#define TSEC2_PHY_ADDR          1
#define TSEC3_PHY_ADDR          2
#define TSEC4_PHY_ADDR          3
 
#define TSEC1_FLAGS             TSEC_GIGABIT | TSEC_REDUCED
#define TSEC2_FLAGS             TSEC_GIGABIT | TSEC_REDUCED
#define TSEC3_FLAGS             TSEC_GIGABIT | TSEC_REDUCED
#define TSEC4_FLAGS             TSEC_GIGABIT | TSEC_REDUCED
 
#define TSEC1_PHYIDX            0
#define TSEC2_PHYIDX            0
#define TSEC3_PHYIDX            0
#define TSEC4_PHYIDX            0
 
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME         "eTSEC0"
 
When the U-boot comes up i get the below display:
 
U-Boot 1.2.0 (Jan  5 2009 - 10:18:30)
 
CPU:   8548_E, Version: 2.1, (0x80390021)
Core:  E500, Version: 2.2, (0x80210022)
Clock Configuration:
       CPU: 666 MHz, CCB: 266 MHz,
       DDR: 133 MHz, LBC:  33 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: ..........
I2C:   ready
DRAM:  Initializing
    DDR: 512 MB
SRIO: disabled
FLASH: 128 MB
L2 cache 512KB: enabled
*** Warning - bad CRC, using default environment
 
PCIe: disabled
In:    serial
Out:   serial
Err:   serial
Net:   eTSEC0: PHY id ffffffff is not supported!
eTSEC0: No PHY found
eTSEC1: PHY id ffffffff is not supported!
eTSEC1: No PHY found
eTSEC2: PHY id ffffffff is not supported!
eTSEC2: No PHY found
eTSEC3: PHY id ffffffff is not supported!
eTSEC3: No PHY found
eTSEC0, eTSEC1, eTSEC2, eTSEC3
Hit any key to stop autoboot:  0
## Booting image at fc000000 ...
Bad Magic Number
<board>=>
 
Later we scanned through all the PHY address(0 to 31) and only ONE port's
PHY address(0x12) was successfully read.
 
Our queries are as follows
 
1. Why were we not able to detect and configure the PHY in the first
attempt???
 
2. Why other PHY address are not set. We checked the Hardware its correct.