[U-Boot] [PATCH 2/3 v2] MIPS: Add VCT board series support (Part 2/3)
Stefan Roese
sr at denx.de
Tue Jan 6 11:35:57 CET 2009
This patch adds support for the Micronas VCT board series.
Currently the following platforms are supported:
vct_premium
vct_premium_small
vct_premium_onenand
vct_premium_onenand_small
vct_platinum
vct_platinum_small
vct_platinum_onenand
vct_platinum_onenand_small
vct_platinumavc
vct_platinumavc_small
vct_platinumavc_onenand
vct_platinumavc_onenand_small
One speciality of the VCT board is that it can't access NOR FLASH
memory-mapped. It has to use special access functions for this.
Signed-off-by: Stefan Roese <sr at denx.de>
---
v2:
- No changes
board/micronas/vct/ebi.h | 95 +++++++++++
board/micronas/vct/vct.h | 97 +++++++++++
board/micronas/vct/vcth/reg_dcgu.h | 25 +++
board/micronas/vct/vcth/reg_ebi.h | 242 ++++++++++++++++++++++++++
board/micronas/vct/vcth/reg_fwsram.h | 73 ++++++++
board/micronas/vct/vcth/reg_gpio.h | 32 ++++
board/micronas/vct/vcth/reg_wdt.h | 24 +++
board/micronas/vct/vcth2/reg_ebi.h | 290 +++++++++++++++++++++++++++++++
board/micronas/vct/vctv/reg_dcgu.h | 25 +++
board/micronas/vct/vctv/reg_ebi.h | 290 +++++++++++++++++++++++++++++++
board/micronas/vct/vctv/reg_gpio.h | 32 ++++
board/micronas/vct/vctv/reg_wdt.h | 24 +++
include/configs/vct.h | 310 ++++++++++++++++++++++++++++++++++
13 files changed, 1559 insertions(+), 0 deletions(-)
create mode 100644 board/micronas/vct/ebi.h
create mode 100644 board/micronas/vct/vct.h
create mode 100644 board/micronas/vct/vcth/reg_dcgu.h
create mode 100644 board/micronas/vct/vcth/reg_ebi.h
create mode 100644 board/micronas/vct/vcth/reg_fwsram.h
create mode 100644 board/micronas/vct/vcth/reg_gpio.h
create mode 100644 board/micronas/vct/vcth/reg_wdt.h
create mode 100644 board/micronas/vct/vcth2/reg_ebi.h
create mode 100644 board/micronas/vct/vctv/reg_dcgu.h
create mode 100644 board/micronas/vct/vctv/reg_ebi.h
create mode 100644 board/micronas/vct/vctv/reg_gpio.h
create mode 100644 board/micronas/vct/vctv/reg_wdt.h
create mode 100644 include/configs/vct.h
diff --git a/board/micronas/vct/ebi.h b/board/micronas/vct/ebi.h
new file mode 100644
index 0000000..69456bd
--- /dev/null
+++ b/board/micronas/vct/ebi.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __EBI__
+#define __EBI__
+
+#include <common.h>
+#include <asm/io.h>
+#include "vct.h"
+
+#define EXT_DEVICE_CHANNEL_3 (0x30000000)
+#define EXT_DEVICE_CHANNEL_2 (0x20000000)
+#define EXT_DEVICE_CHANNEL_1 (0x10000000)
+#define EXT_CPU_ACCESS_ACTIVE (0x00000001)
+#define EXT_DMA_ACCESS_ACTIVE (1 << 14)
+#define EXT_CPU_IORDY_SL (0x00000001)
+
+#define EBI_CPU_WRITE (1 << 31)
+#define EBI_CPU_ID_SHIFT (28)
+#define EBI_CPU_ADDR_MASK ~(~0UL << EBI_CPU_ID_SHIFT)
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD1 */
+#define ADDR_LATCH_ENABLE 0
+#define ADDR_ACTIVATION 4
+#define CHIP_SELECT_START 8
+#define OUTPUT_ENABLE_START 12
+#define WAIT_TIME 28
+#define READ_DURATION 20
+
+/* position of various bit slices in timing register EBI_DEV[01]_TIM1_RD2 */
+#define OUTPUT_ENABLE_END 0
+#define CHIP_SELECT_END 4
+#define ADDR_DEACTIVATION 8
+#define RECOVER_TIME 12
+#define ACK_TIME 20
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG1 */
+#define EBI_EXTERNAL_DATA_8 (1 << 8)
+#define EBI_EXT_ADDR_SHIFT (1 << 22)
+#define EBI_EXTERNAL_DATA_16 EBI_EXT_ADDR_SHIFT
+#define EBI_CHIP_SELECT_1 0x2
+#define EBI_CHIP_SELECT_2 0x4
+#define EBI_BUSY_EN_RD (1 << 12)
+#define DIR_ACCESS_WRITE (1 << 20)
+#define DIR_ACCESS_MASK (1 << 20)
+
+/* various bits in configuration register EBI_DEV[01]_CONFIG2 */
+#define ADDRESS_INCREMENT_ON 0x0
+#define ADDRESS_INCREMENT_OFF 0x100
+#define QUEUE_LENGTH_1 0x40
+#define QUEUE_LENGTH_2 0x80
+#define QUEUE_LENGTH_3 0xC0
+#define QUEUE_LENGTH_4 0
+#define CPU_TRANSFER_SIZE_32 0
+#define CPU_TRANSFER_SIZE_16 0x10
+#define CPU_TRANSFER_SIZE_8 0x20
+#define READ_ENDIANNESS_ABCD 0
+#define READ_ENDIANNESS_DCBA 0x4
+#define READ_ENDIANNESS_BADC 0x8
+#define READ_ENDIANNESS_CDAB 0xC
+#define WRITE_ENDIANNESS_ABCD 0
+#define WRITE_ENDIANNESS_DCBA 0x1
+#define WRITE_ENDIANNESS_BADC 0x2
+#define WRITE_ENDIANNESS_CDAB 0x3
+
+/* various bits in configuration register EBI_CTRL_SIG_ACTLV */
+#define IORDY_ACTIVELEVEL_HIGH (1 << 14)
+#define ALE_ACTIVELEVEL_HIGH (1 << 8)
+
+/* bits in register EBI_SIG_LEVEL */
+#define IORDY_LEVEL_MASK 1
+
+static inline void ebi_wait(void)
+{
+ while (reg_read(EBI_STATUS(EBI_BASE)) & EXT_CPU_ACCESS_ACTIVE)
+ ; /* wait */
+}
+
+#endif
diff --git a/board/micronas/vct/vct.h b/board/micronas/vct/vct.h
new file mode 100644
index 0000000..c14f46d
--- /dev/null
+++ b/board/micronas/vct/vct.h
@@ -0,0 +1,97 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+
+#include "ebi.h"
+
+#ifdef CONFIG_VCT_PREMIUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUM
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbf800000
+#define TOP_BASE 0x000c8000
+
+#include "vcth2/reg_ebi.h"
+#include "vcth/reg_dcgu.h"
+#include "vcth/reg_wdt.h"
+#include "vcth/reg_gpio.h"
+#include "vcth/reg_fwsram.h"
+#endif
+
+#ifdef CONFIG_VCT_PLATINUMAVC
+/* Global start address of all memory mapped registers */
+#define REG_GLOBAL_START_ADDR 0xbdc00000
+#define TOP_BASE 0x00050000
+
+#include "vctv/reg_ebi.h"
+#include "vctv/reg_dcgu.h"
+#include "vctv/reg_wdt.h"
+#include "vctv/reg_gpio.h"
+#endif
+
+#ifndef _VCT_H
+#define _VCT_H
+
+/*
+ * Defines
+ */
+#define PRID_COMP_LEGACY 0x000000
+#define PRID_COMP_MIPS 0x010000
+#define PRID_IMP_LX4280 0xc200
+#define PRID_IMP_VGC 0x9000
+
+/*
+ * Prototypes
+ */
+int ebi_initialize(void);
+int ebi_init_nor_flash(void);
+int ebi_init_onenand(void);
+int ebi_init_smc911x(void);
+u32 smc911x_reg_read(u32 addr);
+void smc911x_reg_write(u32 addr, u32 data);
+int top_set_pin(int pin, int func);
+void vct_pin_mux_initialize(void);
+
+/*
+ * static inlines
+ */
+static inline void reg_write(u32 addr, u32 data)
+{
+ __raw_writel(data, addr + REG_GLOBAL_START_ADDR);
+}
+
+static inline u32 reg_read(u32 addr)
+{
+ return __raw_readl(addr + REG_GLOBAL_START_ADDR);
+}
+
+#endif /* _VCT_H */
diff --git a/board/micronas/vct/vcth/reg_dcgu.h b/board/micronas/vct/vcth/reg_dcgu.h
new file mode 100644
index 0000000..c83ef27
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_dcgu.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE 0x00084000
+#define DCGU_EN_WDT_RESET_OFFS 0x00000064
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vcth/reg_ebi.h b/board/micronas/vct/vcth/reg_ebi.h
new file mode 100644
index 0000000..7a1e115
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_ebi.h
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000008
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000010
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_fwsram.h b/board/micronas/vct/vcth/reg_fwsram.h
new file mode 100644
index 0000000..19afb6b
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_fwsram.h
@@ -0,0 +1,73 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Premium & Platinum register addresses/definitions seem to be
+ * identical, so we only need to use one file for both platforms.
+ */
+
+#ifndef _REG_FWSRAM_H_
+#define _REG_FWSRAM_H_
+
+#define FWSRAM_BASE 0x00030000
+
+/* Relative offsets of the register adresses */
+
+#define FWSRAM_SR_ADDR_OFFSET_OFFS 0x00002000
+#define FWSRAM_SR_ADDR_OFFSET(base) ((base) + FWSRAM_SR_ADDR_OFFSET_OFFS)
+#define FWSRAM_TOP_BOOT_LOG_OFFS 0x00002004
+#define FWSRAM_TOP_BOOT_LOG(base) ((base) + FWSRAM_TOP_BOOT_LOG_OFFS)
+#define FWSRAM_TOP_ROM_KBIST_OFFS 0x00002008
+#define FWSRAM_TOP_ROM_KBIST(base) ((base) + FWSRAM_TOP_ROM_KBIST_OFFS)
+#define FWSRAM_TOP_CID1_H_OFFS 0x0000200C
+#define FWSRAM_TOP_CID1_H(base) ((base) + FWSRAM_TOP_CID1_H_OFFS)
+#define FWSRAM_TOP_CID1_L_OFFS 0x00002010
+#define FWSRAM_TOP_CID1_L(base) ((base) + FWSRAM_TOP_CID1_L_OFFS)
+#define FWSRAM_TOP_CID2_H_OFFS 0x00002014
+#define FWSRAM_TOP_CID2_H(base) ((base) + FWSRAM_TOP_CID2_H_OFFS)
+#define FWSRAM_TOP_CID2_L_OFFS 0x00002018
+#define FWSRAM_TOP_CID2_L(base) ((base) + FWSRAM_TOP_CID2_L_OFFS)
+#define FWSRAM_TOP_TDO_CFG_OFFS 0x0000203C
+#define FWSRAM_TOP_TDO_CFG(base) ((base) + FWSRAM_TOP_TDO_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_0_CFG_OFFS 0x00002040
+#define FWSRAM_TOP_GPIO2_0_CFG(base) ((base) + FWSRAM_TOP_GPIO2_0_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_1_CFG_OFFS 0x00002044
+#define FWSRAM_TOP_GPIO2_1_CFG(base) ((base) + FWSRAM_TOP_GPIO2_1_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_2_CFG_OFFS 0x00002048
+#define FWSRAM_TOP_GPIO2_2_CFG(base) ((base) + FWSRAM_TOP_GPIO2_2_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_3_CFG_OFFS 0x0000204C
+#define FWSRAM_TOP_GPIO2_3_CFG(base) ((base) + FWSRAM_TOP_GPIO2_3_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_4_CFG_OFFS 0x00002050
+#define FWSRAM_TOP_GPIO2_4_CFG(base) ((base) + FWSRAM_TOP_GPIO2_4_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_5_CFG_OFFS 0x00002054
+#define FWSRAM_TOP_GPIO2_5_CFG(base) ((base) + FWSRAM_TOP_GPIO2_5_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_6_CFG_OFFS 0x00002058
+#define FWSRAM_TOP_GPIO2_6_CFG(base) ((base) + FWSRAM_TOP_GPIO2_6_CFG_OFFS)
+#define FWSRAM_TOP_GPIO2_7_CFG_OFFS 0x0000205C
+#define FWSRAM_TOP_GPIO2_7_CFG(base) ((base) + FWSRAM_TOP_GPIO2_7_CFG_OFFS)
+#define FWSRAM_TOP_SCL_CFG_OFFS 0x00002060
+#define FWSRAM_TOP_SCL_CFG(base) ((base) + FWSRAM_TOP_SCL_CFG_OFFS)
+#define FWSRAM_TOP_SDA_CFG_OFFS 0x00002064
+#define FWSRAM_TOP_SDA_CFG(base) ((base) + FWSRAM_TOP_SDA_CFG_OFFS)
+#define FWSRAM_NO_MCM_FLASH_OFFS 0x00002068
+#define FWSRAM_NO_MCM_FLASH(base) ((base) + FWSRAM_NO_MCM_FLASH_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vcth/reg_gpio.h b/board/micronas/vct/vcth/reg_gpio.h
new file mode 100644
index 0000000..7ada9c9
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE 0x00088000
+#define GPIO2_BASE 0x0008c000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vcth/reg_wdt.h b/board/micronas/vct/vcth/reg_wdt.h
new file mode 100644
index 0000000..a9b4bf0
--- /dev/null
+++ b/board/micronas/vct/vcth/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE 0x000b0000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/board/micronas/vct/vcth2/reg_ebi.h b/board/micronas/vct/vcth2/reg_ebi.h
new file mode 100644
index 0000000..37f0711
--- /dev/null
+++ b/board/micronas/vct/vcth2/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PREMIUM_H_
+#define _REG_EBI_PREMIUM_H_
+
+#define EBI_BASE 0x00000000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_dcgu.h b/board/micronas/vct/vctv/reg_dcgu.h
new file mode 100644
index 0000000..6f5c968
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_dcgu.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define DCGU_BASE 0x0004c000
+#define DCGU_EN_WDT_RESET_OFFS 0x000000FC
+#define DCGU_EN_WDT_RESET(base) ((base) + DCGU_EN_WDT_RESET_OFFS)
+
+/* The magic value to write in order to activate the WDT */
+#define DCGU_MAGIC_WDT 0x1909
diff --git a/board/micronas/vct/vctv/reg_ebi.h b/board/micronas/vct/vctv/reg_ebi.h
new file mode 100644
index 0000000..82f345e
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_ebi.h
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * Copyright (C) 2006 Micronas GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _REG_EBI_PLATINUMAVC_H_
+#define _REG_EBI_PLATINUMAVC_H_
+
+#define EBI_BASE 0x00014000
+
+/* Relative offsets of the register adresses */
+
+#define EBI_CPU_IO_ACCS_OFFS 0x00000000
+#define EBI_CPU_IO_ACCS(base) ((base) + EBI_CPU_IO_ACCS_OFFS)
+#define EBI_IO_ACCS_DATA_OFFS 0x00000004
+#define EBI_IO_ACCS_DATA(base) ((base) + EBI_IO_ACCS_DATA_OFFS)
+#define EBI_CPU_IO_ACCS2_OFFS 0x00000008
+#define EBI_CPU_IO_ACCS2(base) ((base) + EBI_CPU_IO_ACCS2_OFFS)
+#define EBI_IO_ACCS2_DATA_OFFS 0x0000000C
+#define EBI_IO_ACCS2_DATA(base) ((base) + EBI_IO_ACCS2_DATA_OFFS)
+#define EBI_CTRL_OFFS 0x00000010
+#define EBI_CTRL(base) ((base) + EBI_CTRL_OFFS)
+#define EBI_IRQ_MASK_OFFS 0x00000018
+#define EBI_IRQ_MASK(base) ((base) + EBI_IRQ_MASK_OFFS)
+#define EBI_IRQ_MASK2_OFFS 0x0000001C
+#define EBI_IRQ_MASK2(base) ((base) + EBI_IRQ_MASK2_OFFS)
+#define EBI_TAG1_SYS_ID_OFFS 0x00000030
+#define EBI_TAG1_SYS_ID(base) ((base) + EBI_TAG1_SYS_ID_OFFS)
+#define EBI_TAG2_SYS_ID_OFFS 0x00000040
+#define EBI_TAG2_SYS_ID(base) ((base) + EBI_TAG2_SYS_ID_OFFS)
+#define EBI_TAG3_SYS_ID_OFFS 0x00000050
+#define EBI_TAG3_SYS_ID(base) ((base) + EBI_TAG3_SYS_ID_OFFS)
+#define EBI_TAG4_SYS_ID_OFFS 0x00000060
+#define EBI_TAG4_SYS_ID(base) ((base) + EBI_TAG4_SYS_ID_OFFS)
+#define EBI_GEN_DMA_CTRL_OFFS 0x00000070
+#define EBI_GEN_DMA_CTRL(base) ((base) + EBI_GEN_DMA_CTRL_OFFS)
+#define EBI_STATUS_OFFS 0x00000080
+#define EBI_STATUS(base) ((base) + EBI_STATUS_OFFS)
+#define EBI_STATUS_DMA_CNT_OFFS 0x00000084
+#define EBI_STATUS_DMA_CNT(base) ((base) + EBI_STATUS_DMA_CNT_OFFS)
+#define EBI_SIG_LEVEL_OFFS 0x00000088
+#define EBI_SIG_LEVEL(base) ((base) + EBI_SIG_LEVEL_OFFS)
+#define EBI_CTRL_SIG_ACTLV_OFFS 0x0000008C
+#define EBI_CTRL_SIG_ACTLV(base) ((base) + EBI_CTRL_SIG_ACTLV_OFFS)
+#define EBI_CRC_GEN_OFFS 0x00000090
+#define EBI_CRC_GEN(base) ((base) + EBI_CRC_GEN_OFFS)
+#define EBI_EXT_ADDR_OFFS 0x000000A0
+#define EBI_EXT_ADDR(base) ((base) + EBI_EXT_ADDR_OFFS)
+#define EBI_IRQ_STATUS_OFFS 0x000000B0
+#define EBI_IRQ_STATUS(base) ((base) + EBI_IRQ_STATUS_OFFS)
+#define EBI_IRQ_STATUS2_OFFS 0x000000B4
+#define EBI_IRQ_STATUS2(base) ((base) + EBI_IRQ_STATUS2_OFFS)
+#define EBI_EXT_MASTER_SRAM_HIGH_OFFS 0x000000C0
+#define EBI_EXT_MASTER_SRAM_HIGH(base) ((base) + EBI_EXT_MASTER_SRAM_HIGH_OFFS)
+#define EBI_EXT_MASTER_SRAM_LOW_OFFS 0x000000C4
+#define EBI_EXT_MASTER_SRAM_LOW(base) ((base) + EBI_EXT_MASTER_SRAM_LOW_OFFS)
+#define EBI_ECC0_OFFS 0x000000D0
+#define EBI_ECC0(base) ((base) + EBI_ECC0_OFFS)
+#define EBI_ECC1_OFFS 0x000000D4
+#define EBI_ECC1(base) ((base) + EBI_ECC1_OFFS)
+#define EBI_ECC2_OFFS 0x000000D8
+#define EBI_ECC2(base) ((base) + EBI_ECC2_OFFS)
+#define EBI_ECC3_OFFS 0x000000DC
+#define EBI_ECC3(base) ((base) + EBI_ECC3_OFFS)
+#define EBI_DEV1_DMA_EXT_ADDR_OFFS 0x00000100
+#define EBI_DEV1_DMA_EXT_ADDR(base) ((base) + EBI_DEV1_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV1_EXT_ACC_OFFS 0x00000104
+#define EBI_DEV1_EXT_ACC(base) ((base) + EBI_DEV1_EXT_ACC_OFFS)
+#define EBI_DEV1_CONFIG1_OFFS 0x00000108
+#define EBI_DEV1_CONFIG1(base) ((base) + EBI_DEV1_CONFIG1_OFFS)
+#define EBI_DEV1_CONFIG2_OFFS 0x0000010C
+#define EBI_DEV1_CONFIG2(base) ((base) + EBI_DEV1_CONFIG2_OFFS)
+#define EBI_DEV1_FIFO_CONFIG_OFFS 0x00000110
+#define EBI_DEV1_FIFO_CONFIG(base) ((base) + EBI_DEV1_FIFO_CONFIG_OFFS)
+#define EBI_DEV1_FLASH_CONF_ST_OFFS 0x00000114
+#define EBI_DEV1_FLASH_CONF_ST(base) ((base) + EBI_DEV1_FLASH_CONF_ST_OFFS)
+#define EBI_DEV1_DMA_CONFIG1_OFFS 0x00000118
+#define EBI_DEV1_DMA_CONFIG1(base) ((base) + EBI_DEV1_DMA_CONFIG1_OFFS)
+#define EBI_DEV1_DMA_CONFIG2_OFFS 0x0000011C
+#define EBI_DEV1_DMA_CONFIG2(base) ((base) + EBI_DEV1_DMA_CONFIG2_OFFS)
+#define EBI_DEV1_DMA_ECC_CTRL_OFFS 0x00000120
+#define EBI_DEV1_DMA_ECC_CTRL(base) ((base) + EBI_DEV1_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV1_TIM1_RD1_OFFS 0x00000124
+#define EBI_DEV1_TIM1_RD1(base) ((base) + EBI_DEV1_TIM1_RD1_OFFS)
+#define EBI_DEV1_TIM1_RD2_OFFS 0x00000128
+#define EBI_DEV1_TIM1_RD2(base) ((base) + EBI_DEV1_TIM1_RD2_OFFS)
+#define EBI_DEV1_TIM1_WR1_OFFS 0x0000012C
+#define EBI_DEV1_TIM1_WR1(base) ((base) + EBI_DEV1_TIM1_WR1_OFFS)
+#define EBI_DEV1_TIM1_WR2_OFFS 0x00000130
+#define EBI_DEV1_TIM1_WR2(base) ((base) + EBI_DEV1_TIM1_WR2_OFFS)
+#define EBI_DEV1_TIM_EXT_OFFS 0x00000134
+#define EBI_DEV1_TIM_EXT(base) ((base) + EBI_DEV1_TIM_EXT_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD1_OFFS 0x00000138
+#define EBI_DEV1_TIM2_CFI_RD1(base) ((base) + EBI_DEV1_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV1_TIM2_CFI_RD2_OFFS 0x0000013C
+#define EBI_DEV1_TIM2_CFI_RD2(base) ((base) + EBI_DEV1_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV1_TIM3_DMA1_OFFS 0x00000140
+#define EBI_DEV1_TIM3_DMA1(base) ((base) + EBI_DEV1_TIM3_DMA1_OFFS)
+#define EBI_DEV1_TIM3_DMA2_OFFS 0x00000144
+#define EBI_DEV1_TIM3_DMA2(base) ((base) + EBI_DEV1_TIM3_DMA2_OFFS)
+#define EBI_DEV1_TIM4_UDMA1_OFFS 0x00000148
+#define EBI_DEV1_TIM4_UDMA1(base) ((base) + EBI_DEV1_TIM4_UDMA1_OFFS)
+#define EBI_DEV1_TIM4_UDMA2_OFFS 0x0000014C
+#define EBI_DEV1_TIM4_UDMA2(base) ((base) + EBI_DEV1_TIM4_UDMA2_OFFS)
+#define EBI_DEV1_ACK_RM_CNT_OFFS 0x00000150
+#define EBI_DEV1_ACK_RM_CNT(base) ((base) + EBI_DEV1_ACK_RM_CNT_OFFS)
+#define EBI_DEV2_DMA_EXT_ADDR_OFFS 0x00000200
+#define EBI_DEV2_DMA_EXT_ADDR(base) ((base) + EBI_DEV2_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV2_EXT_ACC_OFFS 0x00000204
+#define EBI_DEV2_EXT_ACC(base) ((base) + EBI_DEV2_EXT_ACC_OFFS)
+#define EBI_DEV2_CONFIG1_OFFS 0x00000208
+#define EBI_DEV2_CONFIG1(base) ((base) + EBI_DEV2_CONFIG1_OFFS)
+#define EBI_DEV2_CONFIG2_OFFS 0x0000020C
+#define EBI_DEV2_CONFIG2(base) ((base) + EBI_DEV2_CONFIG2_OFFS)
+#define EBI_DEV2_FIFO_CONFIG_OFFS 0x00000210
+#define EBI_DEV2_FIFO_CONFIG(base) ((base) + EBI_DEV2_FIFO_CONFIG_OFFS)
+#define EBI_DEV2_FLASH_CONF_ST_OFFS 0x00000214
+#define EBI_DEV2_FLASH_CONF_ST(base) ((base) + EBI_DEV2_FLASH_CONF_ST_OFFS)
+#define EBI_DEV2_DMA_CONFIG1_OFFS 0x00000218
+#define EBI_DEV2_DMA_CONFIG1(base) ((base) + EBI_DEV2_DMA_CONFIG1_OFFS)
+#define EBI_DEV2_DMA_CONFIG2_OFFS 0x0000021C
+#define EBI_DEV2_DMA_CONFIG2(base) ((base) + EBI_DEV2_DMA_CONFIG2_OFFS)
+#define EBI_DEV2_DMA_ECC_CTRL_OFFS 0x00000220
+#define EBI_DEV2_DMA_ECC_CTRL(base) ((base) + EBI_DEV2_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV2_TIM1_RD1_OFFS 0x00000224
+#define EBI_DEV2_TIM1_RD1(base) ((base) + EBI_DEV2_TIM1_RD1_OFFS)
+#define EBI_DEV2_TIM1_RD2_OFFS 0x00000228
+#define EBI_DEV2_TIM1_RD2(base) ((base) + EBI_DEV2_TIM1_RD2_OFFS)
+#define EBI_DEV2_TIM1_WR1_OFFS 0x0000022C
+#define EBI_DEV2_TIM1_WR1(base) ((base) + EBI_DEV2_TIM1_WR1_OFFS)
+#define EBI_DEV2_TIM1_WR2_OFFS 0x00000230
+#define EBI_DEV2_TIM1_WR2(base) ((base) + EBI_DEV2_TIM1_WR2_OFFS)
+#define EBI_DEV2_TIM_EXT_OFFS 0x00000234
+#define EBI_DEV2_TIM_EXT(base) ((base) + EBI_DEV2_TIM_EXT_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD1_OFFS 0x00000238
+#define EBI_DEV2_TIM2_CFI_RD1(base) ((base) + EBI_DEV2_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV2_TIM2_CFI_RD2_OFFS 0x0000023C
+#define EBI_DEV2_TIM2_CFI_RD2(base) ((base) + EBI_DEV2_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV2_TIM3_DMA1_OFFS 0x00000240
+#define EBI_DEV2_TIM3_DMA1(base) ((base) + EBI_DEV2_TIM3_DMA1_OFFS)
+#define EBI_DEV2_TIM3_DMA2_OFFS 0x00000244
+#define EBI_DEV2_TIM3_DMA2(base) ((base) + EBI_DEV2_TIM3_DMA2_OFFS)
+#define EBI_DEV2_TIM4_UDMA1_OFFS 0x00000248
+#define EBI_DEV2_TIM4_UDMA1(base) ((base) + EBI_DEV2_TIM4_UDMA1_OFFS)
+#define EBI_DEV2_TIM4_UDMA2_OFFS 0x0000024C
+#define EBI_DEV2_TIM4_UDMA2(base) ((base) + EBI_DEV2_TIM4_UDMA2_OFFS)
+#define EBI_DEV2_ACK_RM_CNT_OFFS 0x00000250
+#define EBI_DEV2_ACK_RM_CNT(base) ((base) + EBI_DEV2_ACK_RM_CNT_OFFS)
+#define EBI_DEV3_DMA_EXT_ADDR_OFFS 0x00000300
+#define EBI_DEV3_DMA_EXT_ADDR(base) ((base) + EBI_DEV3_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV3_EXT_ACC_OFFS 0x00000304
+#define EBI_DEV3_EXT_ACC(base) ((base) + EBI_DEV3_EXT_ACC_OFFS)
+#define EBI_DEV3_CONFIG1_OFFS 0x00000308
+#define EBI_DEV3_CONFIG1(base) ((base) + EBI_DEV3_CONFIG1_OFFS)
+#define EBI_DEV3_CONFIG2_OFFS 0x0000030C
+#define EBI_DEV3_CONFIG2(base) ((base) + EBI_DEV3_CONFIG2_OFFS)
+#define EBI_DEV3_FIFO_CONFIG_OFFS 0x00000310
+#define EBI_DEV3_FIFO_CONFIG(base) ((base) + EBI_DEV3_FIFO_CONFIG_OFFS)
+#define EBI_DEV3_FLASH_CONF_ST_OFFS 0x00000314
+#define EBI_DEV3_FLASH_CONF_ST(base) ((base) + EBI_DEV3_FLASH_CONF_ST_OFFS)
+#define EBI_DEV3_DMA_CONFIG1_OFFS 0x00000318
+#define EBI_DEV3_DMA_CONFIG1(base) ((base) + EBI_DEV3_DMA_CONFIG1_OFFS)
+#define EBI_DEV3_DMA_CONFIG2_OFFS 0x0000031C
+#define EBI_DEV3_DMA_CONFIG2(base) ((base) + EBI_DEV3_DMA_CONFIG2_OFFS)
+#define EBI_DEV3_DMA_ECC_CTRL_OFFS 0x00000320
+#define EBI_DEV3_DMA_ECC_CTRL(base) ((base) + EBI_DEV3_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV3_TIM1_RD1_OFFS 0x00000324
+#define EBI_DEV3_TIM1_RD1(base) ((base) + EBI_DEV3_TIM1_RD1_OFFS)
+#define EBI_DEV3_TIM1_RD2_OFFS 0x00000328
+#define EBI_DEV3_TIM1_RD2(base) ((base) + EBI_DEV3_TIM1_RD2_OFFS)
+#define EBI_DEV3_TIM1_WR1_OFFS 0x0000032C
+#define EBI_DEV3_TIM1_WR1(base) ((base) + EBI_DEV3_TIM1_WR1_OFFS)
+#define EBI_DEV3_TIM1_WR2_OFFS 0x00000330
+#define EBI_DEV3_TIM1_WR2(base) ((base) + EBI_DEV3_TIM1_WR2_OFFS)
+#define EBI_DEV3_TIM_EXT_OFFS 0x00000334
+#define EBI_DEV3_TIM_EXT(base) ((base) + EBI_DEV3_TIM_EXT_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD1_OFFS 0x00000338
+#define EBI_DEV3_TIM2_CFI_RD1(base) ((base) + EBI_DEV3_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV3_TIM2_CFI_RD2_OFFS 0x0000033C
+#define EBI_DEV3_TIM2_CFI_RD2(base) ((base) + EBI_DEV3_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV3_TIM3_DMA1_OFFS 0x00000340
+#define EBI_DEV3_TIM3_DMA1(base) ((base) + EBI_DEV3_TIM3_DMA1_OFFS)
+#define EBI_DEV3_TIM3_DMA2_OFFS 0x00000344
+#define EBI_DEV3_TIM3_DMA2(base) ((base) + EBI_DEV3_TIM3_DMA2_OFFS)
+#define EBI_DEV3_TIM4_UDMA1_OFFS 0x00000348
+#define EBI_DEV3_TIM4_UDMA1(base) ((base) + EBI_DEV3_TIM4_UDMA1_OFFS)
+#define EBI_DEV3_TIM4_UDMA2_OFFS 0x0000034C
+#define EBI_DEV3_TIM4_UDMA2(base) ((base) + EBI_DEV3_TIM4_UDMA2_OFFS)
+#define EBI_DEV3_ACK_RM_CNT_OFFS 0x00000350
+#define EBI_DEV3_ACK_RM_CNT(base) ((base) + EBI_DEV3_ACK_RM_CNT_OFFS)
+#define EBI_DEV4_DMA_EXT_ADDR_OFFS 0x00000400
+#define EBI_DEV4_DMA_EXT_ADDR(base) ((base) + EBI_DEV4_DMA_EXT_ADDR_OFFS)
+#define EBI_DEV4_EXT_ACC_OFFS 0x00000404
+#define EBI_DEV4_EXT_ACC(base) ((base) + EBI_DEV4_EXT_ACC_OFFS)
+#define EBI_DEV4_CONFIG1_OFFS 0x00000408
+#define EBI_DEV4_CONFIG1(base) ((base) + EBI_DEV4_CONFIG1_OFFS)
+#define EBI_DEV4_CONFIG2_OFFS 0x0000040C
+#define EBI_DEV4_CONFIG2(base) ((base) + EBI_DEV4_CONFIG2_OFFS)
+#define EBI_DEV4_FIFO_CONFIG_OFFS 0x00000410
+#define EBI_DEV4_FIFO_CONFIG(base) ((base) + EBI_DEV4_FIFO_CONFIG_OFFS)
+#define EBI_DEV4_FLASH_CONF_ST_OFFS 0x00000414
+#define EBI_DEV4_FLASH_CONF_ST(base) ((base) + EBI_DEV4_FLASH_CONF_ST_OFFS)
+#define EBI_DEV4_DMA_CONFIG1_OFFS 0x00000418
+#define EBI_DEV4_DMA_CONFIG1(base) ((base) + EBI_DEV4_DMA_CONFIG1_OFFS)
+#define EBI_DEV4_DMA_CONFIG2_OFFS 0x0000041C
+#define EBI_DEV4_DMA_CONFIG2(base) ((base) + EBI_DEV4_DMA_CONFIG2_OFFS)
+#define EBI_DEV4_DMA_ECC_CTRL_OFFS 0x00000420
+#define EBI_DEV4_DMA_ECC_CTRL(base) ((base) + EBI_DEV4_DMA_ECC_CTRL_OFFS)
+#define EBI_DEV4_TIM1_RD1_OFFS 0x00000424
+#define EBI_DEV4_TIM1_RD1(base) ((base) + EBI_DEV4_TIM1_RD1_OFFS)
+#define EBI_DEV4_TIM1_RD2_OFFS 0x00000428
+#define EBI_DEV4_TIM1_RD2(base) ((base) + EBI_DEV4_TIM1_RD2_OFFS)
+#define EBI_DEV4_TIM1_WR1_OFFS 0x0000042C
+#define EBI_DEV4_TIM1_WR1(base) ((base) + EBI_DEV4_TIM1_WR1_OFFS)
+#define EBI_DEV4_TIM1_WR2_OFFS 0x00000430
+#define EBI_DEV4_TIM1_WR2(base) ((base) + EBI_DEV4_TIM1_WR2_OFFS)
+#define EBI_DEV4_TIM_EXT_OFFS 0x00000434
+#define EBI_DEV4_TIM_EXT(base) ((base) + EBI_DEV4_TIM_EXT_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD1_OFFS 0x00000438
+#define EBI_DEV4_TIM2_CFI_RD1(base) ((base) + EBI_DEV4_TIM2_CFI_RD1_OFFS)
+#define EBI_DEV4_TIM2_CFI_RD2_OFFS 0x0000043C
+#define EBI_DEV4_TIM2_CFI_RD2(base) ((base) + EBI_DEV4_TIM2_CFI_RD2_OFFS)
+#define EBI_DEV4_TIM3_DMA1_OFFS 0x00000440
+#define EBI_DEV4_TIM3_DMA1(base) ((base) + EBI_DEV4_TIM3_DMA1_OFFS)
+#define EBI_DEV4_TIM3_DMA2_OFFS 0x00000444
+#define EBI_DEV4_TIM3_DMA2(base) ((base) + EBI_DEV4_TIM3_DMA2_OFFS)
+#define EBI_DEV4_TIM4_UDMA1_OFFS 0x00000448
+#define EBI_DEV4_TIM4_UDMA1(base) ((base) + EBI_DEV4_TIM4_UDMA1_OFFS)
+#define EBI_DEV4_TIM4_UDMA2_OFFS 0x0000044C
+#define EBI_DEV4_TIM4_UDMA2(base) ((base) + EBI_DEV4_TIM4_UDMA2_OFFS)
+#define EBI_DEV4_ACK_RM_CNT_OFFS 0x00000450
+#define EBI_DEV4_ACK_RM_CNT(base) ((base) + EBI_DEV4_ACK_RM_CNT_OFFS)
+#define EBI_INTERLEAVE_CNT_OFFS 0x00000900
+#define EBI_INTERLEAVE_CNT(base) ((base) + EBI_INTERLEAVE_CNT_OFFS)
+#define EBI_CNT_FL_PROGR_OFFS 0x00000904
+#define EBI_CNT_FL_PROGR(base) ((base) + EBI_CNT_FL_PROGR_OFFS)
+#define EBI_CNT_EXT_PAGE_SZ_OFFS 0x0000090C
+#define EBI_CNT_EXT_PAGE_SZ(base) ((base) + EBI_CNT_EXT_PAGE_SZ_OFFS)
+#define EBI_CNT_WAIT_RDY_OFFS 0x00000914
+#define EBI_CNT_WAIT_RDY(base) ((base) + EBI_CNT_WAIT_RDY_OFFS)
+#define EBI_CNT_ACK_OFFS 0x00000918
+#define EBI_CNT_ACK(base) ((base) + EBI_CNT_ACK_OFFS)
+#define EBI_GENIO1_CONFIG1_OFFS 0x00000A00
+#define EBI_GENIO1_CONFIG1(base) ((base) + EBI_GENIO1_CONFIG1_OFFS)
+#define EBI_GENIO1_CONFIG2_OFFS 0x00000A04
+#define EBI_GENIO1_CONFIG2(base) ((base) + EBI_GENIO1_CONFIG2_OFFS)
+#define EBI_GENIO1_CONFIG3_OFFS 0x00000A08
+#define EBI_GENIO1_CONFIG3(base) ((base) + EBI_GENIO1_CONFIG3_OFFS)
+#define EBI_GENIO2_CONFIG1_OFFS 0x00000A10
+#define EBI_GENIO2_CONFIG1(base) ((base) + EBI_GENIO2_CONFIG1_OFFS)
+#define EBI_GENIO2_CONFIG2_OFFS 0x00000A14
+#define EBI_GENIO2_CONFIG2(base) ((base) + EBI_GENIO2_CONFIG2_OFFS)
+#define EBI_GENIO2_CONFIG3_OFFS 0x00000A18
+#define EBI_GENIO2_CONFIG3(base) ((base) + EBI_GENIO2_CONFIG3_OFFS)
+#define EBI_GENIO3_CONFIG1_OFFS 0x00000A20
+#define EBI_GENIO3_CONFIG1(base) ((base) + EBI_GENIO3_CONFIG1_OFFS)
+#define EBI_GENIO3_CONFIG2_OFFS 0x00000A24
+#define EBI_GENIO3_CONFIG2(base) ((base) + EBI_GENIO3_CONFIG2_OFFS)
+#define EBI_GENIO3_CONFIG3_OFFS 0x00000A28
+#define EBI_GENIO3_CONFIG3(base) ((base) + EBI_GENIO3_CONFIG3_OFFS)
+#define EBI_GENIO4_CONFIG1_OFFS 0x00000A30
+#define EBI_GENIO4_CONFIG1(base) ((base) + EBI_GENIO4_CONFIG1_OFFS)
+#define EBI_GENIO4_CONFIG2_OFFS 0x00000A34
+#define EBI_GENIO4_CONFIG2(base) ((base) + EBI_GENIO4_CONFIG2_OFFS)
+#define EBI_GENIO4_CONFIG3_OFFS 0x00000A38
+#define EBI_GENIO4_CONFIG3(base) ((base) + EBI_GENIO4_CONFIG3_OFFS)
+#define EBI_GENIO5_CONFIG1_OFFS 0x00000A40
+#define EBI_GENIO5_CONFIG1(base) ((base) + EBI_GENIO5_CONFIG1_OFFS)
+#define EBI_GENIO5_CONFIG2_OFFS 0x00000A44
+#define EBI_GENIO5_CONFIG2(base) ((base) + EBI_GENIO5_CONFIG2_OFFS)
+#define EBI_GENIO5_CONFIG3_OFFS 0x00000A48
+#define EBI_GENIO5_CONFIG3(base) ((base) + EBI_GENIO5_CONFIG3_OFFS)
+
+#endif
diff --git a/board/micronas/vct/vctv/reg_gpio.h b/board/micronas/vct/vctv/reg_gpio.h
new file mode 100644
index 0000000..24eb8e9
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_gpio.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define GPIO1_BASE 0x00044000
+#define GPIO2_BASE 0x00048000
+
+/* Instances */
+#define GPIO_INSTANCES 2
+
+/* Relative offsets of the register adresses */
+#define GPIO_SWPORTA_DR_OFFS 0x00000000
+#define GPIO_SWPORTA_DR(base) ((base) + GPIO_SWPORTA_DR_OFFS)
+#define GPIO_SWPORTA_DDR_OFFS 0x00000004
+#define GPIO_SWPORTA_DDR(base) ((base) + GPIO_SWPORTA_DDR_OFFS)
+#define GPIO_EXT_PORTA_OFFS 0x00000050
+#define GPIO_EXT_PORTA(base) ((base) + GPIO_EXT_PORTA_OFFS)
diff --git a/board/micronas/vct/vctv/reg_wdt.h b/board/micronas/vct/vctv/reg_wdt.h
new file mode 100644
index 0000000..04842e5
--- /dev/null
+++ b/board/micronas/vct/vctv/reg_wdt.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define WDT_BASE 0x00040000
+#define WDT_CR_OFFS 0x00000000
+#define WDT_CR(base) ((base) + WDT_CR_OFFS)
+#define WDT_TORR_OFFS 0x00000004
+#define WDT_TORR(base) ((base) + WDT_TORR_OFFS)
diff --git a/include/configs/vct.h b/include/configs/vct.h
new file mode 100644
index 0000000..5ef88ec
--- /dev/null
+++ b/include/configs/vct.h
@@ -0,0 +1,310 @@
+/*
+ * (C) Copyright 2008 Stefan Roese <sr at denx.de>, DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for the VCT board
+ * family:
+ *
+ * vct_premium
+ * vct_premium_small
+ * vct_premium_onenand
+ * vct_premium_onenand_small
+ * vct_platinum
+ * vct_platinum_small
+ * vct_platinum_onenand
+ * vct_platinum_onenand_small
+ * vct_platinumavc
+ * vct_platinumavc_small
+ * vct_platinumavc_onenand
+ * vct_platinumavc_onenand_small
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */
+#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_STACKSIZE (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (1 << 20)
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10)
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND)
+#define CONFIG_VCT_NOR
+#else
+#define CONFIG_SYS_NO_FLASH
+#endif
+
+/*
+ * UART
+ */
+#define CONFIG_VCT_SERIAL
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * SDRAM
+ */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_MBYTES_SDRAM 128
+#define CONFIG_SYS_MEMTEST_START 0x80200000
+#define CONFIG_SYS_MEMTEST_END 0x80400000
+#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
+
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+/*
+ * SMSC91C11x Network Card
+ */
+#define CONFIG_DRIVER_SMC911X
+#define CONFIG_DRIVER_SMC911X_BASE 0x00000000
+#define CONFIG_DRIVER_SMC911X_32_BIT
+#define CONFIG_NET_RETRY_COUNT 20
+#endif
+
+/*
+ * Commands
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+
+/*
+ * Only Premium/Platinum have ethernet support right now
+ */
+#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM)
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SNTP
+#else
+#undef CONFIG_CMD_NET
+#endif
+
+#if !defined(CONFIG_VCT_NOR)
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
+#if defined(CONFIG_VCT_NAND)
+#define CONFIG_CMD_NAND
+#endif
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_CMD_ONENAND
+#endif
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "VCT# " /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#define CONFIG_CMDLINE_EDITING /* add command line history */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+
+/*
+ * FLASH and environment organization
+ */
+#if defined(CONFIG_VCT_NOR)
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_FLASH_NOT_MEM_MAPPED
+
+/*
+ * We need special accessor functions for the CFI FLASH driver. This
+ * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option.
+ */
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+
+/*
+ * For the non-memory-mapped NOR FLASH, we need to define the
+ * NOR FLASH area. This can't be detected via the addr2info()
+ * function, since we check for flash access in the very early
+ * U-Boot code, before the NOR FLASH is detected.
+ */
+#define CONFIG_FLASH_BASE 0xb0000000
+#define CONFIG_FLASH_END 0xbfffffff
+
+/*
+ * CFI driver settings
+ */
+#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */
+
+#define CONFIG_SYS_FLASH_BASE 0xb0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#ifdef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+#endif /* CONFIG_ENV_IS_IN_FLASH */
+#endif /* CONFIG_VCT_NOR */
+
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_ENV_IS_IN_ONENAND
+#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */
+#define CONFIG_SYS_FLASH_BASE 0x00000000
+#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */
+#define CONFIG_ENV_SIZE (128 << 10) /* erase size */
+#endif /* CONFIG_VCT_ONENAND */
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * I2C/EEPROM
+ */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C /* I2C bit-banged */
+
+#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define CONFIG_SYS_GPIO_I2C_SCL 11
+#define CONFIG_SYS_GPIO_I2C_SDA 10
+
+#ifndef __ASSEMBLY__
+int vct_gpio_dir(int pin, int dir);
+void vct_gpio_set(int pin, int val);
+int vct_gpio_get(int pin);
+#endif
+
+#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1)
+#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1)
+#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0)
+#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA)
+#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit)
+#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit)
+#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
+
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
+/* CAT24WC32 */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
+ /* 32 byte page write mode using*/
+ /* last 5 bits of the address */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
+
+#define CONFIG_BOOTCOMMAND "run test3"
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+/*
+ * Needed for 64bit printf format
+ */
+#define CONFIG_SYS_64BIT_VSPRINTF 1
+#define CONFIG_SYS_64BIT_STRTOUL 1
+
+/*
+ * UBI configuration
+ */
+#if defined(CONFIG_VCT_ONENAND)
+#define CONFIG_SYS_USE_UBI
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_JFFS2_CMDLINE
+
+#define MTDIDS_DEFAULT "onenand0=onenand"
+#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \
+ "128k(env)," \
+ "20m(kernel)," \
+ "-(rootfs)"
+#endif
+
+/*
+ * We need a small, stripped down image to fit into the first 128k OneNAND
+ * erase block (gzipped). This image only needs basic commands for FLASH
+ * (NOR/OneNAND) usage and Linux kernel booting.
+ */
+#if defined(CONFIG_VCT_SMALL_IMAGE)
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_PING
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_CONSOLE
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_IRQ
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_MISC
+#undef CONFIG_CMD_REGINFO
+#undef CONFIG_CMD_STRINGS
+#undef CONFIG_CMD_TERMINAL
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_CMD_DHCP
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_LOADY
+#undef CONFIG_CMD_BDI
+
+#undef CONFIG_DRIVER_SMC911X
+#undef CONFIG_SOFT_I2C
+#undef CONFIG_AUTOSCRIPT
+#undef CONFIG_SYS_LONGHELP
+#undef CONFIG_TIMESTAMP
+#endif /* CONFIG_VCT_SMALL_IMAGE */
+
+#endif /* __CONFIG_H */
--
1.6.1
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