[U-Boot] [PATCH 1/1] at91rm9200: move define from lowlevel_init to header

[1229547702-20400-2-git-send-email-plagnioj at jcrosoft.com]

From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj at jcrosoft.com>
---
 cpu/arm920t/at91rm9200/lowlevel_init.S       |   70 ++++++++------------------
 include/asm-arm/arch-at91rm9200/AT91RM9200.h |   27 ++++++++++
 2 files changed, 49 insertions(+), 48 deletions(-)

diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 736f1ea..0913284 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -38,33 +38,7 @@
  * turn is based on the boot.bin code from ATMEL
  *
  */
-
-/* flash */
-#define MC_PUIA		0xFFFFFF10
-#define MC_PUP		0xFFFFFF50
-#define MC_PUER		0xFFFFFF54
-#define MC_ASR		0xFFFFFF04
-#define MC_AASR		0xFFFFFF08
-#define EBI_CFGR	0xFFFFFF64
-#define SMC_CSR0	0xFFFFFF70
-
-/* clocks */
-#define PLLAR		0xFFFFFC28
-#define PLLBR		0xFFFFFC2C
-#define MCKR		0xFFFFFC30
-
-#define AT91C_BASE_CKGR 0xFFFFFC20
-#define CKGR_MOR 0
-
-/* sdram */
-#define PIOC_ASR	0xFFFFF870
-#define PIOC_BSR	0xFFFFF874
-#define PIOC_PDR	0xFFFFF804
-#define EBI_CSA		0xFFFFFF60
-#define SDRC_CR		0xFFFFFF98
-#define SDRC_MR		0xFFFFFF90
-#define SDRC_TR		0xFFFFFF94
-
+#include <asm/arch/AT91RM9200.h>
 
 _MTEXT_BASE:
 #undef START_FROM_MEM
@@ -84,7 +58,7 @@ lowlevel_init:
 #else
 	ldr     r0, =0x0000FF00		/* Disable main oscillator, OSCOUNT = 0xFF */
 #endif
-	str     r0, [r1, #CKGR_MOR]
+	str     r0, [r1, #AT91C_CKGR_MOR]
 	/* Add loop to compensate Main Oscillator startup time */
 	ldr     r0, =0x00000010
 LoopOsc:
@@ -134,44 +108,44 @@ LoopOsc:
 	.ltorg
 
 SMRDATA:
-	.word MC_PUIA
+	.word AT91C_MC_PUIA
 	.word CONFIG_SYS_MC_PUIA_VAL
-	.word MC_PUP
+	.word AT91C_MC_PUP
 	.word CONFIG_SYS_MC_PUP_VAL
-	.word MC_PUER
+	.word AT91C_MC_PUER
 	.word CONFIG_SYS_MC_PUER_VAL
-	.word MC_ASR
+	.word AT91C_MC_ASR
 	.word CONFIG_SYS_MC_ASR_VAL
-	.word MC_AASR
+	.word AT91C_MC_AASR
 	.word CONFIG_SYS_MC_AASR_VAL
-	.word EBI_CFGR
+	.word AT91C_EBI_CFGR
 	.word CONFIG_SYS_EBI_CFGR_VAL
-	.word SMC_CSR0
+	.word AT91C_SMC_CSR0
 	.word CONFIG_SYS_SMC_CSR0_VAL
-	.word PLLAR
+	.word AT91C_PLLAR
 	.word CONFIG_SYS_PLLAR_VAL
-	.word PLLBR
+	.word AT91C_PLLBR
 	.word CONFIG_SYS_PLLBR_VAL
-	.word MCKR
+	.word AT91C_MCKR
 	.word CONFIG_SYS_MCKR_VAL
 	/* SMRDATA is 80 bytes long */
 	/* here there's a delay of 100 */
 SMRDATA1:
-	.word PIOC_ASR
+	.word AT91C_PIOC_ASR
 	.word CONFIG_SYS_PIOC_ASR_VAL
-	.word PIOC_BSR
+	.word AT91C_PIOC_BSR
 	.word CONFIG_SYS_PIOC_BSR_VAL
-	.word PIOC_PDR
+	.word AT91C_PIOC_PDR
 	.word CONFIG_SYS_PIOC_PDR_VAL
-	.word EBI_CSA
+	.word AT91C_EBI_CSA
 	.word CONFIG_SYS_EBI_CSA_VAL
-	.word SDRC_CR
+	.word AT91C_SDRC_CR
 	.word CONFIG_SYS_SDRC_CR_VAL
-	.word SDRC_MR
+	.word AT91C_SDRC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL
 	.word CONFIG_SYS_SDRAM
 	.word CONFIG_SYS_SDRAM_VAL
-	.word SDRC_MR
+	.word AT91C_SDRC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL1
 	.word CONFIG_SYS_SDRAM
 	.word CONFIG_SYS_SDRAM_VAL
@@ -189,15 +163,15 @@ SMRDATA1:
 	.word CONFIG_SYS_SDRAM_VAL
 	.word CONFIG_SYS_SDRAM
 	.word CONFIG_SYS_SDRAM_VAL
-	.word SDRC_MR
+	.word AT91C_SDRC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL2
 	.word CONFIG_SYS_SDRAM1
 	.word CONFIG_SYS_SDRAM_VAL
-	.word SDRC_TR
+	.word AT91C_SDRC_TR
 	.word CONFIG_SYS_SDRC_TR_VAL
 	.word CONFIG_SYS_SDRAM
 	.word CONFIG_SYS_SDRAM_VAL
-	.word SDRC_MR
+	.word AT91C_SDRC_MR
 	.word CONFIG_SYS_SDRC_MR_VAL3
 	.word CONFIG_SYS_SDRAM
 	.word CONFIG_SYS_SDRAM_VAL
diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 95db017..00bae1c 100644
--- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h
+++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
@@ -781,5 +781,32 @@ typedef struct _AT91S_PDC
 #define AT91C_PIOB_ODR		((AT91_REG *)	0xFFFFF614) /* (PIOB) Output Disable Registerr */
 #define AT91C_PIOB_PDSR		((AT91_REG *)	0xFFFFF63C) /* (PIOB) Pin Data Status Register */
 
+#else
+/* flash */
+#define AT91C_MC_PUIA		0xFFFFFF10
+#define AT91C_MC_PUP		0xFFFFFF50
+#define AT91C_MC_PUER		0xFFFFFF54
+#define AT91C_MC_ASR		0xFFFFFF04
+#define AT91C_MC_AASR		0xFFFFFF08
+#define AT91C_EBI_CFGR		0xFFFFFF64
+#define AT91C_SMC_CSR0		0xFFFFFF70
+
+/* clocks */
+#define AT91C_PLLAR		0xFFFFFC28
+#define AT91C_PLLBR		0xFFFFFC2C
+#define AT91C_MCKR		0xFFFFFC30
+
+#define AT91C_BASE_CKGR		0xFFFFFC20
+#define AT91C_CKGR_MOR		0
+
+/* sdram */
+#define AT91C_PIOC_ASR		0xFFFFF870
+#define AT91C_PIOC_BSR		0xFFFFF874
+#define AT91C_PIOC_PDR		0xFFFFF804
+#define AT91C_EBI_CSA		0xFFFFFF60
+#define AT91C_SDRC_CR		0xFFFFFF98
+#define AT91C_SDRC_MR		0xFFFFFF90
+#define AT91C_SDRC_TR		0xFFFFFF94
+
 #endif /* __ASSEMBLY__ */
 #endif /* AT91RM9200_H */
-- 
1.5.6.5