[U-Boot] ppc440 (440EPx sequoia) - inhibiting the cpu cache?

[Stefan Roese]

Hi Jonathan,

On Thursday 08 January 2009, Jonathan Barrow wrote:
> I'm in the process of bringing up a custom board featuring AMCC's
> 440EPx processor.  I'm using the uboot-2008-10 source tree and
> "sequoia" board for my starting configuration, also using ELDK v4.2.
> for cross-compiler tools and such.
>
> Although my board initializes and completes its memory tests
> "relocate_code" fails.  I've noted in the FAQ and mailing lists the
> sensitive nature of sdram timing and have spent considerable effort
> making sure the ddr_xx settings are correct.  I thought my latest
> adjustment would save the day,  I realized 'BSTLEN' should likely be
> changed from 4 words to 8 words because my memory configuration is x32
> not x64.  Unfortunately my latest u-boot.bin is still not happy.
>
> To be really really certain my problem lies elsewhere, for the
> purposes of hardware bringup  I was wondering if there was a
> relatively easy way to inhibit memory bursts, by turning off the CPU
> Cache.   I searched many of the the .h files and didnt' notice
> anything along the lines of EN or DISABLE the cache,  only size
> adjustments and associations to Chip Selects.

Usually caches are disabled on 44x platforms in U-Boot. So you shouldn't see 
any burst access to SDRAM anyway.

> If I overlooked 
> something I'd would really appreciate a tip on strategy getting past
> relocate_code.  This is what I have so far:

Most likely still an SDRAM configuration problem. Did you check if SDRAM is 
working after initialization either using a debugger or by using some simple 
memory test (write value to SDRAM and read it back and print the result)? 
This is what I would recommend to do. Only if this works you can continue to 
run U-Boot from RAM.

Best regards,
Stefan

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