[U-Boot] U-Boot-v2009.01-rc2 w90p710 ARM support PATCH
Vovk Konstantin
ksl at kslemb.com
Fri Jan 16 17:52:07 CET 2009
This patch will add W90P710 ARM7 SoC to u-boot-v2009-rc2.
Best regards
Konstantin Vovk
KSL Embdedded Ltd
www.kslemb.com
w90p710-v2009.01-rc2.diff:
Size: 92K
diff -Naur u-boot/board/w90p1/config.mk u-boot-patched/board/w90p1/config.mk
--- u-boot/board/w90p1/config.mk 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/config.mk 2009-01-15 11:10:10.000000000 +0200
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2008 KSL Embedded (http://www.kslemb.com)
+# Vovk Konstantin <ksl at kslemb.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x01FC0000
diff -Naur u-boot/board/w90p1/ide.c u-boot-patched/board/w90p1/ide.c
--- u-boot/board/w90p1/ide.c 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/ide.c 2009-01-15 11:10:10.000000000 +0200
@@ -0,0 +1,112 @@
+/*
+ * (C) Copyright 2008
+ * Vovk Konstantin, KSL Embedded, ksl at kslemb.com
+ *
+ * IDE interface for Winbond W90P710 ARM7 SoC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+#if defined(CONFIG_CMD_IDE)
+#include <ata.h>
+#include <ide.h>
+
+/* Define the start address of the IDE_CS0 region (0x73000000 but we wr/rd
to the 0xF3000000 for disable internal cache memory MSB=1) */
+#define EXT1_BASE 0xF3000000 /* Start Address for IDE CS0 - mapped to
the EBI ECS1 */
+/* Define the start address of the IDE_CS1 region (0x74000000 but we wr/rd
to the 0xF4000000 for disable internal cache memory MSB=1) */
+#define EXT2_BASE 0xF4000000 /* Start Address for IDE CS1 - mapped to
the EBI ECS2 */
+
+/* Config bits for ECS1 and ECS2 */
+
+#define SIZE_256k (0<<16) /* Memory size is 256K */
+#define SIZE_512k (1<<16) /* Memory size is 512K */
+#define SIZE_1M (2<<16) /* Memory size is 1M */
+#define SIZE_16M (6<<16) /* Memory size is 16M */
+#define SIZE_32M (7<<16) /* Memory size is 32M */
+
+#define ADRS (1<<15)
+#define tACC (15<<11) /* Access cycles of external I/O bank
*/
+#define tCOH (7<<8) /* Chip selection hold time of external I/O
bank */
+#define tACS (7<<5) /* Address set-up before nECS of external I/O
bank*/
+#define tCOS (7<<2) /* Chip selection setup time of external I/O
bank */
+
+#define BUS16 (2) /* 16-bit bus width for IDE */
+#define BUS08 (1) /* 8-bit bus width for IDE */
+
+// IDE_CS0 with 16bit data bus
+#define ENABLE16() PUT_REG(REG_EXT1CON,
((EXT1_BASE<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|BUS16))
+// IDE_CS0 with 8bit data bus
+#define DISABLE16() PUT_REG(REG_EXT1CON,
((EXT1_BASE<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|BUS08))
+
+
+void outb(unsigned char val, volatile unsigned char *addr)
+{
+ *(addr) = val;
+}
+
+unsigned char inb(volatile unsigned char *addr)
+{
+ volatile unsigned char c;
+
+ c = *(addr);
+ return c;
+}
+
+/* IDE work with Data Port via 16-bit BUS that's why we must first of all /
+ * enable 16-bit bus on ECS1, read/write data to the Data Port, and finaly
+ disable 16-bit wide data bus
+ */
+void insw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ ENABLE16();
+ for (i = 0; i < words; i++)
+ *(sect_buf + i) = *(addr);
+ DISABLE16();
+}
+
+void outsw(unsigned short *addr, unsigned short *sect_buf, int words)
+{
+ int i;
+
+ ENABLE16();
+ for (i = 0; i < words; i++)
+ *(addr) = *(sect_buf + i);
+ DISABLE16();
+}
+
+
+int ide_preinit (void)
+{
+ /* Init IDE_CS0 with 8bit data bus */
+ PUT_REG(REG_EXT1CON,
((EXT1_BASE<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|BUS08));
+ /* Init IDE_CS1 with 8bit data bus */
+ PUT_REG(REG_EXT2CON,
((EXT2_BASE<<1)|SIZE_256k|ADRS|tACC|tCOH|tACS|tCOS|BUS08));
+ /* Enable nWE as a write strob for ECS1 and ECS2 */
+ PUT_REG(REG_EBICON, GET_REG(REG_EBICON) | (1<<25) | (1<<26));
+
+ return 0;
+}
+
+#endif
diff -Naur u-boot/board/w90p1/led.c u-boot-patched/board/w90p1/led.c
--- u-boot/board/w90p1/led.c 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/led.c 2009-01-15 11:10:10.000000000 +0200
@@ -0,0 +1,63 @@
+/***********************************************************************
+ * (C) Copyright 2008
+ * Vovk Konstantin, KSL Embedded, ksl at kslemb.com
+ *
+ * Defines helper functions for toggeling LEDs
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ ***********************************************************************/
+#include <common.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_STATUS_LED
+
+#include <status_led.h>
+
+void __led_init( led_id_t mask, int state )
+{
+ unsigned int *dir = (unsigned int *)STATUS_LED_DIR;
+ unsigned int *port = (unsigned int *)STATUS_LED_PORT;
+
+ *dir = mask;
+
+ if (state == STATUS_LED_ON)
+ *port &= ~mask;
+ else
+ *port |= mask;
+}
+
+void __led_toggle( led_id_t mask )
+{
+ unsigned int *port = (unsigned int *)STATUS_LED_PORT;
+ unsigned int val;
+
+ val = *port;
+ val ^= mask;
+ *port = val;
+}
+
+void __led_set( led_id_t mask, int state )
+{
+ unsigned int *port = (unsigned int *)STATUS_LED_PORT;
+
+ if (state == STATUS_LED_ON)
+ *port &= ~mask;
+ else
+ *port |= mask;
+}
+
+#endif /* CONFIG_STATUS_LED */
diff -Naur u-boot/board/w90p1/lowlevel_init.S
u-boot-patched/board/w90p1/lowlevel_init.S
--- u-boot/board/w90p1/lowlevel_init.S 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/lowlevel_init.S 2009-01-16 02:26:51.000000000
+0200
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2008 KSL Embedded Ltd (http://www.kslemb.com)
+ * by Vovk Konstantin <ksl at kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM. After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000. After lowlevel_init completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ * to 32MB on board SDRAM via DD6 and DD7
+ * 0x02000000
+ *
+ * 0x7F000000
+ * to 2MB(16Bit) on board Flash M29W320ET via DD8
+ * 0x7F200000
+ *
+ *
+ * Load all 6 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written. The
+ * last register written re-enables memory access.
+ ***********************************************************************/
+
+#define CKSKEW 0xFFF01F00 /* Clock Skew Control register */
+
+
+.globl lowlevel_init
+lowlevel_init:
+
+ /* Check version number of W90P710 to set the clock skew
+ The clock skew of W90P710 ver A = 0x7A
+ The clock skew of W90P710 ver B = 0x39
+ */
+ LDR r0, =REG_PDID
+ LDR r0, [r0]
+ LDR r1, =0x0F000000
+ ANDS r0,r0,r1
+ BEQ ver0
+ LDR r1, =0x01000000
+ CMP r0, r1
+ BEQ ver1
+ B unknow_version
+ver0:
+ LDR r0, =0x0FF007A
+ B skew_update
+ver1:
+ LDR r0, =0x0FF0039
+skew_update:
+ LDR r1, =CKSKEW
+ STR r0,[r1]
+unknow_version:
+ /* Nothing to do */
+
+
+ /* preserve the temp register (r12 AKA ip) and remap it. */
+ LDR r1, =SRAM_BASE+0xC
+ ADD r0, r12, #CONFIG_SYS_FLASH_BASE
+ STR r0, [r1]
+
+ /* remap the link register for when we return */
+ ADD lr, lr, #CONFIG_SYS_FLASH_BASE
+
+ /* store a short program in the on chip SRAM, which is
+ * unaffected when remapping memory. Note the cache must be
+ * disabled for the on chip SRAM to be available.
+ */
+ LDR r1, =SRAM_BASE
+ LDR r0, =0xe880007e /* stmia r0, {r1-r6} - write init values to EBICON,
ROMCON, SDCONF0, SDCONF1, SDTIME0, SDTIME1*/
+ STR r0, [r1]
+ ADD r1, r1, #4
+ LDR r0, =0xe59fc000 /* ldr r12, [pc, #0] - restore remaped ip */
+ STR r0, [r1]
+ ADD r1, r1, #4
+ LDR r0, =0xe1a0f00e /* mov pc, lr - return from branch */
+ STR r0, [r1]
+
+ ADR r0, InitData /* Load start address of the Init data */
+ LDMIA r0, {r1-r6} /* Load six bytes of the Init data to the registers
r1...r6*/
+
+ LDR r0, =REG_EBICON /* Load the address of the EBICON register */
+ LDR pc, =SRAM_BASE /* execute relocation programm */
+
+.globl reset_cpu
+reset_cpu:
+
+ LDR r1, =REG_CLKSEL /* Set RESET bit in CLKSEL register */
+ LDR r0, =0x01
+ STR r0, [r1]
+
+wait_loop:
+ b wait_loop
+
+ /* never return */
+
+/************************************************************************
+ * Below are six 32-bit values for the six memory registers of
+ * the system manager, starting with register EBICON
+ ***********************************************************************/
+
+ InitData:
+ /* Default configuration */
+ .long 0x000530C0 /* EBICON : not need to change.
*/
+ .long 0xFE040080 /* ROMCON(Flash) - M29W320ET
*/
+ .long 0x000090ED /* SDCONF0(SDRAM) - 32M(16Mx16x2): 0x000090ED
*/
+ .long 0x00000000 /* SDCONF1 - The same as SDCONF0 with proper
base address*/
+ .long 0x0000014B /* SDTIME0 - not need to change
*/
+ .long 0x0000014B /* SDTIME1 - not need to change
*/
+
+
+
+
+
diff -Naur u-boot/board/w90p1/Makefile u-boot-patched/board/w90p1/Makefile
--- u-boot/board/w90p1/Makefile 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/Makefile 2009-01-16 15:04:52.000000000 +0200
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := $(BOARD).o
+COBJS-$(CONFIG_CMD_NAND) += nand.o
+COBJS-$(CONFIG_CMD_IDE) += ide.o
+COBJS-$(CONFIG_STATUS_LED) += led.o
+
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+#########################################################################
diff -Naur u-boot/board/w90p1/nand.c u-boot-patched/board/w90p1/nand.c
--- u-boot/board/w90p1/nand.c 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/nand.c 2009-01-16 15:06:59.000000000 +0200
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2008
+ * KSL Embedded Development Team <www.kslemb.com>
+ * Vovk Konstantin <ksl at kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+
+ Date Version Description
+ 16.01.2009 v1.1 Updated w90p710_nand_hwcontrol function.
+ for support new U-Boot 2009.01-rc1
+ */
+#include <asm/io.h>
+#include <common.h>
+#include <asm/hardware.h>
+
+#if defined(CONFIG_CMD_NAND)
+
+#include <nand.h>
+
+/* W90P710 EBI Config bits */
+#define SIZE_256k (0<<16) /* Memory size is 256K */
+#define SIZE_512k (1<<16) /* Memory size is 512K */
+#define SIZE_1M (2<<16) /* Memory size is 1M */
+#define SIZE_16M (6<<16) /* Memory size is 16M */
+#define SIZE_32M (7<<16) /* Memory size is 32M */
+
+#define ADRS (1<<15) /* Bus alignment to the byte address format
*/
+#define tACC (7<<11) /* Access cycles of external I/O bank
*/
+#define tCOH (7<<8) /* Chip selection hold time of external I/O
bank */
+#define tACS (7<<5) /* Address set-up before nECS of external
I/O bank */
+#define tCOS (7<<2) /* Chip selection setup time of external I/O
bank */
+#define BUS08 (1) /* Bus is 8 bit wide
*/
+
+/* Define the start address of the CS0 region (0x72000000 but we wr/rd to
the 0xF2000000 for disable internal cache memory) */
+#define EXT0_BASE 0xF2000000
+
+/* Hardware specific access to control-lines */
+
+void w90p710_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
ctrl)
+{
+ struct nand_chip *this = mtd->priv;
+ ulong base = (ulong) this->IO_ADDR_W;
+
+ if (ctrl & NAND_CTRL_CHANGE)
+ {
+ if (ctrl & NAND_CLE)
+ base = (base | W90P710_NAND_CLE);
+ else
+ base = (base & ~W90P710_NAND_CLE);
+ if (ctrl & NAND_ALE)
+ base = (base | W90P710_NAND_ALE);
+ else
+ base = (base & ~W90P710_NAND_ALE);
+
+ this->IO_ADDR_W = (void __iomem *) ( base );
+ }
+
+ this->IO_ADDR_R = this->IO_ADDR_W;
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+}
+
+/* We use nWait pin that's why we don't think abot ready */
+int w90p710_nand_ready(struct mtd_info *mtd)
+{
+ return 1;
+}
+
+/*
+ * Board-specific NAND initialization.
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+ /* Init CS0 with 8bit data bus 16M bank space (we use A21 for ALE and A20
CLE) */
+ PUT_REG(REG_EXT0CON,
((EXT0_BASE<<1)|SIZE_16M|ADRS|tACC|tCOH|tACS|tCOS|BUS08));
+ /* Enable nWE as a write strob for CS0 */
+ PUT_REG(REG_EBICON, GET_REG(REG_EBICON) | (1<<24));
+
+ nand->cmd_ctrl = w90p710_nand_hwcontrol;
+ nand->ecc.mode = NAND_ECC_SOFT;
+ nand->dev_ready = w90p710_nand_ready;
+ nand->chip_delay = 30;
+
+ return 0;
+}
+#endif
diff -Naur u-boot/board/w90p1/u-boot.lds
u-boot-patched/board/w90p1/u-boot.lds
--- u-boot/board/w90p1/u-boot.lds 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/u-boot.lds 2009-01-16 15:07:30.000000000
+0200
@@ -0,0 +1,69 @@
+/*
+ * (C) Copyright 2000-2007
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm720t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss (NOLOAD) : { *(.bss) }
+ _end = .;
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
diff -Naur u-boot/board/w90p1/w90p1.c u-boot-patched/board/w90p1/w90p1.c
--- u-boot/board/w90p1/w90p1.c 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/board/w90p1/w90p1.c 2009-01-16 01:29:43.000000000 +0200
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2008
+ * KSL Embedded Development Team <www.kslemb.com>
+ * Vovk Konstantin <ksl at kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#ifdef CONFIG_DRIVER_W90P710_ETH
+#include <net.h>
+#include <netdev.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+#define MACH_W90X700 1861
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+int board_init (void)
+{
+ /* arch number MACH_TYPE_W90P710 */
+ gd->bd->bi_arch_number = MACH_W90X700;
+
+ /* location of boot parameters */
+ gd->bd->bi_boot_params = 0x00000800;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ #if CONFIG_NR_DRAM_BANKS == 2
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+ #endif
+
+ return (0);
+}
+
+#if defined(CONFIG_DRIVER_W90P710_ETH)
+int board_eth_init(bd_t *bis)
+{
+ return W90P710_EMC_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+ PHY_Reset();
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+#ifdef CONFIG_CMD_IDE
+extern int ide_preinit (void);
+ /* Init ECS1 and ECS2 for working with memory mapped IDE */
+ ide_preinit ();
+#endif
+ return 0;
+}
+#endif
diff -Naur u-boot/cpu/arm720t/cpu.c u-boot-patched/cpu/arm720t/cpu.c
--- u-boot/cpu/arm720t/cpu.c 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/cpu/arm720t/cpu.c 2009-01-15 11:10:10.000000000 +0200
@@ -73,7 +73,7 @@
/* go to high speed */
IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
#endif
-#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) ||
defined(CONFIG_LPC2292)
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) ||
defined(CONFIG_LPC2292) || defined(CONFIG_W90P710)
disable_interrupts ();
/* Nothing more needed */
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
@@ -253,6 +253,50 @@
{
}
#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */
+
+#elif defined(CONFIG_W90P710)
+void icache_enable (void)
+{
+ PUT_REG(REG_CAHCON, 0x05); /* Flush I-cache */
+ while(GET_REG(REG_CAHCON)); /* Wait for operation
progress */
+
+ PUT_REG(REG_CAHCNF, 0x01); /* Enable I-CACHE */
+}
+
+void icache_disable (void)
+{
+ PUT_REG(REG_CAHCON, 0x05); /* Flush I-cache */
+ while(GET_REG(REG_CAHCON)); /* Wait for operation
progress */
+
+ PUT_REG(REG_CAHCNF, GET_REG(REG_CAHCNF)&(~0x01)); /* Disable I-cache */
+}
+
+int icache_status (void)
+{
+ return (GET_REG(REG_CAHCNF) & 0x01)!=0; /* Check if I-Cache enable */
+}
+
+void dcache_enable (void)
+{
+ PUT_REG(REG_CAHCON, 0x06); /* Flush D-cache */
+ while(GET_REG(REG_CAHCON)); /* Wait for operation
progress */
+
+ PUT_REG(REG_CAHCNF, GET_REG(REG_CAHCNF)|0x02); /* Enable D-CACHE */
+}
+
+void dcache_disable (void)
+{
+ PUT_REG(REG_CAHCON, 0x06); /* Flush D-cache */
+ while(GET_REG(REG_CAHCON)); /* Wait for operation
progress */
+
+ PUT_REG(REG_CAHCNF, GET_REG(REG_CAHCNF)&(~0x02)); /* Disable
D-cache */
+}
+
+int dcache_status (void)
+{
+ return (GET_REG(REG_CAHCNF) & 0x02)!=0; /* Check if D-Cache enable */
+}
+
#else
#error No icache/dcache enable/disable functions defined for this CPU type
#endif
diff -Naur u-boot/cpu/arm720t/interrupts.c
u-boot-patched/cpu/arm720t/interrupts.c
--- u-boot/cpu/arm720t/interrupts.c 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/cpu/arm720t/interrupts.c 2009-01-16 15:45:07.000000000
+0200
@@ -50,6 +50,13 @@
#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
#endif
+#ifdef CONFIG_W90P710
+ #undef TIMER_LOAD_VAL
+ #define TIMER_LOAD_VAL (0x00FFFFFF) /* We have the 24-bit timer - set
maximum value*/
+ #undef READ_TIMER
+ #define READ_TIMER (GET_REG(REG_TDR0) & 0xFFFFFF)
+#endif
+
#ifdef CONFIG_S3C4510B
/* require interrupts for the S3C4510B */
# ifndef CONFIG_USE_IRQ
@@ -80,6 +87,8 @@
pfnct = (void (*)(void))VICVectAddr;
(*pfnct)();
+#elif defined(CONFIG_W90P710)
+ /* No do_irq() for W90P710 as yet */
#else
#error do_irq() not defined for this CPU type
#endif
@@ -186,6 +195,23 @@
PUT32(T0TC, 0);
PUT32(T0TCR, 1); /* enable timer0 */
+#elif defined(CONFIG_W90P710)
+ /*Stop Timer0*/
+ PUT_REG(REG_TCR0, 0x00000000);
+
+ /* Enable Timer clock */
+ PUT_REG(REG_CLKSEL, GET_REG(REG_CLKSEL)|0x40);
+
+ /* Set Timer0 reload value*/
+ PUT_REG(REG_TICR0, (TIMER_LOAD_VAL));
+
+ /* Save to lastdec value that we load to the timer*/
+ lastdec = TIMER_LOAD_VAL;
+
+ /* CEN=1 - Timer0 Start counting, MODE = 01 - Timer0 is operat in pereodic
mode */
+ /* IE = 0 - Disable Timer0 interrupt Prescaler=0x0E Timer clock is
15000000/(14+1)=1Mhz*/
+ PUT_REG(REG_TCR0,0x4800000E);
+
#else
#error No interrupt_init() defined for this CPU type
#endif
@@ -305,6 +331,80 @@
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No timer routines for IntegratorAP/CM720T as yet */
+
+#elif defined(CONFIG_W90P710)
+/* We have Timer0 decrement frequency 1MHz that's why timestamp is in uS
+ Some problems may arise in the program, when it works more than one hour
and twenty minutes
+ (32bit vlue in uS).During this time, a variable 'timestamp' can be
overcrowded and cleared,
+ but previous timestamp value can be very large. In this case wait
function will be 'wait'
+ the next overflow. This bug will be removed in next port. Sorry for
inconvenience :-)
+*/
+void reset_timer (void)
+{
+ reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+ ulong timestamp_in_us;
+
+ /* Get timestamp in uS*/
+ timestamp_in_us = get_timer_masked ();
+
+ /* Convert timestamp in mS and subtract base*/
+ return timestamp_in_us/1000 - base;
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+void reset_timer_masked (void)
+{
+ /* reset time */
+ lastdec = READ_TIMER;
+ timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+ ulong now = READ_TIMER;
+
+ if (lastdec >= now) /* normal mode */
+ {
+ timestamp += (lastdec - now);
+ }
+ else /* we have an overflow ... */
+ {
+ timestamp += (lastdec + TIMER_LOAD_VAL - now);
+ }
+ lastdec = now;
+
+ return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+ ulong endtime;
+ signed long diff;
+
+ endtime = get_timer_masked () + usec;
+ do
+ {
+ ulong now = get_timer_masked ();
+ diff = endtime - now;
+ } while (diff >= 0);
+}
+
+
+void udelay (unsigned long usec)
+{
+ udelay_masked (usec);
+}
+
+
+
#else
#error Timer routines not defined for this CPU type
#endif
diff -Naur u-boot/cpu/arm720t/serial.c u-boot-patched/cpu/arm720t/serial.c
--- u-boot/cpu/arm720t/serial.c 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/cpu/arm720t/serial.c 2009-01-15 11:10:10.000000000 +0200
@@ -199,4 +199,116 @@
return (GET8(U0LSR) & 1);
}
+#elif defined(CONFIG_W90P710)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#include <asm/arch/hardware.h>
+
+void serial_setbrg (void)
+{
+ unsigned int divider = 0;
+
+ /* use values for 15Mhz quarts */
+ switch (gd->baudrate)
+ {
+ case 1200: divider = 779; break;
+ case 2400: divider = 389; break;
+ case 4800: divider = 193; break;
+ case 9600: divider = 96; break;
+ case 14400: divider = 65; break;
+ case 19200: divider = 47; break;
+ case 38400: divider = 22; break;
+ case 57600: divider = 14; break;
+ case 115200: divider = 6; break;
+ default: hang (); break;
+ }
+
+
+ /* Reset LCR register and disable Uart interrupt*/
+ PUT_REG(REG_UART0_LCR, 0x0);
+ PUT_REG(REG_UART0_IER, 0x0);
+
+ /* Set baud rate to mentioned in divider */
+ PUT_REG(REG_UART0_LCR, GET_REG(REG_UART0_LCR)|(1<<7)); /* Set DLAB
to '1' to access Divisor */
+ PUT_REG(REG_UART0_LSB, (divider & 0xFF));
+ PUT_REG(REG_UART0_MSB, ((divider>>8) & 0xFF));
+ PUT_REG(REG_UART0_LCR, GET_REG(REG_UART0_LCR)&(~(1<<7))); /* Reset DLAB
to '0' to access RBR, THR, IER */
+
+ /* Set port parameters 8 bit, 1 stop, no parity */
+ PUT_REG(REG_UART0_LCR, GET_REG(REG_UART0_LCR)|((1<<0)|(1<<1)));
+
+ /* Set the RX FIFO trigger level t0 8 bytes, reset RX, TX FIFO, Enable
FIFO*/
+ PUT_REG(REG_UART0_FCR, ((0x2<<6)|(1<<2)|(1<<1)|(1<<0)));
+
+ /* Reset timeout comparator */
+ PUT_REG(REG_UART0_TOR, 0x0);
+
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit.
+ *
+ */
+int serial_init (void)
+{
+ unsigned int Temp;
+
+ serial_setbrg ();
+
+/* Set GPIO_CFG to use pins PORT5_0 as TXD0 and PORT5_1 as RXD0 */
+ Temp = GET_REG(REG_GPIO_CFG5);
+ Temp|= 0X00000005;
+ Temp&= 0XFFFFFFF5;
+ PUT_REG(REG_GPIO_CFG5, Temp);
+
+ return (0);
+}
+
+/* Check for Transmitter holding register is empty */
+void CheckForUART0TXReady (void)
+{
+ unsigned int Status;
+
+ do
+ Status = GET_REG(REG_UART0_LSR);
+ while (!(Status & (1<<6))); /* Check for TE=1*/
+}
+
+/*Put one character to Uart0 TX FIFO
+ Add 'LF' after 'CR'
+*/
+void serial_putc (const char c)
+{
+ if (c == '\n')
+ {
+ CheckForUART0TXReady(); /* Wait for empty THR */
+ PUT_REG(REG_UART0_TX, '\r');
+ }
+
+ CheckForUART0TXReady(); /* Wait for empty THR */
+ PUT_REG(REG_UART0_TX, c);
+}
+
+int serial_getc (void)
+{
+ while((GET_REG(REG_UART0_LSR) & 1) == 0);
+ return GET_REG(REG_UART0_RX);
+}
+
+int serial_tstc (void)
+{
+ return (GET_REG(REG_UART0_LSR) & 1);
+}
+
+
+void serial_puts (const char *s)
+{
+ while (*s)
+ {
+ serial_putc (*s++);
+ }
+}
#endif
diff -Naur u-boot/cpu/arm720t/start.S u-boot-patched/cpu/arm720t/start.S
--- u-boot/cpu/arm720t/start.S 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/cpu/arm720t/start.S 2009-01-16 15:32:51.000000000 +0200
@@ -224,6 +224,14 @@
VPBDIV_ADR: .word VPBDIV
MEMMAP_ADR: .word MEMMAP
+#elif defined(CONFIG_W90P710)
+
+#define CAHCON 0xFFF02004 /* W90P710 Cache control register
*/
+#define AIC_MDCR 0xFFF82124 /* W90P710 AIC Mask Disable Control Register
*/
+#define CAHCNF 0xFFF02000 /* W90P710 Cache configuration register
*/
+#define IDREG 0xFFF00000 /* W90P710 CHIP ID */
+#define CKSKEW 0xFFF01F00 /* Clock Skew Control
register */
+
#endif
cpu_init_crit:
@@ -368,6 +376,23 @@
ldr r0, VPBDIV_ADR
mov r1, #0x01 /* VPB clock is same as process clock */
str r1, [r0]
+
+#elif defined(CONFIG_W90P710)
+ /* Disable Interrupt*/
+ LDR r0, =AIC_MDCR
+ LDR r1, =0x7FFFE
+ STR r1, [r0]
+
+ /*Disable FIQ and IRQ*/
+ MRS r0, CPSR
+ ORR r0, r0, #0xC0
+ MSR CPSR_c, r0
+
+ /* Disable I-Cache and D-cache entirely */
+ LDR r1,=CAHCNF
+ MOV r0, #0x0
+ STR r0, [r1]
+
#else
#error No cpu_init_crit() defined for current CPU type
#endif
@@ -606,6 +631,9 @@
.globl reset_cpu
reset_cpu:
mov pc, r0
+#elif defined(CONFIG_W90P710)
+/* Nothing done here as reseting the CPU is board specific, depending on
external peripherals see lowlevel_init.c*/
+
#else
#error No reset_cpu() defined for current CPU type
#endif
diff -Naur u-boot/drivers/net/Makefile u-boot-patched/drivers/net/Makefile
--- u-boot/drivers/net/Makefile 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/drivers/net/Makefile 2009-01-15 11:52:47.000000000 +0200
@@ -69,6 +69,7 @@
COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o
COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o
COBJS-$(CONFIG_SH_ETHER) += sh_eth.o
+COBJS-$(CONFIG_DRIVER_W90P710_ETH) += w90p710_eth.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff -Naur u-boot/drivers/net/w90p710_eth.c
u-boot-patched/drivers/net/w90p710_eth.c
--- u-boot/drivers/net/w90p710_eth.c 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/drivers/net/w90p710_eth.c 2009-01-15 11:10:41.000000000
+0200
@@ -0,0 +1,501 @@
+/***********************************************************************
+ *
+ * Copyright (c) 2008 KSL Embedded (http://www.kslemb.com)
+ * Vovk Konstantin <ksl at kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description: Ethernet interface for Winbond W90P710 SoC
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_W90P710_ETH
+
+#include <command.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/hardware.h>
+#include "w90p710_eth.h"
+
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
+
+#if 0
+#define DEBUG
+#endif
+
+#if 1
+#define DEBUG_PHY_RESET
+#endif
+
+#ifdef DEBUG
+ #define printk(fmt, args...) printf(fmt, ##args)
+#else
+ #define printk(fmt, args...)
+#endif
+
+#ifdef DEBUG_PHY_RESET
+ #define print_phy(fmt, args...) printf(fmt, ##args)
+#else
+ #define print_phy(fmt, args...)
+#endif
+
+static TX_FrameDescriptor txFDbase[ETH_MaxTxFrames];
+static MACFrame txFrameBase[ETH_MaxTxFrames];
+static RX_FrameDescriptor rxFDbase[PKTBUFSRX];
+static ETH m_eth;
+
+static s32 TxFDinit( ETH *eth)
+{
+ s32 i;
+ MACFrame *txFrmBase;
+
+ /* use non-cacheble space for access to the TX buffers */
+ txFrmBase = (MACFrame *)( (u32)txFrameBase | 0x80000000);
+
+ /* store start of Tx descriptors and set current */
+ eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | 0x80000000);
+ eth->m_baseTX_FD = eth->m_curTX_FD;
+
+ for ( i = 0; i < ETH_MaxTxFrames; i++)
+ {
+ eth->m_baseTX_FD[i].m_frameDataPtr.ui = (u32)&txFrmBase[i];
+ eth->m_baseTX_FD[i].m_opt.ui = 0; /* Clear Owner and
IntEn bits - Oner now is CPU*/
+ eth->m_baseTX_FD[i].m_opt.bf.padding = 1; /* Enable Padding
Automaticaly */
+ eth->m_baseTX_FD[i].m_opt.bf.crc_en = 1; /* Enable CRC Append
*/
+ eth->m_baseTX_FD[i].m_status.ui = 0; /* Clear status and
transmit count*/
+ eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1];
/* Point to the next descriptor */
+ }
+
+ /* make the list circular */
+ eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0];
+ /* Write Current TX Descriptor Buffer Start Address */
+ PUT_REG(REG_TXDLSA, (u32)eth->m_curTX_FD);
+
+ return 0;
+}
+
+static s32 RxFDinit( ETH *eth)
+{
+ s32 i;
+ /* MACFrame *rxFrmBase; */
+
+ /* disable cache for access to the RX buffers */
+ /* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */
+
+ /* store start of Rx descriptors and set current */
+ eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | 0x80000000);
+ eth->m_baseRX_FD = eth->m_curRX_FD;
+
+ for ( i = 0; i < PKTBUFSRX; i++)
+ {
+ eth->m_baseRX_FD[i].m_frameDataPtr.ui = (u32)NetRxPackets[i] |
0x80000000;
+ eth->m_baseRX_FD[i].m_status.ui = 0x0;
+ eth->m_baseRX_FD[i].m_status.bf.owner = 0x02; /* Owner is EMC
*/
+ eth->m_baseRX_FD[i].m_reserved = 0x0;
+ eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1];
+ }
+
+ /* make the list circular */
+ eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0];
+ /* Write Current RX Descriptor Buffer Start Address */
+ PUT_REG(REG_RXDLSA, (u32)eth->m_curRX_FD);
+
+ return 0;
+}
+
+#ifdef CONFIG_RESET_PHY_R
+
+/* Write External PHY Register */
+void PHY_Write(unsigned int PHY_Reg_Addr, unsigned int PHY_Number, unsigned
int Data)
+{
+ volatile unsigned int Check;
+
+ PUT_REG(REG_MIID, Data);
+ PUT_REG(REG_MIIDA, PHY_Reg_Addr | PHY_Number | PHYBUSY | PHYWR | MDCCR);
+
+ do
+ Check = GET_REG(REG_MIIDA);
+ while (Check & PHYBUSY);
+
+ PUT_REG(REG_MIID, 0x0);
+}
+
+/* Read External PHY Register */
+unsigned int PHY_Read(unsigned int PHY_Reg_Addr, unsigned int PHY_Number)
+{
+ unsigned int PHY_Data;
+ volatile unsigned int Check;
+
+ PUT_REG(REG_MIIDA, PHY_Reg_Addr | PHY_Number | PHYBUSY | MDCCR);
+
+ do
+ Check = GET_REG(REG_MIIDA);
+ while (Check & PHYBUSY);
+
+ PHY_Data = GET_REG(REG_MIID);
+ return PHY_Data;
+}
+
+/* Reset external PHY Chip */
+void PHY_Reset(void)
+{
+ unsigned int Read_Value;
+ unsigned int wait;
+ int i;
+ unsigned char Status = 0;
+
+ /* Configure GPIO2 function as MAC pins */
+ PUT_REG(REG_GPIO_CFG2, 0x00055555);
+ /* Configure MAC Command Register: 100M, Full Duplex, strip CRC, MDC clock
generation, accept control frame */
+ PUT_REG(REG_MCMDR, MCMDR_OPMOD | MCMDR_FDUP | MCMDR_SPCRC | MCMDR_EnMDC
/*| MCMDR_ACP | MCMDR_AEP*/);
+
+ print_phy("Reset KSZ8001 PHY...");
+ PHY_Write(PHY_CNTL_REG, PHYAD, RESET_PHY);
+
+ wait = 1000000;
+ while (1) /* wait for auto-negotiation complete */
+ {
+ Read_Value = PHY_Read(PHY_STATUS_REG, PHYAD) ;
+
+ if((Read_Value & AN_COMPLETE)!=0)
+ {
+ print_phy("OK\n");
+ break;
+ }
+
+ if(!(wait--))
+ {
+ print_phy("FAILED!\n");
+ break;
+ }
+ }
+
+
+ PHY_Write(PHY_ANA_REG, PHYAD,
DR100_TX_FULL|DR100_TX_HALF|DR10_TX_FULL|DR10_TX_HALF|IEEE_802_3_CSMA_CD);
+
+ Read_Value = PHY_Read(PHY_CNTL_REG, PHYAD);
+ Read_Value |= (RESTART_AN+ENABLE_AN);
+ PHY_Write(PHY_CNTL_REG, PHYAD, Read_Value);
+
+ print_phy("Wait for auto-negotiation complete...");
+ wait = 1000000; i=0;
+ while (1) /* wait for auto-negotiation complete */
+ {
+ Read_Value = PHY_Read(PHY_STATUS_REG, PHYAD) ;
+ if ((Read_Value & AN_COMPLETE) != 0)
+ {
+ print_phy("OK\n");
+ Status = 1;
+ break;
+ }
+
+ if (!(wait--))
+ {
+ print_phy("FAILED!!\n");
+ break;
+ }
+
+ if(i==10000)
+ {
+ i=0;
+ printk(".");
+ }
+ else
+ i++;
+
+ }// end while
+
+ if( Status == 0 )
+ {
+ print_phy("Set default: 100M Full Duplex\n");
+ /* Configure MAC Command Register: 100M, Full Duplex, strip CRC, MDC
clock generation, accept control frame */
+ PUT_REG(REG_MCMDR, MCMDR_OPMOD | MCMDR_FDUP | MCMDR_SPCRC | MCMDR_EnMDC
/*| MCMDR_ACP | MCMDR_AEP*/);
+ }
+ else
+ {
+ Read_Value = PHY_Read(0x1F, PHYAD) ; /* See KSZ8001 Data Sheet for
details */
+ Read_Value &= 0x1C;
+ if((Read_Value==8) || (Read_Value==0x18)) /* 100MB */
+ {
+ print_phy("100Mb - ");
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) | MCMDR_OPMOD);
+ }
+ else
+ if((Read_Value==4) || (Read_Value==0x14)) /* 10 MB */
+ {
+ print_phy("10MB - ");
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) & (~MCMDR_OPMOD));
+ }
+ else
+ print_phy("Still in auto-negotiation or PHY/MII isolate mode\n");
+
+
+ if((Read_Value == 0x18) || (Read_Value == 0x14))/* Full Duplex */
+ {
+ print_phy("Full Duplex\n");
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) | MCMDR_FDUP);
+ }
+ else
+ if((Read_Value == 8) || (Read_Value == 4)) /* Half Duplex */
+ {
+ print_phy("Half Duplex\n");
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) & (~MCMDR_FDUP));
+ }
+ }
+}
+#endif
+
+
+
+
+/* Public u-boot interface functions below */
+
+/* Init W90P710 Ethernet controller */
+int W90P710_eth_init(struct eth_device *dev, bd_t *bis)
+{
+ volatile unsigned int Check;
+ unsigned int cnt = 0;
+ ETH *eth = &m_eth;
+
+ printk("\nInit W90P710 EMC...\n");
+
+/* Configure GPIO2 function as MAC pins */
+ PUT_REG(REG_GPIO_CFG2, 0x00055555);
+
+ /* Store our MAC address */
+ eth->m_mac = bis->bi_enetaddr;
+
+ /* Issue Software Reset to the MAC */
+ PUT_REG(REG_MCMDR, MCMDR_SWR);
+
+ /* Wait for MAC come out from Reset */
+ do
+ {
+ Check = GET_REG(REG_MCMDR);
+ cnt++;
+ if(cnt == 10000)
+ printk("Error reseting MAC\n");
+ }
+ while(Check & MCMDR_SWR);
+
+ /* Set the Max RX Frame Length */
+ PUT_REG(REG_DMARFC, sizeof(MACFrame));
+
+ /* Set thresholds: TX low to 96, RX low to 96 and DMA burst to 8 words */
+ PUT_REG(REG_FFTCR, 0x100303);
+
+ /* Init frame descriptors */
+ TxFDinit(eth);
+ RxFDinit(eth);
+
+ /* Init the CAM with our MAC address */
+ PUT_REG(REG_CAM0M_Base, (eth->m_mac[0] << 24) | (eth->m_mac[1] << 16) |
(eth->m_mac[2] << 8) | (eth->m_mac[3]));
+ PUT_REG(REG_CAM0L_Base, (eth->m_mac[4] << 24) | (eth->m_mac[5] << 16));
+
+ /* Enable CAM address 0 -- the MAC we just loaded */
+ PUT_REG(REG_CAMEN, 0x1);
+ /* Accept broadcast packetes, enable compare mode */
+ PUT_REG(REG_CAMCMR, CAM_ABP | CAM_ECMP);
+
+ /* Configure MAC Command Register: 100M, Full Duplex, strip CRC, MDC clock
generation, accept control frame */
+//#ifndef CONFIG_RESET_PHY_R /* We do this operation in the phy_reset */
+ PUT_REG(REG_MCMDR, MCMDR_OPMOD | MCMDR_FDUP | MCMDR_SPCRC | MCMDR_EnMDC
/*| MCMDR_ACP | MCMDR_AEP*/);
+//#endif
+ /* Start reception process */
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) | MCMDR_RXON);
+
+ /* Remove halt on Rx */
+ /*PUT_REG(REG_RSDR,0);*/
+
+ /* Enable interrupts on TX and RX*/
+ PUT_REG(REG_MIEN, EnRXINTR | EnTXINTR | EnTXCP | EnRXGD | MISTA_RDU |
MISTA_RxBErr | MISTA_TxBErr);
+
+ return 0;
+}
+
+/* Send a packet */
+s32 W90P710_eth_send(struct eth_device *dev, volatile void *packet, s32
length)
+{
+ u32 Check;
+ ETH *eth = &m_eth;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ printk("EMC TX...");
+
+ if( eth->m_curTX_FD->m_opt.bf.owner)
+ {
+ printk("eth_send(): TX Frame. CPU not owner.\n");
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return -1;
+ }
+
+ /* copy user data into frame data pointer */
+ memcpy((void *)((u32)(eth->m_curTX_FD->m_frameDataPtr.ui)), (void
*)packet, length);
+
+ /* Set TX Frame flags */
+ eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1; /* Tx Interrupt Enable */
+ eth->m_curTX_FD->m_opt.bf.crc_en = 1; /* CRC Append Enable */
+ eth->m_curTX_FD->m_opt.bf.padding = 1; /* Padding Enable */
+
+ /* Set TX Frame length */
+ eth->m_curTX_FD->m_status.bf.len = length;
+
+ /* Change ownership to EMC */
+ eth->m_curTX_FD->m_opt.bf.owner = 1;
+
+ /* Enable MAC TXON if need and remove halt state writing TXDR control
register */
+ Check = GET_REG(REG_MCMDR);
+ if(!(Check & MCMDR_TXON))
+ PUT_REG(REG_MCMDR, Check | MCMDR_TXON);
+ PUT_REG(REG_TSDR, 0);
+
+ do
+ {
+ Check = GET_REG(REG_MISTA);
+// printk("MISTA=%x\n", Check);
+ }
+ while(!(Check & MISTA_TXINTR));
+
+ /* Clear all TX Bits in MISTA Register */
+ PUT_REG(REG_MISTA, Check & 0xFFFF0000);
+
+ /* If transmission comlete correctly */
+ if(eth->m_curTX_FD->m_status.bf.complete)
+ {
+ /* Change the Tx frame descriptor for next use */
+ eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD;
+ printk("Ok\n");
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return 0;
+ }
+ /* There was an error */
+ else
+ {
+ printk("EMC Transmission error. MISTA=%x\n", Check);
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return -1;
+ }
+}
+
+/* Check for received packets */
+s32 W90P710_eth_rx (struct eth_device *dev)
+{
+ s32 nLen = 0;
+ ETH *eth = &m_eth;
+ u32 Check, i=0;
+
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+ printk("EMC RX...");
+/* Get RX Interrupt status */
+ do
+ {
+ Check = GET_REG(REG_MISTA);
+ i++;
+ if(i>500000)
+ {
+ printk("RX Interrupt wait timeout elapsed\n");
+ break;
+ }
+ }
+ while(!(Check & MISTA_RXINTR));
+
+ /* check if packet ready */
+ if( Check & MISTA_RXINTR )
+ {
+ /* Clear all RX Bits in MISTA Register */
+ PUT_REG(REG_MISTA, Check & 0x0000FFFF);
+
+ /* process all waiting packets */
+ while (eth->m_curRX_FD->m_status.bf.owner==0)
+ {
+ /* If receive is successfull */
+ if(eth->m_curRX_FD->m_status.bf.good)
+ {
+ nLen = eth->m_curRX_FD->m_status.bf.len;
+ /* call back u-boot Receive function --> may call eth_send() */
+ NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
+ printk(" %d bytes received\n", nLen);
+ }
+
+ /* clear status */
+ eth->m_curRX_FD->m_status.ui = 0x0;
+ /* set owner back to EMC */
+ eth->m_curRX_FD->m_status.bf.owner = 0x02;
+
+ /* advance to next descriptor */
+ eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
+ }
+ }
+
+ /* Receive Descriptor Unavailable interrupt -> remove halt state from
RxDMA*/
+ if(Check & MISTA_RDU)
+ {
+ printk("Remove halt state from RxDMA\n");
+ PUT_REG(REG_RSDR, 0x0);
+ }
+#ifdef CONFIG_STATUS_LED
+ status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+ return nLen;
+}
+
+/* Halt ethernet engine */
+void W90P710_eth_halt(struct eth_device *dev)
+{
+ printk("ETH Halt...\n");
+ /* disable MAC TX and RX*/
+ PUT_REG(REG_MCMDR, GET_REG(REG_MCMDR) & (~(MCMDR_RXON | MCMDR_TXON)));
+}
+
+/* Fill eth_device structure with W90P710 EMC functions */
+int W90P710_EMC_initialize(bd_t *bis)
+{
+ struct eth_device *dev;
+ dev = (struct eth_device *)malloc(sizeof(*dev));
+ if (dev == NULL)
+ hang();
+
+ memset(dev, 0, sizeof(*dev));
+ sprintf(dev->name, "W90P710 EMC");
+
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = W90P710_eth_init;
+ dev->halt = W90P710_eth_halt;
+ dev->send = W90P710_eth_send;
+ dev->recv = W90P710_eth_rx;
+
+ eth_register(dev);
+ return 1;
+}
+#endif
diff -Naur u-boot/drivers/net/w90p710_eth.h
u-boot-patched/drivers/net/w90p710_eth.h
--- u-boot/drivers/net/w90p710_eth.h 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/drivers/net/w90p710_eth.h 2009-01-15 11:10:41.000000000
+0200
@@ -0,0 +1,296 @@
+#ifndef __W90P710_ETH_H
+#define __W90P710_ETH_H
+/*
+ * Copyright (c) 2008 KSL Embedded (http://www.kslemb.com)
+ * Vovk Konstantin <ksl at kslemb.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * MODULE: $Id:$
+ * Description: Ethernet interface
+ * Runtime Env: W90P710 SoC
+ * Change History:
+ * 08-09-2008 Created ksl at kslemb.com
+ *
+ */
+
+/* MAC MII Management Data Control and Address Register(MIIDA) */
+/*#define MDCCR 0x00000000 */ /* MDC clock rating */
+#define MDCCR 0x00F80000 /* MDC clock rating */
+#define PHYAD 0x00000100 /* PHY Address */
+#define PHYWR 0x00010000 /* Write Operation */
+#define PHYBUSY 0x00020000 /* Busy Bit */
+#define PHYPreSP 0x00040000 /* Preamble Suppress */
+
+/* MAC Command Register(MCMDR) Bits */
+#define MCMDR_RXON 0x00000001 /* Receive ON */
+#define MCMDR_ALP 0x00000002 /* Accept Long Packet */
+#define MCMDR_ARP 0x00000004 /* Accept Runt Packet */
+#define MCMDR_ACP 0x00000008 /* Accept Control Packet */
+#define MCMDR_AEP 0x00000010 /* Accept Error Packet */
+#define MCMDR_SPCRC 0x00000020 /* Accept Strip CRC Value*/
+#define MCMDR_TXON 0x00000100 /* Transmit On */
+#define MCMDR_NDEF 0x00000200 /* No defer */
+#define MCMDR_SDPZ 0x00010000 /* Send Pause */
+#define MCMDR_EnSQE 0x00020000 /* Enable SQE test */
+#define MCMDR_FDUP 0x00040000 /* Full Duplex */
+#define MCMDR_EnMDC 0x00080000 /* Enable MDC signal */
+#define MCMDR_OPMOD 0x00100000 /* Operation Mode */
+#define MCMDR_LBK 0x00200000 /* Loop Back */
+#define MCMDR_EnRMII 0x00400000 /* Enable RMII */
+#define MCMDR_LAN 0x00800000 /* LAN Port Setting Mode */
+#define MCMDR_SWR 0x01000000 /* Software Reset */
+
+/* MAC Interrupt Status Register (MISTA) Bits */
+#define MISTA_RXINTR 0x00000001 /* Interrupt on Receive
*/
+#define MISTA_CRCE 0x00000002 /* CRC Error
*/
+#define MISTA_RXOV 0x00000004 /* Receive FIFO Overflow error
*/
+#define MISTA_PTLE 0x00000008 /* Packet Too Long Error
*/
+#define MISTA_RXGD 0x00000010 /* Receive Good
*/
+#define MISTA_ALIE 0x00000020 /* Alignment Error
*/
+#define MISTA_RP 0x00000040 /* Runt Packet
*/
+#define MISTA_MMP 0x00000080 /* More Missed Packets than miss rolling
over counter flag */
+#define MISTA_DFOI 0x00000100 /* DMA receive frame over maximum size
interrupt */
+#define MISTA_DENI 0x00000200 /* DMA early notification interrupt
*/
+#define MISTA_RDU 0x00000400 /* Receive Descriptor Unavailable
interrupt */
+#define MISTA_RxBErr 0x00000800 /* Receive Bus Error interrupt
*/
+#define MISTA_NATOK 0x00001000 /* NAT Processing OK
*/
+#define MISTA_NATErr 0x00002000 /* NAT Processing Error
*/
+#define MISTA_CFR 0x00004000 /* Control Frame Receive
*/
+#define MISTA_TXINTR 0x00010000 /* Interrupt on Transmit
*/
+#define MISTA_TXEMP 0x00020000 /* Transmit FIFO Empty
*/
+#define MISTA_TXCP 0x00040000 /* Transmit Completion
*/
+#define MISTA_EXDEF 0x00080000 /* Defer
*/
+#define MISTA_NCS 0x00100000 /* No Carrier Sense
*/
+#define MISTA_TXABT 0x00200000 /* Transmit Abort
*/
+#define MISTA_LC 0x00400000 /* Late Collision
*/
+#define MISTA_TDU 0x00800000 /* Transmit Descriptor Unavailable
interrupt */
+#define MISTA_TxBErr 0x01000000 /* Transmit Bus Error interrupt
*/
+
+/* MAC Interrupt Enable Register(MIEN) */
+#define EnRXINTR 0x00000001 /* Enable Interrupt on Receive Interrupt
*/
+#define EnCRCE 0x00000002 /* Enable CRC Error Interrupt
*/
+#define EnRXOV 0x00000004 /* Enable Receive FIFO Overflow Interrupt
*/
+#define EnPTLE 0x00000008 /* Enable Packet Too Long Interrupt
*/
+#define EnRXGD 0x00000010 /* Enable Receive Good Interrupt
*/
+#define EnALIE 0x00000020 /* Enable Alignment Error Interrupt
*/
+#define EnRP 0x00000040 /* Enable Runt Packet on Receive
Interrupt */
+#define EnMMP 0x00000080 /* Enable More Missed Packets Interrupt
*/
+#define EnDFO 0x00000100 /* Enable DMA receive frame over maximum
size Interrupt */
+#define EnDEN 0x00000200 /* Enable DMA early notification
Interrupt */
+#define EnRDU 0x00000400 /* Enable Receive Descriptor Unavailable
Interrupt */
+#define EnRxBErr 0x00000800 /* Enable Receive Bus ERROR interrupt
*/
+#define EnNATOK 0x00001000 /* Enable NAT Processing OK Interrupt
*/
+#define EnNATErr 0x00002000 /* Enable NAT Processing Error Interrupt
*/
+#define EnCFR 0x00004000 /* Enable Control Frame Receive Interrupt
*/
+#define EnTXINTR 0x00010000 /* Enable Interrupt on Transmit Interrupt
*/
+#define EnTXEMP 0x00020000 /* Enable Transmit FIFO Empty Interrupt
*/
+#define EnTXCP 0x00040000 /* Enable Transmit Completion Interrupt
*/
+#define EnEXDEF 0x00080000 /* Enable Defer Interrupt
*/
+#define EnNCS 0x00100000 /* Enable No Carrier Sense Interrupt
*/
+#define EnTXABT 0x00200000 /* Enable Transmit Abort Interrupt
*/
+#define EnLC 0x00400000 /* Enable Late Collision Interrupt
*/
+#define EnTDU 0x00800000 /* Enable Transmit Descriptor Unavailable
Interrupt */
+#define EnTxBErr 0x01000000 /* Enable Transmit Bus ERROR Interrupt
*/
+
+/* CAM Command Register(CAMCMR) Bits */
+#define CAM_AUP 0x0001 /* Accept Packets with Unicast Address
*/
+#define CAM_AMP 0x0002 /* Accept Packets with Multicast Address
*/
+#define CAM_ABP 0x0004 /* Accept Packets with Broadcast Address
*/
+#define CAM_CCAM 0x0008 /* 0: Accept Packets CAM Recognizes and
Reject Others */
+ /* 1: Reject Packets CAM Recognizes and
Accept Others */
+#define CAM_ECMP 0x0010 /* Enable CAM Compare
*/
+
+
+/* PHY Register Description */
+#define PHY_CNTL_REG 0x00
+#define PHY_STATUS_REG 0x01
+#define PHY_ID1_REG 0x02
+#define PHY_ID2_REG 0x03
+#define PHY_ANA_REG 0x04
+#define PHY_ANLPA_REG 0x05
+#define PHY_ANE_REG 0x06
+
+#define PHY_DSC_REG 0x10
+#define PHY_DSCS_REG 0x11
+#define PHY_10BTCS_REG 0x12
+#define PHY_SINT_REG 0x15
+#define PHY_SREC_REG 0x16
+#define PHY_DISC_REG 0x17
+
+/* PHY Control Register Bits */
+#define RESET_PHY (1 << 15)
+#define ENABLE_LOOPBACK (1 << 14)
+#define DR_100MB (1 << 13)
+#define ENABLE_AN (1 << 12)
+#define PHY_POWER_DOWN (1 << 11)
+#define PHY_MAC_ISOLATE (1 << 10)
+#define RESTART_AN (1 << 9)
+#define PHY_FULLDUPLEX (1 << 8)
+#define PHY_COL_TEST (1 << 7)
+
+/* PHY Status Register Bits */
+#define AN_COMPLETE (1 << 5)
+
+/* PHY Auto-negotiation Advertisement Register Bits */
+#define DR100_TX_FULL (1 << 8)
+#define DR100_TX_HALF (1 << 7)
+#define DR10_TX_FULL (1 << 6)
+#define DR10_TX_HALF (1 << 5)
+#define IEEE_802_3_CSMA_CD 1
+
+
+
+#define ETH_MAC_ADDR_SIZE (6) /* dst,src addr is 6 bytes each
*/
+#define ETH_MaxTxFrames (16) /* Max number of Tx Frames */
+
+
+/* type of ethernet packets */
+#define ETH_TYPE_ARP (0x0806)
+#define ETH_TYPE_IP (0x0800)
+
+#define ETH_HDR_SIZE (14) /*
Dest[6]+Src[6]+LengthorType[2] */
+
+/* W90P710 bit field for TX Descriptor Word 0 */
+typedef struct __BF_TX_Options
+{
+ unsigned int padding: 1; /* PadEN - Padding Enable */
+ unsigned int crc_en: 1; /* CRCApp - CRC Append */
+ unsigned int macTxIrqEnbl: 1; /* IntEn - Transmit Interrupt Enable */
+ unsigned int reserved:28; /* Reserved */
+ unsigned int owner: 1; /* Owner - Ownership */
+} BF_TX_Options;
+
+/* W90P710 TX descriptor Word 0 as a union */
+typedef union _TX_Options
+{
+ unsigned int ui;
+ BF_TX_Options bf;
+} TX_Options;
+
+/* W90P710 bit field for Transmit Buffer Starting Address word */
+typedef struct __BF_FrameDataPtr
+{
+ unsigned int BO: 2;
+ unsigned int dataPtr:30;
+} BF_FrameDataPtr;
+
+/* W90P710 TX descriptor Word 1 as a union */
+typedef union _FrameDataPtr
+{
+ unsigned int ui;
+ BF_FrameDataPtr bf;
+} FrameDataPtr;
+
+/* W90P710 Third word of the TX Buffer descriptor */
+typedef struct __BF_TX_Status
+{
+ unsigned int len:16; /* Frame length */
+ unsigned int intTx: 1; /* TXINTR - Transmittion interrupt */
+ unsigned int txDefer: 1; /* DEF - Transmission Deffered */
+ unsigned int Reserverd1: 1; /* Reserved */
+ unsigned int complete: 1; /* TXCP - Transmission Complete */
+ unsigned int defer: 1; /* EXDEF - Deffer Exceed */
+ unsigned int noCarrier: 1; /* NCS - No Carrier Sense */
+ unsigned int exColl: 1; /* TXABT - Transmission Abort */
+ unsigned int lateColl: 1; /* LC - Late Collision */
+ unsigned int halted: 1; /* TXHA - Transmission Halted */
+ unsigned int paused: 1; /* PAU - Transmission Paused */
+ unsigned int SQErr: 1; /* SQE - SQE Error */
+ unsigned int Reserverd2: 1; /* Reserved */
+ unsigned int txCollCnt: 4; /* CCNT - Collision Count */
+} BF_TX_Status;
+
+/* W90P710 Third word of the TX Buffer descriptor as a union of the WORD
and Status+Byte count */
+typedef union _TX_Status
+{
+ unsigned int ui;
+ BF_TX_Status bf;
+} TX_Status;
+
+
+/* W90P710 TX descriptor structure */
+typedef struct __TX_FrameDescriptor
+{
+ TX_Options m_opt;
+ volatile FrameDataPtr m_frameDataPtr;
+ volatile TX_Status m_status;
+ struct __TX_FrameDescriptor *m_nextFD;
+} TX_FrameDescriptor __attribute__ ((aligned(16)));
+
+
+
+/* W90P710 Rx Buffer Descriptor Word 0 */
+typedef struct __BF_RX_Status
+{
+ unsigned int len:16; /* frame length */
+ unsigned int intRx: 1; /* RXINTR - Receive Interrupt */
+ unsigned int crcErr: 1; /* CRCE - CRC Error */
+ unsigned int Reserved1: 1; /* Reserved */
+ unsigned int longErr: 1; /* PTLE - Packet Too Long */
+ unsigned int good: 1; /* RXGD - Frame Reception Complete */
+ unsigned int alignErr: 1; /* ALIE - Alignment Error */
+ unsigned int RuntPack: 1; /* RP - Runt Packet */
+ unsigned int Reserved2: 7; /* Reserved */
+ unsigned int owner: 2; /* Owner - Ownership */
+} BF_RX_Status;
+
+/* W90P710 Rx Buffer Descriptor Word 0 as a union of the WORD and
Status+Byte count */
+typedef union _RX_Status
+{
+ unsigned int ui;
+ BF_RX_Status bf;
+} RX_Status;
+
+
+/* RX Buffer descriptor structure */
+typedef struct __RX_FrameDescriptor
+{
+ volatile RX_Status m_status;
+ volatile FrameDataPtr m_frameDataPtr;
+ volatile unsigned int m_reserved;
+ struct __RX_FrameDescriptor *m_nextFD;
+} RX_FrameDescriptor __attribute__ ((aligned(16)));
+
+
+
+
+
+/* MAC Frame Structure */
+struct __MACFrame
+{
+ unsigned char m_dstAddr[6];
+ unsigned char m_srcAddr[6];
+ unsigned short m_lengthOrType;
+ unsigned char m_payload[1506];
+} __attribute__ ((packed));
+
+typedef struct __MACFrame MACFrame;
+
+/* Ethernet Control block */
+typedef struct __ETH
+{
+ TX_FrameDescriptor *m_curTX_FD; /* pointer to current TX frame
descriptor */
+ TX_FrameDescriptor *m_baseTX_FD; /* pointer to base TX frame descriptor
*/
+ RX_FrameDescriptor *m_curRX_FD; /* pointer to current RX frame
descriptor */
+ RX_FrameDescriptor *m_baseRX_FD; /* pointer to base RX frame descriptor
*/
+ unsigned char *m_mac; /* pointer to our MAC address
*/
+} ETH;
+
+#endif
diff -Naur u-boot/examples/Makefile u-boot-patched/examples/Makefile
--- u-boot/examples/Makefile 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/examples/Makefile 2009-01-15 11:10:41.000000000 +0200
@@ -33,7 +33,11 @@
ifeq ($(BOARD),omap2420h4)
LOAD_ADDR = 0x80300000
else
-LOAD_ADDR = 0xc100000
+ ifeq ($(BOARD),w90p1)
+ LOAD_ADDR = 0x00001000
+ else
+ LOAD_ADDR = 0xc100000
+endif
endif
endif
diff -Naur u-boot/include/asm-arm/arch-arm720t/hardware.h
u-boot-patched/include/asm-arm/arch-arm720t/hardware.h
--- u-boot/include/asm-arm/arch-arm720t/hardware.h 2008-12-17
00:48:27.000000000 +0200
+++ u-boot-patched/include/asm-arm/arch-arm720t/hardware.h 2009-01-15
11:10:41.000000000 +0200
@@ -23,8 +23,9 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-
-#if defined(CONFIG_S3C4510B)
+#if defined(CONFIG_W90P710)
+#include <asm-arm/arch-arm720t/W90P710.h>
+#elif defined(CONFIG_S3C4510B)
#include <asm-arm/arch-arm720t/s3c4510b.h>
#elif defined(CONFIG_NETARM)
#include <asm-arm/arch-arm720t/netarm_registers.h>
diff -Naur u-boot/include/asm-arm/arch-arm720t/W90P710.h
u-boot-patched/include/asm-arm/arch-arm720t/W90P710.h
--- u-boot/include/asm-arm/arch-arm720t/W90P710.h 1970-01-01
03:00:00.000000000 +0300
+++ u-boot-patched/include/asm-arm/arch-arm720t/W90P710.h 2009-01-16
16:05:50.000000000 +0200
@@ -0,0 +1,308 @@
+/**************************************************************************************************
+ *
+ * Copyright (c) 2004 - 2006 Winbond Electronics Corp. All rights reserved.
+ *
+ * FILENAME: w90p710.h
+ *
+ * VERSION: 0.1
+ *
+ * DESCRIPTION
+ * This file contains the register map of W90P710 processor.
+ *
+ * HISTORY
+ * 2004/11/04 0.1 Draft version, Created by PC30 MNCheng
+ * 2008/18/08 Modifyed by KSL Embedded
+ *
+ * REMARK
+ * None
+
*************************************************************************************************/
+#ifndef _W90P710_H
+#define _W90P710_H
+
+/* L1 8KB on chip SRAM base address */
+#define SRAM_BASE 0xFFE00000
+
+#define GET_REG(reg) (*((volatile unsigned int *)(reg)))
+#define PUT_REG(reg, val) (*((volatile unsigned int *)(reg))) = (unsigned
int)(val)
+
+/**********************************************************************************************************
+ *
+ * System Address Map - Defines the register base address of each Macro
function.
+ *
+
**********************************************************************************************************/
+#define GCR_BA 0xFFF00000 /* Global Control */
+#define EBI_BA 0xFFF01000 /* EBI Control */
+#define CACHE_BA 0xFFF02000 /* Cache Control */
+#define EMC_BA 0xFFF03000 /* Ethernet MAC */
+#define GDMA_BA 0xFFF04000 /* GDMA control */
+#define USBH_BA 0xFFF05000 /* USB Host Control */
+#define USBD_BA 0xFFF06000 /* USB Device Control */
+#define FMI_BA 0xFFF07000 /* Flash Memory Card Interface */
+#define LCD_BA 0xFFF08000 /* Display, LCM Interface & Bypass */
+#define ADO_BA 0xFFF09000 /* Audio Control */
+
+#define UART0_BA 0xFFF80000 /* UART0 Control (console) */
+#define UART1_BA 0xFFF80100 /* UART1 Control (Bluetooth) */
+#define UART2_BA 0xFFF80200 /* UART2 Control (IrDA) */
+#define UART3_BA 0xFFF80300 /* UART3 Control (micro-printer) */
+#define TMR_BA 0xFFF81000 /* Timer */
+#define AIC_BA 0xFFF82000 /* Interrupt Controller */
+#define GPIO_BA 0xFFF83000 /* GPIO Control */
+#define RTC_BA 0xFFF84000 /* Real Time Clock Control */
+#define SCHI0_BA 0xFFF85000 /* Smart Card Host Interface 0 Control */
+#define SCHI1_BA 0xFFF85800 /* Smart Card Host Interface 1 Control */
+#define I2C0_BA 0xFFF86000 /* I2C 0 Control */
+#define I2C1_BA 0xFFF86100 /* I2C 1 Control */
+#define SSP_BA 0xFFF86200 /* Synchronous Serial Port */
+#define PWM_BA 0xFFF87000 /* Pulse Width Modulation Control */
+#define KPI_BA 0xFFF88000 /* Keypad Interface Control */
+#define PS2_BA 0xFFF89000 /* PS2 Interface Control */
+
+/****************************************************************************************************
+ *
+ * System Manager Control Registers
+ *
+
****************************************************************************************************/
+#define REG_PDID (GCR_BA+0x0000) /* Product Identifier Register */
+#define REG_ARBCON (GCR_BA+0x0004) /* Arbitration Control Register */
+#define REG_PLLCON (GCR_BA+0x0008) /* PLL Control Register */
+#define REG_CLKSEL (GCR_BA+0x000C) /* Clock Select Register */
+#define REG_PLLCON2 (GCR_BA+0x0010) /* PLL Control Register 2 */
+#define REG_I2SCKCON (GCR_BA+0x0014) /* Audio IIS Clock Control Register
*/
+#define REG_IRQWAKECON (GCR_BA+0x0020) /* IRQ Wakeup Control Register */
+#define REG_IRQWAKEFLAG (GCR_BA+0x0024) /* IRQ Wakeup Flag Register */
+#define REG_PMCON (GCR_BA+0x0028) /* Power Manager control Register */
+#define REG_USBTXRCON (GCR_BA+0x0030) /* USB transceiver control Register
*/
+
+/****************************************************************************************************
+ *
+ * Memory Control Registers
+ *
+
****************************************************************************************************/
+#define REG_EBICON (EBI_BA+0x000) /* EBI control register */
+#define REG_ROMCON (EBI_BA+0x004) /* ROM/FLASH control register */
+#define REG_SDCONF0 (EBI_BA+0x008) /* SDRAM bank 0 configuration register
*/
+#define REG_SDCONF1 (EBI_BA+0x00C) /* SDRAM bank 1 configuration register
*/
+#define REG_SDTIME0 (EBI_BA+0x010) /* SDRAM bank 0 timing control register
*/
+#define REG_SDTIME1 (EBI_BA+0x014) /* SDRAM bank 1 timing control register
*/
+#define REG_EXT0CON (EBI_BA+0x018) /* External I/O 0 control register */
+#define REG_EXT1CON (EBI_BA+0x01C) /* External I/O 1 control register */
+#define REG_EXT2CON (EBI_BA+0x020) /* External I/O 2 control register */
+#define REG_EXT3CON (EBI_BA+0x024) /* External I/O 3 control register */
+
+/****************************************************************************************************
+ *
+ * Cache Control Registers
+ *
+
****************************************************************************************************/
+#define REG_CAHCNF (CACHE_BA+0x000) /* Cache configuration register */
+#define REG_CAHCON (CACHE_BA+0x004) /* Cache control register */
+#define REG_CAHADR (CACHE_BA+0x008) /* Cache address register */
+
+/****************************************************************************************************
+ *
+ * MAC Registers
+ *
+
****************************************************************************************************/
+ /* Control register */
+#define REG_CAMCMR (EMC_BA+0x000) /* CAM Command Register */
+#define REG_CAMEN (EMC_BA+0x004) /* CAM Enable Register */
+#define REG_CAM0M_Base (EMC_BA+0x008)
+#define REG_CAM0L_Base (EMC_BA+0x00c)
+#define REG_CAMxM_Reg(x) (REG_CAM0M_Base+x*0x8) /* */
+#define REG_CAMxL_Reg(x) (REG_CAM0L_Base+x*0x8) /* */
+
+#define REG_TXDLSA (EMC_BA+0x088) /* Transmit Descriptor Link List Start
Address Register */
+#define REG_RXDLSA (EMC_BA+0x08C) /* Receive Descriptor Link List Start
Address Register */
+#define REG_MCMDR (EMC_BA+0x090) /* MAC Command Register */
+#define REG_MIID (EMC_BA+0x094) /* MII Management Data Register */
+#define REG_MIIDA (EMC_BA+0x098) /* MII Management Control and Address
Register */
+#define REG_FFTCR (EMC_BA+0x09C) /* FIFO Threshold Control Register */
+#define REG_TSDR (EMC_BA+0x0a0) /* Transmit Start Demand Register */
+#define REG_RSDR (EMC_BA+0x0a4) /* Receive Start Demand Register */
+#define REG_DMARFC (EMC_BA+0x0a8) /* Maximum Receive Frame Control
Register */
+#define REG_MIEN (EMC_BA+0x0ac) /* MAC Interrupt Enable Register */
+ /* Status Registers */
+#define REG_MISTA (EMC_BA+0x0b0) /* MAC Interrupt Status Register */
+#define REG_MGSTA (EMC_BA+0x0b4) /* MAC General Status Register */
+#define REG_MPCNT (EMC_BA+0x0b8) /* Missed Packet Count Register */
+#define REG_MRPC (EMC_BA+0x0bc) /* MAC Receive Pause Count Register */
+#define REG_MRPCC (EMC_BA+0x0c0) /* MAC Receive Pause Current Count
Register */
+#define REG_MREPC (EMC_BA+0x0c4) /* MAC Remote Pause Count Register */
+#define REG_DMARFS (EMC_BA+0x0c8) /* DMA Receive Frame Status Register */
+#define REG_CTXDSA (EMC_BA+0x0cc) /* Current Transmit Descriptor Start
Address Register */
+#define REG_CTXBSA (EMC_BA+0x0d0) /* Current Transmit Buffer Start Address
Register */
+#define REG_CRXDSA (EMC_BA+0x0d4) /* Current Receive Descriptor Start
Address Register */
+#define REG_CRXBSA (EMC_BA+0x0d8) /* Current Receive Buffer Start Address
Register */
+ /* Diagnostic Registers */
+#define REG_RXFSM (EMC_BA+0x200) /* Receive Finite State Machine Register
*/
+#define REG_TXFSM (EMC_BA+0x204) /* Transmit Finite State Machine Register
*/
+#define REG_FSM0 (EMC_BA+0x208) /* Finite State Machine Register 0 */
+#define REG_FSM1 (EMC_BA+0x20c) /* Finite State Machine Register 1 */
+#define REG_DCR (EMC_BA+0x210) /* Debug Configuration Register */
+#define REG_DMMIR (EMC_BA+0x214) /* Debug Mode MAC Information Register */
+#define REG_BISTR (EMC_BA+0x300) /* BIST Mode Register */
+
+/****************************************************************************************************
+ *
+ * USB Host Controller Registers
+ *
+
****************************************************************************************************/
+/* OpenHCI Registers */
+#define REG_HcRevision (USBH_BA+0x000) /* Host Controller Revision
Register */
+#define REG_HcControl (USBH_BA+0x004) /* Host Controller Control Register
*/
+#define REG_HcCommandStatus (USBH_BA+0x008) /* Host Controller Command
Status Register */
+#define REG_HcInterruptStatus (USBH_BA+0x00C) /* Host Controller
Interrupt Status Register */
+#define REG_HcInterruptEnable (USBH_BA+0x010) /* Host Controller Interrupt
Enable Register */
+#define REG_HcInterruptDisable (USBH_BA+0x014) /* Host Controller
Interrupt Disable Register */
+#define REG_HcHCCA (USBH_BA+0x018) /* Host Controller Communication Area
Register */
+#define REG_HcPeriodCurrentED (USBH_BA+0x01C) /* Host Controller Period
Current ED Register */
+#define REG_HcControlHeadED (USBH_BA+0x020) /* Host Controller Control
Head ED Register */
+#define REG_HcControlCurrentED (USBH_BA+0x024) /* Host Controller Control
Current ED Register */
+#define REG_HcBulkHeadED (USBH_BA+0x028) /* Host Controller Bulk Head ED
Register */
+#define REG_HcBulkCurrentED (USBH_BA+0x02C) /* Host Controller Bulk
Current ED Register */
+#define REG_HcDoneHead (USBH_BA+0x030) /* Host Controller Done Head
Register */
+#define REG_HcFmInterval (USBH_BA+0x034) /* Host Controller Frame Interval
Register */
+#define REG_HcFrameRemaining (USBH_BA+0x038) /* Host Controller Frame
Remaining Register */
+#define REG_HcFmNumber (USBH_BA+0x03C) /* Host Controller Frame Number
Register */
+#define REG_HcPeriodicStart (USBH_BA+0x040) /* Host Controller Periodic
Start Register */
+#define REG_HcLSThreshold (USBH_BA+0x044) /* Host Controller Low Speed
Threshold Register */
+#define REG_HcRhDescriptorA (USBH_BA+0x048) /* Host Controller Root Hub
Descriptor A Register */
+#define REG_HcRhDescriptorB (USBH_BA+0x04C) /* Host Controller Root Hub
Descriptor B Register */
+#define REG_HcRhStatus (USBH_BA+0x050) /* Host Controller Root Hub Status
Register */
+#define REG_HcRhPortStatus1 (USBH_BA+0x054) /* Host Controller Root Hub
Port Status [1] */
+#define REG_HcRhPortStatus2 (USBH_BA+0x058) /* Host Controller Root Hub
Port Status [2] */
+
+/* USB Configuration Registers */
+#define TestModeEnable (USBH_BA+0x200) /* USB Test Mode Enable Register */
+#define OperationalModeEnable (USBH_BA+0x204) /* USB Operational Mode
Enable Register */
+
+/****************************************************************************************************
+ *
+ * UART Control Registers
+ *
+
****************************************************************************************************/
+/* UART 0 */
+#define REG_UART0_TX (UART0_BA+0x0) /* (W) TX buffer */
+#define REG_UART0_RX (UART0_BA+0x0) /* (R) RX buffer */
+#define REG_UART0_LSB (UART0_BA+0x0) /* Divisor latch LSB */
+#define REG_UART0_MSB (UART0_BA+0x04) /* Divisor latch MSB */
+#define REG_UART0_IER (UART0_BA+0x04) /* Interrupt enable register */
+#define REG_UART0_IIR (UART0_BA+0x08) /* (R) Interrupt ident. register
*/
+#define REG_UART0_FCR (UART0_BA+0x08) /* (W) FIFO control register */
+#define REG_UART0_LCR (UART0_BA+0x0C) /* Line control register */
+#define REG_UART0_LSR (UART0_BA+0x14) /* (R) Line status register */
+#define REG_UART0_TOR (UART0_BA+0x1C) /* (R) Time out register */
+
+/****************************************************************************************************
+ *
+ * Timer Control Registers
+ *
+
****************************************************************************************************/
+#define REG_TCR0 (TMR_BA+0x0) /* Control Register 0 */
+#define REG_TCR1 (TMR_BA+0x04) /* Control Register 1 */
+#define REG_TICR0 (TMR_BA+0x08) /* Initial Control Register 0 */
+#define REG_TICR1 (TMR_BA+0x0C) /* Initial Control Register 1 */
+#define REG_TDR0 (TMR_BA+0x10) /* Data Register 0 */
+#define REG_TDR1 (TMR_BA+0x14) /* Data Register 1 */
+#define REG_TISR (TMR_BA+0x18) /* Interrupt Status Register */
+#define REG_WTCR (TMR_BA+0x1C) /* Watchdog Timer Control Register */
+
+/****************************************************************************************************
+ *
+ * Advanced Interrupt Controller Registers
+ *
+
****************************************************************************************************/
+#define REG_AIC_SCR1 (AIC_BA+0x04) /* Source control register 1 */
+#define REG_AIC_SCR2 (AIC_BA+0x08) /* Source control register 2 */
+#define REG_AIC_SCR3 (AIC_BA+0x0C) /* Source control register 3 */
+#define REG_AIC_SCR4 (AIC_BA+0x10) /* Source control register 4 */
+#define REG_AIC_SCR5 (AIC_BA+0x14) /* Source control register 5 */
+#define REG_AIC_SCR6 (AIC_BA+0x18) /* Source control register 6 */
+#define REG_AIC_SCR7 (AIC_BA+0x1C) /* Source control register 7 */
+#define REG_AIC_SCR8 (AIC_BA+0x20) /* Source control register 8 */
+#define REG_AIC_SCR9 (AIC_BA+0x24) /* Source control register 9 */
+#define REG_AIC_SCR10 (AIC_BA+0x28) /* Source control register 10 */
+#define REG_AIC_SCR11 (AIC_BA+0x2C) /* Source control register 11 */
+#define REG_AIC_SCR12 (AIC_BA+0x30) /* Source control register 12 */
+#define REG_AIC_SCR13 (AIC_BA+0x34) /* Source control register 13 */
+#define REG_AIC_SCR14 (AIC_BA+0x38) /* Source control register 14 */
+#define REG_AIC_SCR15 (AIC_BA+0x3C) /* Source control register 15 */
+#define REG_AIC_SCR16 (AIC_BA+0x40) /* Source control register 16 */
+#define REG_AIC_SCR17 (AIC_BA+0x44) /* Source control register 17 */
+#define REG_AIC_SCR18 (AIC_BA+0x48) /* Source control register 18 */
+#define REG_AIC_SCR19 (AIC_BA+0x4C) /* Source control register 19 */
+#define REG_AIC_SCR20 (AIC_BA+0x50) /* Source control register 20 */
+#define REG_AIC_SCR21 (AIC_BA+0x54) /* Source control register 21 */
+#define REG_AIC_SCR22 (AIC_BA+0x58) /* Source control register 22 */
+#define REG_AIC_SCR23 (AIC_BA+0x5C) /* Source control register 23 */
+#define REG_AIC_SCR24 (AIC_BA+0x60) /* Source control register 24 */
+#define REG_AIC_SCR25 (AIC_BA+0x64) /* Source control register 25 */
+#define REG_AIC_SCR26 (AIC_BA+0x68) /* Source control register 26 */
+#define REG_AIC_SCR27 (AIC_BA+0x6c) /* Source control register 27 */
+#define REG_AIC_SCR28 (AIC_BA+0x70) /* Source control register 28 */
+#define REG_AIC_SCR29 (AIC_BA+0x74) /* Source control register 29 */
+#define REG_AIC_SCR30 (AIC_BA+0x78) /* Source control register 30 */
+#define REG_AIC_SCR31 (AIC_BA+0x7c) /* Source control register 31 */
+
+#define REG_AIC_IRSR (AIC_BA+0x100) /* Interrupt raw status register
*/
+#define REG_AIC_IASR (AIC_BA+0x104) /* Interrupt active status
register */
+#define REG_AIC_ISR (AIC_BA+0x108) /* Interrupt status register */
+#define REG_AIC_IPER (AIC_BA+0x10C) /* Interrupt priority encoding
register */
+#define REG_AIC_ISNR (AIC_BA+0x110) /* Interrupt source number
register */
+#define REG_AIC_IMR (AIC_BA+0x114) /* Interrupt mask register */
+#define REG_AIC_OISR (AIC_BA+0x118) /* Output interrupt status
register */
+#define REG_AIC_MECR (AIC_BA+0x120) /* Mask enable command register */
+#define REG_AIC_MDCR (AIC_BA+0x124) /* Mask disable command register
*/
+#define REG_AIC_SSCR (AIC_BA+0x128) /* Source set command register */
+#define REG_AIC_SCCR (AIC_BA+0x12C) /* Source clear command register
*/
+#define REG_AIC_EOSCR (AIC_BA+0x130) /* End of service command register
*/
+#define REG_AIC_TEST (AIC_BA+0x200) /* ICE/Debug mode register */
+
+/****************************************************************************************************
+ *
+ * General-Purpose Input/Output Controller Registers
+ *
+
****************************************************************************************************/
+#define GPIO_OFFSET 0x10
+/* groups 0 */
+#define REG_GPIO_CFG0 (GPIO_BA+0x0000) /* GPIO port0 configuration
Register */
+#define REG_GPIO_DIR0 (GPIO_BA+0x0004) /* GPIO port0 direction control
Register */
+#define REG_GPIO_DATAOUT0 (GPIO_BA+0x0008) /* GPIO port0 data out Register
*/
+#define REG_GPIO_DATAIN0 (GPIO_BA+0x000c) /* GPIO port0 data input
Register */
+/* groups 1 */
+#define REG_GPIO_CFG1 (GPIO_BA+0x0010) /* GPIO port1 configuration
Register */
+#define REG_GPIO_DIR1 (GPIO_BA+0x0014) /* GPIO port1 direction control
Register */
+#define REG_GPIO_DATAOUT1 (GPIO_BA+0x0018) /* GPIO port1 data out Register
*/
+#define REG_GPIO_DATAIN1 (GPIO_BA+0x001c) /* GPIO port1 data input
Register */
+/* groups 2 */
+#define REG_GPIO_CFG2 (GPIO_BA+0x0020) /* GPIO port2 configuration
Register */
+#define REG_GPIO_DIR2 (GPIO_BA+0x0024) /* GPIO port2 direction control
Register */
+#define REG_GPIO_DATAOUT2 (GPIO_BA+0x0028) /* GPIO port2 data out Register
*/
+#define REG_GPIO_DATAIN2 (GPIO_BA+0x002c) /* GPIO port2 data input
Register */
+/* groups 3 */
+#define REG_GPIO_CFG3 (GPIO_BA+0x0030) /* GPIO port3 configuration
Register */
+#define REG_GPIO_DIR3 (GPIO_BA+0x0034) /* GPIO port3 direction control
Register */
+#define REG_GPIO_DATAOUT3 (GPIO_BA+0x0038) /* GPIO port3 data out Register
*/
+#define REG_GPIO_DATAIN3 (GPIO_BA+0x003c) /* GPIO port3 data input
Register */
+/* groups 4 */
+#define REG_GPIO_CFG4 (GPIO_BA+0x0040) /* GPIO port4 configuration
Register */
+#define REG_GPIO_DIR4 (GPIO_BA+0x0044) /* GPIO port4 direction control
Register */
+#define REG_GPIO_DATAOUT4 (GPIO_BA+0x0048) /* GPIO port4 data out Register
*/
+#define REG_GPIO_DATAIN4 (GPIO_BA+0x004c) /* GPIO port4 data input
Register */
+/* groups 5 */
+#define REG_GPIO_CFG5 (GPIO_BA+0x0050) /* GPIO port5 configuration
Register */
+#define REG_GPIO_DIR5 (GPIO_BA+0x0054) /* GPIO port5 direction control
Register */
+#define REG_GPIO_DATAOUT5 (GPIO_BA+0x0058) /* GPIO port5 data out Register
*/
+#define REG_GPIO_DATAIN5 (GPIO_BA+0x005c) /* GPIO port5 data input
Register */
+/* groups 6 */
+#define REG_GPIO_CFG6 (GPIO_BA+0x0060) /* GPIO port6 configuration
Register */
+#define REG_GPIO_DIR6 (GPIO_BA+0x0064) /* GPIO port6 direction control
Register */
+#define REG_GPIO_DATAOUT6 (GPIO_BA+0x0068) /* GPIO port6 data out Register
*/
+#define REG_GPIO_DATAIN6 (GPIO_BA+0x006c) /* GPIO port6 data input
Register */
+
+#define REG_GPIO_DBNCECON (GPIO_BA+0x0070) /* GPIO input debounce
control Register */
+#define REG_GPIO_XICFG (GPIO_BA+0x0074) /* Extend Interrupt Configure
Register */
+#define REG_GPIO_XISTATUS (GPIO_BA+0x0078) /* Extend Interrupt Status
Register */
+
+#endif /* _W90P710_H */
diff -Naur u-boot/include/asm-arm/io.h u-boot-patched/include/asm-arm/io.h
--- u-boot/include/asm-arm/io.h 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/include/asm-arm/io.h 2009-01-15 11:10:41.000000000 +0200
@@ -46,6 +46,10 @@
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
+ #ifdef CONFIG_W90P710
+ if(flags==MAP_NOCACHE)
+ paddr |= 0x80000000;
+ #endif
return (void *)paddr;
}
diff -Naur u-boot/include/configs/W90P1.h
u-boot-patched/include/configs/W90P1.h
--- u-boot/include/configs/W90P1.h 1970-01-01 03:00:00.000000000 +0300
+++ u-boot-patched/include/configs/W90P1.h 2009-01-16 10:17:31.000000000
+0200
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2008 KSL Embedded (http://www.kslemb.com)
+ * Vovk Konstantin <ksl at kslemb.com>
+ *
+ * Configuation settings for W90P1 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ *
+ * #define CONFIG_SKIP_LOWLEVEL_INIT
+ */
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
+#define CONFIG_W90P710 1 /* it's a W90P710 chip */
+#define CONFIG_W90P1 1 /* on an W90P1 Board */
+
+#define CONFIG_IDENT_STRING "\nKSL uBoot port for W90P710 SoC v1.1"
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_W90P710_ETH 1
+#define CONFIG_DRIVER_W90P710_UART 1
+#define CONFIG_DRIVER_W90P710_FLASH 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 1 /* we use Serial line 1*/
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * BOOTP options
+ */
+
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+/*
+ * Board miscellaneous initializations: Init ECS1 and ECS2 for work with
IDE bus
+ */
+#define CONFIG_MISC_INIT_R 1
+
+
+/* Enable NAND Flash support */
+#define CONFIG_CMD_NAND 1
+
+/* Enable IDE support */
+#define CONFIG_CMD_IDE 1
+
+/* Enable status LED */
+#define CONFIG_STATUS_LED 1
+
+/* If board support NAND flash */
+#if defined (CONFIG_CMD_NAND)
+
+#define NAND_MAX_CHIPS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define W90P710_NAND_BASE 0xF2000000
+#define W90P710_NAND_CLE (1<<20) /* CLE Address line */
+#define W90P710_NAND_ALE (1<<21) /* ALE Address line */
+#define CONFIG_SYS_NAND_BASE W90P710_NAND_BASE /* Base Address of the
memory mapped NAND flash interface */
+
+#endif /* CONFIG_CMD_NAND */
+
+/* If board support IDE interface */
+#if defined (CONFIG_CMD_IDE)
+
+#define CONFIG_DOS_PARTITION 1
+
+/* W90P710 memory mapped IDE/ATA stuff */
+#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
+#undef CONFIG_IDE_LED /* no led for ide supported */
+#undef CONFIG_IDE_RESET /* no reset for ide supported */
+
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max is 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) /* max 1
drive per IDE bus */
+
+/* W90P1 board implements work with Data and registers via ECS1*/
+#define CONFIG_SYS_ATA_BASE_ADDR 0xF3000000 /* Must be identical
to the EXT1_BASE defined in /board/w90p1/ide.c */
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data
I/O */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal
register accesses */
+/* CONFIG_SYS_ATA_ALT_OFFSET is used for work with Control Block [CBR]
registers with A0...A2 = 0x6,0x7 */
+/* uBoot used only 0x6 - Alter Status/Device Control register */
+/* W90P1 board implements work with CBR via ECS2*/
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x01000000 /* Offset for
alternate registers Must be identical to the (EXT2_BASE-EXT1_BASE) */
+
+#endif /* CONFIG_CMD_IDE */
+
+/* If board support Status LED */
+#if defined (CONFIG_STATUS_LED)
+
+#define CONFIG_BOARD_SPECIFIC_LED 1
+
+#define STATUS_LED_BIT 0x00000004 /* GPIO2 pin 60 */
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4) /* 250ms */
+#define STATUS_LED_STATE STATUS_LED_BLINKING
+#define STATUS_LED_ACTIVE 0 /* LED on for bit is '0' */
+#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
+
+#define STATUS_LED_DIR 0xFFF83004 /* GPIO Port
Direction register address*/
+#define STATUS_LED_PORT 0xFFF83008 /* GPIO Port Data
output register */
+
+#endif /* CONFIG_STATUS_LED */
+
+/* Enable Ping command */
+#define CONFIG_CMD_PING
+/* Enable one or more MAC's support */
+#define CONFIG_NET_MULTI
+
+#define CONFIG_ETHADDR 00:40:95:36:35:33
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.0.84
+#define CONFIG_SERVERIP 192.168.0.4
+
+/* Enable PHY Reset after MAC Init */
+/*#define CONFIG_RESET_PHY_R*/
+
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_BOOTDELAY 2 /* delay for automatic boot */
+/*#define CONFIG_SYS_AUTOLOAD "no"*/ /*rarpb, bootp or dhcp commands will
perform only*/
+
+#define CONFIG_LOADADDR 0x8000 /* default load address */
+#define CONFIG_BOOTCOMMAND "bootm 0x7F090000" /* Start uClinux from NOR
Flash */
+/*#define CONFIG_BOOTCOMMAND "tftp 0x8000 uImage"*/
+
+#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/hda1 rw"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "->" /* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer
Size */
+
+#define CONFIG_CMDLINE_TAG 1 /* allow passing of command line
args to linux */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x01F00000 /* 31 MB in DRAM */
+
+
+#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default Linux kernel load
address */
+
+#define CONFIG_SYS_CLK_FREQ 80000000 /* CPU freq: 80 MHz */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 KHz */
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+
+#if defined (CONFIG_USE_IRQ)
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*
+ * Physical Memory Map after relocation
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
+
+/* U-Boot code can handle detection of the flash automatically */
+#define CONFIG_SYS_FLASH_CFI 1 /* The flash is CFI compatible */
+#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
+#define CONFIG_FLASH_CFI_AMD_RESET /* Reset command is F0 */
+
+#define CONFIG_SYS_FLASH_BASE 0x7F000000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB),
but newer have 71 (M29W320EB) */
+
+
+/* environment settings */
+#define CONFIG_ENV_IS_IN_FLASH
+#undef CONFIG_ENV_IS_NOWHERE
+
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) /* environment
start address 256K used for uBoot*/
+#define CONFIG_ENV_SECT_SIZE 0x10000 /* Total
Size of Environment Sector 64K*/
+
+#define CONFIG_ENV_SIZE 0x1000 /* max size for
environment 4K */
+#define CONFIG_FLASH_SHOW_PROGRESS 15
+
+#endif /* __CONFIG_H */
diff -Naur u-boot/include/netdev.h u-boot-patched/include/netdev.h
--- u-boot/include/netdev.h 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/include/netdev.h 2009-01-16 01:15:51.000000000 +0200
@@ -70,6 +70,7 @@
int tsi108_eth_initialize(bd_t *bis);
int uec_initialize(int index);
int uli526x_initialize(bd_t *bis);
+int W90P710_EMC_initialize(bd_t *bis);
/* Boards with PCI network controllers can call this from their
board_eth_init()
* function to initialize whatever's on board.
diff -Naur u-boot/MAKEALL u-boot-patched/MAKEALL
--- u-boot/MAKEALL 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/MAKEALL 2009-01-15 12:25:51.000000000 +0200
@@ -475,6 +475,7 @@
lpc2292sodimm \
modnet50 \
SMN42 \
+ w90p1 \
"
#########################################################################
diff -Naur u-boot/Makefile u-boot-patched/Makefile
--- u-boot/Makefile 2008-12-17 00:48:27.000000000 +0200
+++ u-boot-patched/Makefile 2009-01-15 12:33:36.000000000 +0200
@@ -2839,6 +2839,9 @@
SMN42_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
+W90P1_config : unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm720t w90p1
+
#########################################################################
## XScale Systems
#########################################################################
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