[U-Boot] [PATCH] 83xx: Use the proper sequence for updating IMMR.

[Scott Wood]

This ensures that subsequent accesses properly hit the new window.

The dcbi during the NAND loop was accidentally working around this;
it's no longer necessary, as the cache is not enabled.

Reported-by: Suchit Lepcha <Suchit.Lepcha at freescale.com>
Signed-off-by: Scott Wood <scottwood at freescale.com>
---
 cpu/mpc83xx/start.S |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S
index 792b2c8..c78126d 100644
--- a/cpu/mpc83xx/start.S
+++ b/cpu/mpc83xx/start.S
@@ -161,9 +161,23 @@ boot_cold: /* time t 3 */
 	nop
 boot_warm: /* time t 5 */
 	mfmsr	r5			/* save msr contents	*/
+
+	/* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
+	bl	1f
+1:	mflr	r7
+
 	lis	r3, CONFIG_SYS_IMMR at h
 	ori	r3, r3, CONFIG_SYS_IMMR at l
+
+	lwz	r6, IMMRBAR(r4)
+	isync
+
 	stw	r3, IMMRBAR(r4)
+	lwz	r6, 0(r7)		/* Arbitrary external load */
+	isync
+
+	lwz	r6, IMMRBAR(r3)
+	isync
 
 	/* Initialise the E300 processor core		*/
 	/*------------------------------------------*/
@@ -173,9 +187,7 @@ boot_warm: /* time t 5 */
 	 * is loaded.  Wait for the rest before branching
 	 * to another flash page.
 	 */
-	addi	r7, r3, 0x50b0
-1:	dcbi	0, r7
-	lwz	r6, 0(r7)
+1:	lwz	r6, 0x50b0(r3)
 	andi.	r6, r6, 1
 	beq	1b
 #endif
-- 
1.5.6.rc1.6.gc53ad