[U-Boot] [PATCH] Add support for the digsy MTC board.
Grzegorz Bernacki
gjb at semihalf.com
Wed Jan 28 16:07:55 CET 2009
This is the InterControl custom device based on the MPC5200B chip.
Signed-off-by: Grzegorz Bernacki <gjb at semihalf.com>
diff --git a/MAKEALL b/MAKEALL
index 530fe82..530651d 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -47,6 +47,7 @@ LIST_5xxx=" \
BC3450 \
cm5200 \
cpci5200 \
+ digsymtc \
EVAL5200 \
fo300 \
icecube_5100 \
diff --git a/Makefile b/Makefile
index 8c73586..db60e93 100644
--- a/Makefile
+++ b/Makefile
@@ -527,6 +527,22 @@ cm5200_config: unconfig
cpci5200_config: unconfig
@$(MKCONFIG) -a cpci5200 ppc mpc5xxx cpci5200 esd
+digsymtc_config \
+digsymtc_LOWBOOT_config \
+digsymtc_RAMBOOT_config: unconfig
+ @mkdir -p $(obj)include
+ @mkdir -p $(obj)board/digsymtc
+ @ >$(obj)include/config.h
+ @[ -z "$(findstring LOWBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0xFF000000" >$(obj)board/digsymtc/config.tmp ; \
+ echo "... with LOWBOOT configuration" ; \
+ }
+ @[ -z "$(findstring RAMBOOT_,$@)" ] || \
+ { echo "TEXT_BASE = 0x00100000" >$(obj)board/digsymtc/config.tmp ; \
+ echo "... with RAMBOOT configuration" ; \
+ }
+ @$(MKCONFIG) -a digsymtc ppc mpc5xxx digsymtc
+
hmi1001_config: unconfig
@$(MKCONFIG) hmi1001 ppc mpc5xxx hmi1001
diff --git a/board/digsymtc/Makefile b/board/digsymtc/Makefile
new file mode 100644
index 0000000..4bcb233
--- /dev/null
+++ b/board/digsymtc/Makefile
@@ -0,0 +1,51 @@
+
+#
+# (C) Copyright 2003-2009
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/digsymtc/config.mk b/board/digsymtc/config.mk
new file mode 100644
index 0000000..f160674
--- /dev/null
+++ b/board/digsymtc/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2003-2009
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# digsyMTC board:
+#
+# Valid values for TEXT_BASE are:
+#
+# 0xFFF00000 boot high (standard configuration)
+# 0xFE000000 boot low
+# 0x00100000 boot from RAM (for testing only)
+#
+
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+
+ifndef TEXT_BASE
+## Standard: boot high
+TEXT_BASE = 0xFFF00000
+## For testing: boot from RAM
+# TEXT_BASE = 0x00100000
+endif
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/digsymtc/digsymtc.c b/board/digsymtc/digsymtc.c
new file mode 100644
index 0000000..bd7d0cd
--- /dev/null
+++ b/board/digsymtc/digsymtc.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * (C) Copyright 2005-2009
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ * frank.bodammer at gcd-solutions.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include "eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#include "is42s16800a-7t.h"
+
+#ifndef CONFIG_SYS_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = control | 0x80000000;
+ __asm__ volatile ("sync");
+
+ /* precharge all banks */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = control | 0x80000002;
+ __asm__ volatile ("sync");
+
+ /* auto refresh */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = control | 0x80000004;
+ __asm__ volatile ("sync");
+
+ /* set mode register */
+ *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+ __asm__ volatile ("sync");
+
+ /* normal operation */
+ *(vu_long *)MPC5XXX_SDRAM_CTRL = control;
+ __asm__ volatile ("sync");
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+#ifndef CONFIG_SYS_RAMBOOT
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001C; /* 512MB at 0x0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
+ __asm__ volatile ("sync");
+
+ /* setup config registers */
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+ *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+ __asm__ volatile ("sync");
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x08000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20)) {
+ dramsize = 0;
+ }
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG =
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ }
+
+ /* let SDRAM CS1 start right after CS0 */
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001C;/* 512MB */
+
+ /* find RAM size using SDRAM CS1 only */
+ test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize),
+ 0x08000000);
+ dramsize2 = test1;
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize2 < (1 << 20)) {
+ dramsize2 = 0;
+ }
+
+ /* set SDRAM CS1 size according to the amount of RAM found */
+ if (dramsize2 > 0) {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+ | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+ } else {
+ *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ }
+
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ if (dramsize >= 0x13) {
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ } else {
+ dramsize = 0;
+ }
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+ if (dramsize2 >= 0x13) {
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ } else {
+ dramsize2 = 0;
+ }
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) &&
+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+ *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+ __asm__ volatile ("sync");
+ }
+
+ return dramsize + dramsize2;
+}
+
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ puts ("Board: InterControl digsyMTC");
+ if (s != NULL) { puts(", "); puts(s); }
+ putc('\n');
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ /*
+ * Now, when we are in RAM, enable flash write access for detection
+ * process. Note that CS_BOOT cannot be cleared when executing in
+ * flash.
+ */
+ *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
+ *(vu_long *)MPC5XXX_ADDECR |= (1 << 17); /* enable CS1 */
+ *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
+
+ return (0);
+}
+
+void set_ethaddr(void)
+{
+ char str_eth_addr[20];
+ uchar eth_addr[6];
+ ulong n;
+ ushort read = 0;
+ ushort addr = 0;
+ ushort chip = 0;
+ ushort addr_of_eth_addr = 0;
+ ushort len_sys = 0;
+ ushort len_sys_cfg = 0;
+
+ /* check identification word */
+ i2c_read(EEPROM_ADDR, EEPROM_ADDR_IDENT, 1, (uchar *)&read, 2);
+ if (read != EEPROM_IDENT)
+ return;
+
+ /* calculate offset of config area */
+ i2c_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYS, 1, (uchar *)&len_sys, 2);
+ i2c_read(EEPROM_ADDR, EEPROM_ADDR_LEN_SYSCFG, 1,
+ (uchar *)&len_sys_cfg, 2);
+ addr_of_eth_addr = (len_sys + len_sys_cfg + EEPROM_OFF_ETHADDR) << 1;
+ if (addr_of_eth_addr >= EEPROM_LEN)
+ return;
+
+ for (n = 0; n < 6 ; n++) {
+ addr = addr_of_eth_addr + n;
+ chip = EEPROM_ADDR + ((addr & 0x300)>>8);
+ i2c_read(chip, (addr & 0xFF), 1, (uchar *)ð_addr[n], 1);
+ }
+
+ sprintf(str_eth_addr, "%02X:%02X:%02X:%02X:%02X:%02X",
+ eth_addr[0], eth_addr[1], eth_addr[2],
+ eth_addr[3], eth_addr[4], eth_addr[5]);
+ setenv("ethaddr", str_eth_addr);
+}
+
+int last_stage_init (void)
+{
+ set_ethaddr();
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+static struct pci_controller hose;
+
+extern void pci_mpc5xxx_init(struct pci_controller *);
+
+void pci_init_board(void)
+{
+ pci_mpc5xxx_init(&hose);
+}
+#endif
+
+#ifdef CONFIG_CMD_IDE
+
+#ifdef CONFIG_IDE_RESET
+
+void init_ide_reset(void)
+{
+ debug ("init_ide_reset\n");
+
+ /* set gpio output value to 1 */
+ *(vu_long *)MPC5XXX_WU_GPIO_DATA_O |= (1 << 25);
+ /* open drain output */
+ *(vu_long *)MPC5XXX_WU_GPIO_ODE |= (1 << 25);
+ /* direction output */
+ *(vu_long *)MPC5XXX_WU_GPIO_DIR |= (1 << 25);
+ /* enable gpio */
+ *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= (1 << 25);
+
+}
+
+void ide_set_reset(int idereset)
+{
+
+ debug ("ide_reset(%d)\n", idereset);
+
+ /* set gpio output value to 0 */
+ *(vu_long *)MPC5XXX_WU_GPIO_DATA_O &= ~(1 << 25);
+ /* open drain output */
+ *(vu_long *)MPC5XXX_WU_GPIO_ODE |= (1 << 25);
+ /* direction output */
+ *(vu_long *)MPC5XXX_WU_GPIO_DIR |= (1 << 25);
+ /* enable gpio */
+ *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= (1 << 25);
+
+ udelay(10000);
+
+ /* set gpio output value to 1 */
+ *(vu_long *)MPC5XXX_WU_GPIO_DATA_O |= (1 << 25);
+ /* open drain output */
+ *(vu_long *)MPC5XXX_WU_GPIO_ODE |= (1 << 25);
+ /* direction output */
+ *(vu_long *)MPC5XXX_WU_GPIO_DIR |= (1 << 25);
+ /* enable gpio */
+ *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= (1 << 25);
+
+}
+#endif /* CONFIG_IDE_RESET */
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#endif /* CONFIG_CMD_IDE */
+
diff --git a/board/digsymtc/eeprom.h b/board/digsymtc/eeprom.h
new file mode 100644
index 0000000..2efed4a
--- /dev/null
+++ b/board/digsymtc/eeprom.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2009 Semihalf.
+ * Written by: Grzegorz Bernacki <gjb at semihalf.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the anty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef CMD_EEPROM_H
+#define CMD_EEPROM_H
+
+#define EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR
+#define EEPROM_LEN 1024
+#define EEPROM_IDENT 2408
+#define EEPROM_ADDR_IDENT 0x0000
+#define EEPROM_ADDR_LEN_SYS 0x0002
+#define EEPROM_ADDR_LEN_SYSCFG 0x0004
+#define EEPROM_OFF_ETHADDR 23
+
+#endif
diff --git a/board/digsymtc/is42s16800a-7t.h b/board/digsymtc/is42s16800a-7t.h
new file mode 100644
index 0000000..1873ea7
--- /dev/null
+++ b/board/digsymtc/is42s16800a-7t.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2004-2009
+ * Mark Jonas, Freescale Semiconductor, mark.jonas at motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#define SDRAM_MODE 0x00CD0000
+#define SDRAM_CONTROL 0x505F0000
+#define SDRAM_CONFIG1 0xD2322900
+#define SDRAM_CONFIG2 0x8AD70000
+
diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c
index df5b4ac..07d33e3 100644
--- a/cpu/mpc5xxx/ide.c
+++ b/cpu/mpc5xxx/ide.c
@@ -12,7 +12,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -42,7 +42,7 @@ int ide_preinit (void)
struct mpc5xxx_sdma *psdma = (struct mpc5xxx_sdma *) MPC5XXX_SDMA;
reg = *(vu_long *) MPC5XXX_GPS_PORT_CONFIG;
-#if defined(CONFIG_TOTAL5200)
+#if defined(CONFIG_TOTAL5200) || defined(CONFIG_DIGSY_MTC)
/* ATA cs0/1 on i2c2 clk/io */
reg = (reg & ~0x03000000ul) | 0x02000000ul;
#else
diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c
index f8618b1..a1c72d6 100644
--- a/drivers/net/mpc5xxx_fec.c
+++ b/drivers/net/mpc5xxx_fec.c
@@ -893,6 +893,7 @@ int mpc5xxx_fec_initialize(bd_t * bis)
fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
#if defined(CONFIG_CANMB) || \
defined(CONFIG_CM5200) || \
+ defined(CONFIG_DIGSY_MTC) || \
defined(CONFIG_HMI1001) || \
defined(CONFIG_ICECUBE) || \
defined(CONFIG_INKA4X0) || \
diff --git a/include/configs/digsymtc.h b/include/configs/digsymtc.h
new file mode 100644
index 0000000..4942103
--- /dev/null
+++ b/include/configs/digsymtc.h
@@ -0,0 +1,341 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * (C) Copyright 2005-2007
+ * Modified for InterControl digsyMTC MPC5200 board by
+ * Frank Bodammer, GCD Hard- & Software GmbH,
+ * frank.bodammer at gcd-solutions.de
+ *
+ * (C) Copyright 2009 Semihalf
+ * Optimized for digsyMTC by: Grzegorz Bernacki <gjb at semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software\; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation\; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY\; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program\; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
+
+#define BOOTFLAG_COLD 0x01
+#define BOOTFLAG_WARM 0x02
+
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * PCI Mapping:
+ * 0x40000000 - 0x4fffffff - PCI Memory
+ * 0x50000000 - 0x50ffffff - PCI IO Space
+ */
+#define CONFIG_PCI 1
+#define CONFIG_PCI_PNP 1
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0x40000000
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x10000000
+
+#define CONFIG_PCI_IO_BUS 0x50000000
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x01000000
+
+/*
+ * Partitions
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BZIP2
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_USB
+
+#if (TEXT_BASE == 0xFF000000)
+#define CONFIG_SYS_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 1
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "console=ttyPSC1\0" \
+ "kernel_addr_r=400000\0" \
+ "fdt_addr_r=600000\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:"\
+ "${netmask}:${hostname}:${netdev}:off panic=1\0" \
+ "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
+ "tftp ${fdt_addr_r} ${fdt_file};" \
+ "run nfsargs addip addcons;" \
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "update=protect off FFF00000 +${filesize};" \
+ "erase FFF00000 +${filesize};" \
+ "cp.b 200000 FFF00000 ${filesize};" \
+ "protect on FFF00000 +${filesize}\0" \
+ ""
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1
+#define CONFIG_SYS_I2C_MODULE 1
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+
+/*
+ * Flash configuration
+ */
+#define CONFIG_SYS_FLASH_CFI 1
+#define CONFIG_FLASH_CFI_DRIVER 1
+
+#define CONFIG_SYS_FLASH_BASE 0xFF000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_FLASH_16BIT
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+
+#define OF_CPU "PowerPC,5200 at 0"
+#define OF_SOC "soc5200 at f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200 at f0000000/serial at 2600"
+
+#define CONFIG_BOARD_EARLY_INIT_R
+/*
+ * Environment settings
+ */
+
+#define CONFIG_ENV_IS_IN_FLASH 1
+#if defined(CONFIG_LOWBOOT)
+#define CONFIG_ENV_ADDR 0xFF060000
+#else /* CONFIG_LOWBOOT */
+#define CONFIG_ENV_ADDR 0xFFF60000
+#endif /* CONFIG_LOWBOOT */
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE 1
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xF0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+#else
+#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
+#endif
+
+/*
+ * Use SRAM until RAM will be available
+ */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE 4096
+#define CONFIG_SYS_GBL_DATA_OFFSET \
+ (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT 1
+#endif
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_PHY_RESET_DELAY 1000
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
+
+/*
+ * GPIO configuration
+ */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_SYS_PROMPT "=> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#define CONFIG_AUTOBOOT_KEYED
+#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
+#define CONFIG_AUTOBOOT_DELAY_STR " "
+
+#define CONFIG_LOOPW 1
+#define CONFIG_MX_CYCLIC 1
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
+#define CONFIG_SYS_MEMTEST_START 0x00010000
+#define CONFIG_SYS_MEMTEST_END 0x019fffff
+
+#define CONFIG_SYS_LOAD_ADDR 0x00100000
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_LAST_STAGE_INIT
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_SDRAM_CS1 1
+#define CONFIG_SYS_XLB_PIPELINING 1
+
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+
+#if defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
+#endif
+
+#define CONFIG_SYS_CS4_START 0x60000000
+#define CONFIG_SYS_CS4_SIZE 0x1000
+#define CONFIG_SYS_CS4_CFG 0x0008FC00
+
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_CFG 0x0002DD00
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
+
+#if !defined(CONFIG_SYS_LOWBOOT)
+#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
+#else
+#define CONFIG_SYS_RESET_ADDRESS 0xff000100
+#endif
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_USB_CLOCK 0x00013333
+#define CONFIG_USB_CONFIG 0x00002000
+
+/*
+ * IDE/ATA
+ */
+
+#define CONFIG_IDE_RESET
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS 1
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
+#define CONFIG_SYS_ATA_STRIDE 4
+
+#define CONFIG_ATAPI 1
+#define CONFIG_LBA48 1
+
+#endif /* __CONFIG_H */
+
--
1.6.0.6
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