[U-Boot] [PATCH] 83xx: UEC: Added support for bitBang MII driver access to PHYs
Richard Retanubun
RichardRetanubun at RuggedCom.com
Wed Jul 1 20:05:04 CEST 2009
From 3aa39a9788c020b2192f44132d310b22e7c866a4 Mon Sep 17 00:00:00 2001
From: Richard Retanubun <RichardRetanubun at RuggedCom.com>
Date: Wed, 17 Jun 2009 16:00:41 -0400
Subject: [PATCH] 83xx: UEC: Added support for bitBang MII driver access to PHYs
This patch enabled support for having PHYs on bitBang MII and uec MII
operating at the same time. Modeled after the MPC8360ADS implementation
and added the ability to specify which ethernet interfaces have bitbang
SMI on the board header file.
---
drivers/net/phy/miiphybb.c | 28 ++++++++++++++++++++-----
drivers/net/phy/miiphybb.h | 26 +++++++++++++++++++++++
drivers/qe/uec.c | 6 +---
drivers/qe/uec_phy.c | 48 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 98 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/phy/miiphybb.h
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index e3c163a..1a15707 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -29,6 +29,7 @@
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
+#include "miiphybb.h"
/*****************************************************************************
*
@@ -38,8 +39,13 @@
static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
/*
@@ -123,8 +129,13 @@ int bb_miiphy_read (char *devname, unsigned char addr,
{
short rdreg; /* register working value */
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
miiphy_pre (1, addr, reg);
@@ -190,8 +201,13 @@ int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value)
{
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \
+ && !defined(CONFIG_MPC83XX)
+ volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
+#elif defined(CONFIG_MPC83XX)
+ volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+ volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio;
+ volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]);
#endif
miiphy_pre (0, addr, reg);
diff --git a/drivers/net/phy/miiphybb.h b/drivers/net/phy/miiphybb.h
new file mode 100644
index 0000000..4fff40d
--- /dev/null
+++ b/drivers/net/phy/miiphybb.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2006-2009 RuggedCom, Inc.
+ *
+ * Richard Retanubun <richardretanubun at ruggedcom.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+int bb_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value);
+
+int bb_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value);
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index 63fede9..a9bac99 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -579,8 +579,7 @@ static void phy_change(struct eth_device *dev)
adjust_link(dev);
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /*&& !defined(BITBANGMII)*/
/*
* Find a device index from the devlist by name
@@ -1383,8 +1382,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info)
return err;
}
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* && !defined(CONFIG_BITBANGMII) */
miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
#endif
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index aa4eb5e..63b5959 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -25,6 +25,7 @@
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
+#include "../net/phy/miiphybb.h"
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
@@ -93,6 +94,27 @@ static const struct fixed_phy_port fixed_phy_port[] = {
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
+/*--------------------------------------------------------------------+
+ * BitBang MII support for ethernet ports
+ *
+ * Based from MPC8560ADS implementation
+ *--------------------------------------------------------------------*/
+/*
+ * Example board header file to define bitbang ethernet ports:
+ *
+ * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
+ * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("FSL UEC0")
+*/
+#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
+#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
+#endif
+
+#if defined(CONFIG_BITBANGMII)
+static const char *bitbang_phy_port[] = {
+ CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
+};
+#endif /* CONFIG_BITBANGMII */
+
static void config_genmii_advert (struct uec_mii_info *mii_info);
static void genmii_setup_forced (struct uec_mii_info *mii_info);
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
@@ -113,6 +135,19 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
+
+#if defined(CONFIG_BITBANGMII)
+ u8 i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+ if (strncmp(dev->name, bitbang_phy_port[i],
+ strlen(dev->name)) == 0) {
+ (void)bb_miiphy_write(NULL, mii_id, regnum, value);
+ return;
+ }
+ }
+#endif /* CONFIG_BITBANGMII */
+
ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
@@ -140,6 +175,19 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
u32 tmp_reg;
u16 value;
+
+#if defined(CONFIG_BITBANGMII)
+ u8 i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
+ if (strncmp(dev->name, bitbang_phy_port[i],
+ strlen(dev->name)) == 0) {
+ (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
+ return (value);
+ }
+ }
+#endif /* CONFIG_BITBANGMII */
+
ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
--
1.6.2.4
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