[U-Boot] [PATCH 1/3] arm: Added support for MB86R01 'Jade' SoC

Matthias Weisser matthias.weisser at graf-syteco.de
Wed Jul 8 09:47:05 CEST 2009


This patch adds support for MB86R01 'Jade' SoC from Fujitsu

Signed-off-by: Matthias Weisser <matthias.weisser at graf-syteco.de>
---
 cpu/arm926ejs/jade/Makefile          |   47 +++++++++
 cpu/arm926ejs/jade/timer.c           |  126 ++++++++++++++++++++++++
 include/asm-arm/arch-jade/hardware.h |   31 ++++++
 include/asm-arm/arch-jade/jade.h     |  177 ++++++++++++++++++++++++++++++++++
 4 files changed, 381 insertions(+), 0 deletions(-)
 create mode 100644 cpu/arm926ejs/jade/Makefile
 create mode 100644 cpu/arm926ejs/jade/timer.c
 create mode 100644 include/asm-arm/arch-jade/hardware.h
 create mode 100644 include/asm-arm/arch-jade/jade.h

diff --git a/cpu/arm926ejs/jade/Makefile b/cpu/arm926ejs/jade/Makefile
new file mode 100755
index 0000000..7da9f40
--- /dev/null
+++ b/cpu/arm926ejs/jade/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).a
+
+COBJS	= timer.o
+SOBJS	=
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm926ejs/jade/timer.c b/cpu/arm926ejs/jade/timer.c
new file mode 100755
index 0000000..2d262c8
--- /dev/null
+++ b/cpu/arm926ejs/jade/timer.c
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop at leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Matthias Weisser <matthias.weisser at graf-syteco.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <div64.h>
+
+#define TIMER_LOAD_VAL 0xffffffff
+#define TIMER_BASE     0xfffe0000
+
+#define READ_TIMER (*(volatile ulong *)(TIMER_BASE+4))
+#define TIMER_FREQ     (CONFIG_JADE_IOCLK  / 16)
+
+static ulong timestamp;
+static ulong lastdec;
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ);
+
+	return tick;
+}
+
+static inline unsigned long long usec_to_tick(unsigned long long usec)
+{
+	usec *= TIMER_FREQ;
+	do_div(usec, 1000000);
+
+	return usec;
+}
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init(void)
+{
+	*(volatile ulong *)(TIMER_BASE + 0) = TIMER_LOAD_VAL;
+	*(volatile ulong *)(TIMER_BASE + 8) = 0x86;
+
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = READ_TIMER;
+
+	if (now <= lastdec)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (lastdec - now);
+	else			/* we have rollover of incrementer */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	lastdec = now;
+	return timestamp;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;	/* capture current decrement value time */
+	timestamp = 0;			/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+	return tick_to_time(get_ticks());
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = usec_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/include/asm-arm/arch-jade/hardware.h b/include/asm-arm/arch-jade/hardware.h
new file mode 100755
index 0000000..79b35f1
--- /dev/null
+++ b/include/asm-arm/arch-jade/hardware.h
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2007
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs at mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/jade.h>
+
+#endif
diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h
new file mode 100755
index 0000000..c2b28a2
--- /dev/null
+++ b/include/asm-arm/arch-jade/jade.h
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2007
+ *
+ * jade definitions
+ *
+ * Author : Carsten Schneider, mycable GmbH
+ *          <cs at mycable.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef JADE_H
+#define JADE_H
+
+typedef	volatile unsigned int	JREG;	/* Hardware register definition */
+
+/*
+ * Physical Address Defines
+ */
+#define JADE_GDC_PHYS_BASE	0xf1fc0000		/* GDC phys */
+#define JADE_GDC_PHYS_DISP_BASE	0xf1fd0000		/* GDC DisplayBase phys */
+#define JADE_CCNT_PHYS_BASE	0xfff42000		/* Chip Control Module */
+#define JADE_CAN0_PHYS_BASE	0xfff54000		/* CAN 0 phys */
+#define JADE_CAN1_PHYS_BASE	0xfff55000		/* CAN 1 phys */
+#define JADE_I2C0_PHYS_BASE	0xfff56000		/* I2C 0 phys */
+#define JADE_I2C1_PHYS_BASE	0xfff57000		/* I2C 1 phys */
+#define JADE_EHCI_PHYS_BASE	0xfff80000		/* EHCI phys */
+#define JADE_OHCI_PHYS_BASE	0xfff81000		/* OHCI phys */
+#define JADE_IRC1_PHYS_BASE	0xfffb0000		/* Jade cascaded Interrupt Controller phys */
+#define JADE_TIMER_PHYS_BASE	0xfffe0000		/* Counter/Timers JADE phys */
+#define JADE_UART0_PHYS_BASE	0xfffe1000		/* UART 0 phys */
+#define JADE_UART1_PHYS_BASE	0xfffe2000		/* UART 1 phys */
+#define JADE_IRCE_PHYS_BASE	0xfffe4000		/* Extended Interrupt Controller */
+#define JADE_CRG_PHYS_BASE	0xfffe7000		/* Clock Reset Generator */
+#define JADE_IRC0_PHYS_BASE	0xfffe8000		/* Jade Interrupt Controller phys */
+#define JADE_GPIO_PHYS_BASE	0xfffe9000		/* GPIO phys */
+
+
+/* -------- DRAMC_DRIC : (DRAMC Offset: 0x0) DRAM Controller Mode Register --------  */
+
+/********************************************************************************
+ *              REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL                *
+ ********************************************************************************/
+#define JREGC_DRAMC_DRIC	((JREG *) 0xF3000000)	/* DRAM Controller Initialization control register */
+#define	JREGC_DRAMC_DRIC1	((JREG *) 0xF3000002)	/* DRAM Controller Init control command register 1 */
+#define	JREGC_DRAMC_DRIC2	((JREG *) 0xF3000004)	/* DRAM Controller Init control command register 2 */
+#define	JREGC_DRAMC_DRCA	((JREG *) 0xF3000006)	/* DRAM Controller Address control register */
+#define	JREGC_DRAMC_DRCM 	((JREG *) 0xF3000008)	/* DRAM Controller Modal control register */
+#define	JREGC_DRAMC_DRCST1	((JREG *) 0xF300000A)	/* DRAM Controller Timing setting register 1 */
+#define	JREGC_DRAMC_DRCST2	((JREG *) 0xF300000C)	/* DRAM Controller Timing setting register 2 */
+#define	JREGC_DRAMC_DRCR	((JREG *) 0xF300000E)	/* DRAM Controller Refresh control register */
+#define JREGC_DRAMC_DRCS	((JREG *) 0xF3000020)	/* DRAM Controller Status control register */
+#define JREGC_DRAMC_DRASR	((JREG *) 0xF3000030)	/* DRAM Controller AXI operation setting register */
+#define JREGC_DRAMC_DRIMS1	((JREG *) 0xF3000042)	/* DRAM Controller IF control register 1 */
+#define JREGC_DRAMC_DRIMS2A1	((JREG *) 0xF3000044)	/* DRAM Controller IF control register 2 */
+#define JREGC_DRAMC_DRIMS3A2	((JREG *) 0xF3000046)	/* DRAM Controller IF control register 3 */
+#define JREGC_DRAMC_DRIMS4	((JREG *) 0xF3000048)	/* DRAM Controller IF control register 4 */
+#define JREGC_DRAMC_DRIMS5	((JREG *) 0xF300004A)	/* DRAM Controller IF control register 5 */
+#define JREGC_DRAMC_DRIMS6	((JREG *) 0xF300004C)	/* DRAM Controller IF control register 6 */
+#define JREGC_DRAMC_DRIMS7D1	((JREG *) 0xF300004E)	/* DRAM Controller IF control register 7 */
+#define JREGC_DRAMC_DRIMS8D2	((JREG *) 0xF3000050)	/* DRAM Controller IF control register 8 */
+#define JREGC_DRAMC_DRIMS9T1	((JREG *) 0xF3000052)	/* DRAM Controller IF control register 9 */
+#define JREGC_DRAMC_DRIMSS10T2	((JREG *) 0xF3000054)	/* DRAM Controller IF control register 10 */
+#define JREGC_DRAMC_DROS	((JREG *) 0xF3000060)	/* DRAM Controller ODT setting register */
+#define JREGC_DRAMC_DRIBSLI	((JREG *) 0xF3000062)	/* DRAM Controller IO LOOPBACK setting register */
+#define JREGC_DRAMC_DRIBSODT1	((JREG *) 0xF3000064)	/* DRAM Controller IO ODT1 setting register */
+#define JREGC_DRAMC_DRIBSOCD	((JREG *) 0xF3000066)	/* DRAM Controller IO OCD setting register */
+#define JREGC_DRAMC_DRIBSOCD2	((JREG *) 0xF3000068)	/* DRAM Controller IO OCD2 setting register */
+#define JREGC_DRAMC_DROABA	((JREG *) 0xF3000070)	/* DRAM Controller ODT bias self adjustment register */
+#define JREGC_DRAMC_DROBV	((JREG *) 0xF3000080)	/* DRAM Controller ODT bias value register */
+#define JREGC_DRAMC_DROBS	((JREG *) 0xF3000084)	/* DRAM Controller ODT bias selection register */
+#define JREGC_DRAMC_DROBSR1	((JREG *) 0xF3000086)	/* DRAM Controller ODT bias setting register 1 */
+#define JREGC_DRAMC_DROBSR2	((JREG *) 0xF3000088)	/* DRAM Controller ODT bias setting register 2 */
+#define JREGC_DRAMC_DROBSR3	((JREG *) 0xF300008A)	/* DRAM Controller ODT bias setting register 3 */
+#define JREGC_DRAMC_DROBSR4	((JREG *) 0xF300008C)	/* DRAM Controller ODT bias setting register 4 */
+#define JREGC_DRAMC_DRIMR1	((JREG *) 0xF3000090)	/* DRAM Controller IO monitor register 1 */
+#define JREGC_DRAMC_DRIMR2	((JREG *) 0xF3000092)	/* DRAM Controller IO monitor register 2 */
+#define JREGC_DRAMC_DRIMR3	((JREG *) 0xF3000094)	/* DRAM Controller IO monitor register 3 */
+#define JREGC_DRAMC_DRIMR4	((JREG *) 0xF3000096)	/* DRAM Controller IO monitor register 4 */
+#define JREGC_DRAMC_DROISR1	((JREG *) 0xF3000098)	/* DRAM Controller OCD impedance setting register 1 */
+#define JREGC_DRAMC_DROISR2	((JREG *) 0xF300009A)	/* DRAM Controller OCD impedance setting register 2 */
+
+/******************************************************************************
+ *              REGISTER ADDRESS DEFINITION FOR GPIO PERIPHERAL               *
+ ******************************************************************************/
+/* GPIO Port data register */
+#define GPIO_PORT_DATA		0x00
+/* GPIO Data Direction */
+#define GPIO_DIRECTION		0x10
+
+/* GPIO Block Defines */
+#define GPIO_BLOCK_0		0x00
+#define GPIO_BLOCK_1		0x04
+#define GPIO_BLOCK_2		0x08
+
+/* ------------------------------------------------------------------------
+ *  JADE Chip Control Module
+ * ------------------------------------------------------------------------
+ */
+
+#define CCNT_CGPIO_IST	0x18	/* GPIO interrupt status register */
+#define CCNT_CGPIO_ISTM	0x1c	/* GPIO interrupt status mask register */
+#define CCNT_CGPIO_IP	0x20	/* GPIO interrupt polarity setting register */
+#define CCNT_CGPIO_IM	0x24	/* GPIO interrupt mode setting register */
+#define CCNT_CMUX_MD	0x30	/* MultiplexMode setting register */
+
+/********************************************************************************
+ *              REGISTER ADDRESS DEFINITION FOR UART0 PERIPHERAL                *
+ ********************************************************************************/
+#define JREGC_UART0_URT0RFR	((JREG *) 0xFFFE1000)	/* UART0 Reception FIFO register */
+#define JREGC_UART0_URT0TFR	((JREG *) 0xFFFE1000)	/* UART0 Transmission register */
+#define JREGC_UART0_URT0DLL	((JREG *) 0xFFFE1000)	/* UART0 Dividing value */
+#define JREGC_UART0_URT0IER	((JREG *) 0xFFFE1004)	/* UART0 DLAB=0: Interrupt enable register */
+#define JREGC_UART0_URT0DLM	((JREG *) 0xFFFE1004)	/* UART0 DLAB=1: Dividing value (upper byte) */
+#define JREGC_UART0_URT0IIR	((JREG *) 0xFFFE1008)	/* UART0 Interrupt ID register (read only) */
+#define JREGC_UART0_URT0FCR	((JREG *) 0xFFFE1008)	/* UART0 FIFO control register (write only) */
+#define JREGC_UART0_URT0LCR	((JREG *) 0xFFFE100C)	/* UART0 Line control register */
+#define JREGC_UART0_URT0MCR	((JREG *) 0xFFFE1010)	/* UART0 Modem control register */
+#define JREGC_UART0_URT0LSR	((JREG *) 0xFFFE1014)	/* UART0 Line status register */
+#define JREGC_UART0_URT0MSR	((JREG *) 0xFFFE1018)	/* UART0 Modem status register */
+#define JREGC_UART0_URT0SCR	((JREG *) 0xFFFE101C)	/* UART0 Scratch register (At DLAB=0) */
+
+/********************************************************************************
+ *              REGISTER ADDRESS DEFINITION FOR UART1 PERIPHERAL                *
+ ********************************************************************************/
+#define JREGC_UART1_URT1RFR	((JREG *) 0xFFFE2000)	/* UART1 Reception FIFO register */
+#define JREGC_UART1_URT1TFR	((JREG *) 0xFFFE2000)	/* UART1 Transmission register */
+#define JREGC_UART1_URT1DLL	((JREG *) 0xFFFE2000)	/* UART1 Dividing value */
+#define JREGC_UART1_URT1IER	((JREG *) 0xFFFE2004)	/* UART1 DLAB=0: Interrupt enable register */
+#define JREGC_UART1_URT1DLM	((JREG *) 0xFFFE2004)	/* UART1 DLAB=1: Dividing value (upper byte) */
+#define JREGC_UART1_URT1IIR	((JREG *) 0xFFFE2008)	/* UART1 Interrupt ID register (read only) */
+#define JREGC_UART1_URT1FCR	((JREG *) 0xFFFE2008)	/* UART1 FIFO control register (write only) */
+#define JREGC_UART1_URT1LCR	((JREG *) 0xFFFE200C)	/* UART1 Line control register */
+#define JREGC_UART1_URT1MCR	((JREG *) 0xFFFE2010)	/* UART1 Modem control register */
+#define JREGC_UART1_URT1LSR	((JREG *) 0xFFFE2014)	/* UART1 Line status register */
+#define JREGC_UART1_URT1MSR	((JREG *) 0xFFFE2018)	/* UART1 Modem status register */
+#define JREGC_UART1_URT1SCR	((JREG *) 0xFFFE201C)	/* UART1 Scratch register (At DLAB=0) */
+
+/********************************************************************************
+ *              REGISTER ADDRESS DEFINITION FOR CLOCK/RESET INTERFACE           *
+ ********************************************************************************/
+#define JREGC_CRG_CRPR		((JREG *) 0xFFFE7000)	/* CRG PLL control register */
+#define JREGC_CRG_CRWR		((JREG *) 0xFFFE7008)	/* CRG Watchdog timer control register */
+#define JREGC_CRG_CRSR		((JREG *) 0xFFFE700C)	/* CRG Reset/standby control register */
+#define JREGC_CRG_CRDA		((JREG *) 0xFFFE7010)	/* CRG Clock divider control register A */
+#define JREGC_CRG_CRDB		((JREG *) 0xFFFE7014)	/* CRG Clock divider control register B */
+#define JREGC_CRG_CRHA		((JREG *) 0xFFFE7018)	/* CRG (AHB(A) bus) bus clock gate control register */
+#define JREGC_CRG_CRPA		((JREG *) 0xFFFE701C)	/* CRG (APB(A) bus) bus clock gate control register */
+#define JREGC_CRG_CRPB		((JREG *) 0xFFFE7020)	/* CRG (APB(B) bus) bus clock gate control register */
+#define JREGC_CRG_CRHB		((JREG *) 0xFFFE7024)	/* CRG (AHB(B) bus) bus clock gate control register */
+#define JREGC_CRG_CRAM		((JREG *) 0xFFFE7028)	/* CRG ARM core clock gate control register */
+
+/********************************************************************************
+ *              REGISTER BASE ADDRESS DEFINITION FOR PERIPHERAL                 *
+ ********************************************************************************/
+#define JREGC_BASE_DRAM		((JREGPS_DRAMC)	0xF3000000)	/* (DRAMC) Base Address */
+#define JREGC_BASE_GPIO		((JREGPS_GPIO)  0xFFFE9000)	/* (GPIO)  Base Address */
+#define JREGC_BASE_UART0	((JREGPS_UART0) 0xFFFE1000)	/* (UART0)  Base Address */
+#define JREGC_BASE_UART1	((JREGPS_UART1) 0xFFFE2000)	/* (UART1)  Base Address */
+
+#endif /* jade_H */
-- 
1.5.6.3



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