[U-Boot] [PATCH-ARM] Add support for Embest SBC2440-II Board 7/7

[Jean-Christophe PLAGNIOL-VILLARD]

> + * Modified for the Samsung SMDK2410 by
> + * (C) Copyright 2002
> + * David Mueller, ELSOFT AG, <d.mueller at elsoft.ch>
> + *
> + * Modified for the friendly-arm SBC-2410X by
> + * (C) Copyright 2005
> + * JinHua Luo, GuangDong Linux Center, <luo.jinhua at gd-linux.com>
> + *
> + * Modified for the Embest SBC2440-II by
> + * (C) Copyright 2009
> + * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt at fearnside-systems.co.uk>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +
> +/*
> + * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
> + *
> + * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar at sec.samsung.com>
> + */
> +
> +#define BWSCON		0x48000000
> +
> +#define DW8		(0x0)
> +#define DW16		(0x1)
> +#define DW32		(0x2)
> +#define WAIT		(0x1 << 2)
> +#define UBLB		(0x1 << 3)
> +
> +#define B1_BWSCON	(DW16)
> +#define B2_BWSCON	(DW16)
> +#define B3_BWSCON	(DW16 + WAIT + UBLB)
> +#define B4_BWSCON	(DW16)
> +#define B5_BWSCON	(DW16)
> +#define B6_BWSCON	(DW32)
> +#define B7_BWSCON	(DW32)
> +#define BWSCON_VAL	((B1_BWSCON <<  4) + (B2_BWSCON <<  8) + \
> +			(B3_BWSCON << 12) + (B4_BWSCON << 16) + \
> +			(B5_BWSCON << 20) + (B6_BWSCON << 24) + \
> +			(B7_BWSCON << 28))
> +
> +#define B0_TACS		0x0
> +#define B0_TCOS		0x0
> +#define B0_TACC		0x7
> +#define B0_TCOH		0x0
> +#define B0_TAH		0x0
> +#define B0_TACP		0x0
> +#define B0_PMC		0x0
> +#define BANKCON0_VAL	((B0_TACS << 13) + (B0_TCOS << 11) + (B0_TACC <<  8) + \
> +			(B0_TCOH <<  6) + (B0_TAH  <<  4) + (B0_TACP <<  2) + \
> +			B0_PMC)
> +
> +#define B1_TACS		0x0
> +#define B1_TCOS		0x0
> +#define B1_TACC		0x7
> +#define B1_TCOH		0x0
> +#define B1_TAH		0x0
> +#define B1_TACP		0x0
> +#define B1_PMC		0x0
> +#define BANKCON1_VAL	((B1_TACS << 13) + (B1_TCOS << 11) + (B1_TACC <<  8) + \
> +			(B1_TCOH <<   6) + (B1_TAH  <<  4) + (B1_TACP <<  2) + \
> +			B1_PMC)
> +
> +#define B2_TACS		0x0
> +#define B2_TCOS		0x0
> +#define B2_TACC		0x7
> +#define B2_TCOH		0x0
> +#define B2_TAH		0x0
> +#define B2_TACP		0x0
> +#define B2_PMC		0x0
> +#define BANKCON2_VAL	((B2_TACS << 13) + (B2_TCOS << 11) + (B2_TACC << 8) + \
> +			(B2_TCOH <<  6) + (B2_TAH  <<  4) + (B2_TACP << 2) + \
> +			B2_PMC)
> +
> +#define B3_TACS		0x0	/* 0clk */
> +#define B3_TCOS		0x3	/* 4clk */
> +#define B3_TACC		0x7	/* 14clk */
> +#define B3_TCOH		0x1	/* 1clk */
> +#define B3_TAH		0x3	/* 4clk */
> +#define B3_TACP		0x3	/* 6clk */
> +#define B3_PMC		0x0	/* 16data */
> +#define BANKCON3_VAL	((B3_TACS << 13) + (B3_TCOS << 11) + (B3_TACC << 8) + \
> +			(B3_TCOH <<  6) + (B3_TAH  <<  4) + (B3_TACP << 2) + \
> +			B3_PMC)
> +
> +#define B4_TACS		0x0
> +#define B4_TCOS		0x0
> +#define B4_TACC		0x7
> +#define B4_TCOH		0x0
> +#define B4_TAH		0x0
> +#define B4_TACP		0x0
> +#define B4_PMC		0x0
> +#define BANKCON4_VAL	((B4_TACS << 13) + (B4_TCOS << 11) + (B4_TACC << 8) + \
> +			(B4_TCOH <<  6) + (B4_TAH  <<  4) + (B4_TACP << 2) + \
> +			B4_PMC)
> +
> +#define B5_TACS		0x0
> +#define B5_TCOS		0x0
> +#define B5_TACC		0x7
> +#define B5_TCOH		0x0
> +#define B5_TAH		0x0
> +#define B5_TACP		0x0
> +#define B5_PMC		0x0
> +#define BANKCON5_VAL	((B5_TACS << 13) + (B5_TCOS << 11) + (B5_TACC << 8) + \
> +			(B5_TCOH <<  6) + (B5_TAH  <<  4) + (B5_TACP << 2) + \
> +			B5_PMC)
> +
> +#define B6_MT		0x3	/* SDRAM */
> +#define B6_TRCD		0x2
> +#define B6_SCAN		0x1	/* 9bit */
> +#define BANKCON6_VAL	((B6_MT << 15) + (B6_TRCD << 2) + B6_SCAN)
> +
> +#define B7_MT		0x3	/* SDRAM */
> +#define B7_TRCD		0x2	/* 4clk */
> +#define B7_SCAN		0x1	/* 9bit */
> +#define BANKCON7_VAL	((B7_MT << 15) + (B7_TRCD << 2) + B7_SCAN)
> +
> +/* REFRESH parameter */
> +#define REFEN		0x1	/* Refresh enable */
> +#define TREFMD		0x0	/* CBR(CAS before RAS)/Auto refresh */
> +#define TRP		0x0	/* 2clk */
> +#define TRC		0x3	/* 7clk */
> +#define TCHR		0x2	/* 3clk */
> +#define REFCNT		1259
> +#define REFRESH_VAL	((REFEN << 23) + (TREFMD << 22) + (TRP << 20) + \
> +			(TRC   << 18) + (TCHR   << 16) + REFCNT)
> +
> +/* BANKSIZE parameter */
> +#define BURST_EN	1	/* Enable burst mode */
> +#define SCKE_EN		1	/* Enable SDRAM power-down mode */
> +#define SCLK_EN		1	/* SCLK is active only during the access */
> +#define BK67MAP		2	/* 128M/128M */
> +#define BANKSIZE_VAL	((BURST_EN << 7) + (SCKE_EN << 5) + \
> +			(SCLK_EN  << 4) + BK67MAP)
> +
> +/* MRSRB6 parameter */
> +#define WBL6		0	/* Burst */
> +#define TM6		0	/* Modem register set */
> +#define CL6		3	/* Latency is 3 clocks */
> +#define BT6		0	/* Sequential */
> +#define BL6		0
> +#define MRSRB6_VAL	((WBL6 << 9) + (TM6 << 7) + (CL6 << 4) + \
> +			(BT6  << 3) + BL6)
> +
> +/* MRSRB7 parameter */
> +#define WBL7		0	/* Burst */
> +#define TM7		0	/* Modem register set */
> +#define CL7		3	/* Latency is 3 clocks */
> +#define BT7		0	/* Sequential */
> +#define BL7		0
> +#define MRSRB7_VAL	((WBL7 << 9) + (TM7 << 7) + (CL7 << 4) + \
> +			(BT7 << 3) + BL7)
please clean this define
please make then more generic
by moving soc macro to a propoper header and board config
to board config header

Best Regards,
J.