[U-Boot] [PATCH V2] ppc4xx: Add 405EP based PMC405DE board

[Wolfgang Denk]

Dear Matthias Fuchs,

In message <4A61E62E.3030001 at esd.eu> you wrote:
> 
> Do you want to see something like this (see below)?

Basicly yes, but see comments below.

> I ran into the problem that include/ppc405.h defines a macro "tcr".
> This conflicts with tcr in my gpio_controller struct.

Indeed - this is one of the resons we sreally should clean this up.

> I hope you do make adding PMC405DE board support dependant from
> fixing all casts with io accessor macros :-(

If you really like and kindly ask for it, we can certainly do that :-)
[Or did was a "not" missing somewhere in this sentence? :-) ]

> index 9c1a119..789e326 100644
> --- a/board/esd/pmc405de/pmc405de.c
> +++ b/board/esd/pmc405de/pmc405de.c
> @@ -26,10 +26,20 @@
>   #include <fdt_support.h>
>   #include <asm/processor.h>
>   #include <asm/io.h>
> +#include <asm/gpio.h>
>   #include <asm/4xx_pci.h>
>   #include <command.h>
>   #include <malloc.h>

Patch is white space corrupted.

> +struct pmc405de_cpld {
> +	u8 version;
> +	u8 reserved0[3];
> +	u8 status;
> +	u8 reserved1[3];
> +	u8 control;
> +	u8 reserved2[3];
> +};

Are you sure these are 8 bit registers?

And some comments would be nice, too.

> -		out_be32((void*)GPIO0_OR,
> -			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO_EREADY);
> -		out_be32((void*)GPIO0_TCR,
> -			 in_be32((void*)GPIO0_TCR) | CONFIG_SYS_GPIO_EREADY);
> +		out_be32(&gpio0->or,
> +			 in_be32(&gpio0->or) | CONFIG_SYS_GPIO_EREADY);
> +		out_be32(&gpio0->_tcr,
> +			 in_be32(&gpio0->_tcr) | CONFIG_SYS_GPIO_EREADY);

Something is wrong here- either it's 8 bit registers, nd you should
use 8 bit accessor functions, or it's 32 bit in both cases.

And instead of
		out_be32(&gpio0->or,
			 in_be32(&gpio0->or) | CONFIG_SYS_GPIO_EREADY);
you better use
		setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY);

[See also clrbits_*() and clrsetbits_*()]

> +/* GPIO controller */
> +struct ppc4xx_gpio_controller {
> +	u32 or;
> +	u32 _tcr;
> +	u32 osl;
> +	u32 osh;
> +	u32 tsl;
> +	u32 tsh;
> +	u32 odr;
> +	u32 ir;
> +	u32 rr1;
> +	u32 rr2;
> +	u32 rr3;
> +	u32 reserved;
> +	u32 is1l;
> +	u32 is1h;
> +	u32 is2l;
> +	u32 is2h;
> +	u32 is3l;
> +	u32 is3h;
> +};

Some comments might be helpful here, too.

Best regards,

Wolfgang Denk

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