[U-Boot] [PATCH] This patch adds support for Fujitsu MB86R01 'JADE' SOC

[Wolfgang Denk]

Dear Matthias Weisser,

In message <1246368064-4957-1-git-send-email-matthias.weisser at graf-syteco.de> you wrote:
> Signed-off-by: Matthias Weisser <matthias.weisser at graf-syteco.de>
> ---
>  cpu/arm926ejs/jade/Makefile          |   47 +++++++++
>  cpu/arm926ejs/jade/timer.c           |  129 ++++++++++++++++++++++++
>  include/asm-arm/arch-jade/hardware.h |   31 ++++++
>  include/asm-arm/arch-jade/jade.h     |  182 ++++++++++++++++++++++++++++++++++
>  4 files changed, 389 insertions(+), 0 deletions(-)
>  create mode 100755 cpu/arm926ejs/jade/Makefile
>  create mode 100755 cpu/arm926ejs/jade/timer.c
>  create mode 100755 include/asm-arm/arch-jade/hardware.h
>  create mode 100755 include/asm-arm/arch-jade/jade.h

Entries to MAKEALL and MAINTAINERS are missing.

> diff --git a/include/asm-arm/arch-jade/jade.h b/include/asm-arm/arch-jade/jade.h
> new file mode 100755
> index 0000000..0ab96e1
> --- /dev/null
> +++ b/include/asm-arm/arch-jade/jade.h
...
> +typedef	volatile unsigned int	JREG;	/* Hardware register definition */

You don't need this. We don't use register accesses, but I/O accessor
functions.

> +/*
> + * Physical Address Defines
> + */
> +#define JADE_GDC_PHYS_BASE	0xf1fc0000		/* GDC phys */
> +#define JADE_GDC_PHYS_DISP_BASE	0xf1fd0000		/* GDC DisplayBase phys */
> +#define JADE_CCNT_PHYS_BASE	0xfff42000		/* Chip Control Module */
> +#define JADE_CAN0_PHYS_BASE	0xfff54000		/* CAN 0 phys */
> +#define JADE_CAN1_PHYS_BASE	0xfff55000		/* CAN 1 phys */
> +#define JADE_I2C0_PHYS_BASE	0xfff56000		/* I2C 0 phys */
> +#define JADE_I2C1_PHYS_BASE	0xfff57000		/* I2C 1 phys */
> +#define JADE_EHCI_PHYS_BASE	0xfff80000		/* EHCI phys */
> +#define JADE_OHCI_PHYS_BASE	0xfff81000		/* OHCI phys */
> +#define JADE_IRC1_PHYS_BASE	0xfffb0000		/* Jade cascaded Interrupt Controller phys */
> +#define JADE_TIMER_PHYS_BASE	0xfffe0000		/* Counter/Timers JADE phys */
> +#define JADE_UART0_PHYS_BASE	0xfffe1000		/* UART 0 phys */
> +#define JADE_UART1_PHYS_BASE	0xfffe2000		/* UART 1 phys */
> +#define JADE_IRCE_PHYS_BASE	0xfffe4000		/* Extended Interrupt Controller */
> +#define JADE_CRG_PHYS_BASE	0xfffe7000		/* Clock Reset Generator */
> +#define JADE_IRC0_PHYS_BASE	0xfffe8000		/* Jade Interrupt Controller phys */
> +#define JADE_GPIO_PHYS_BASE	0xfffe9000		/* GPIO phys */
> +
> +
> +/* -------- DRAMC_DRIC : (DRAMC Offset: 0x0) DRAM Controller Mode Register --------  */
> +
> +/********************************************************************************
> + *              REGISTER ADDRESS DEFINITION FOR DRAMC PERIPHERAL                *
> + ********************************************************************************/
> +#define JREGC_DRAMC_DRIC	((JREG *) 0xF3000000)	/* DRAM Controller Initialization control register */
> +#define	JREGC_DRAMC_DRIC1	((JREG *) 0xF3000002)	/* DRAM Controller Init control command register 1 */
> +#define	JREGC_DRAMC_DRIC2	((JREG *) 0xF3000004)	/* DRAM Controller Init control command register 2 */
> +#define	JREGC_DRAMC_DRCA	((JREG *) 0xF3000006)	/* DRAM Controller Address control register */
> +#define	JREGC_DRAMC_DRCM 	((JREG *) 0xF3000008)	/* DRAM Controller Modal control register */
> +#define	JREGC_DRAMC_DRCST1	((JREG *) 0xF300000A)	/* DRAM Controller Timing setting register 1 */
> +#define	JREGC_DRAMC_DRCST2	((JREG *) 0xF300000C)	/* DRAM Controller Timing setting register 2 */
> +#define	JREGC_DRAMC_DRCR	((JREG *) 0xF300000E)	/* DRAM Controller Refresh control register */
> +#define JREGC_DRAMC_DRCS	((JREG *) 0xF3000020)	/* DRAM Controller Status control register */
> +#define JREGC_DRAMC_DRASR	((JREG *) 0xF3000030)	/* DRAM Controller AXI operation setting register */
> +#define JREGC_DRAMC_DRIMS1	((JREG *) 0xF3000042)	/* DRAM Controller IF control register 1 */
...

NAK.

We don't allow such a base address + offset approach. 

Please define C structs for the peripherals, and use I/O accessors.


Best regards,

Wolfgang Denk

-- 
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