[U-Boot] [PATCH V2] ppc4xx: use SPRN_TCR macro instead of tcr

[Matthias Fuchs]

This patch migrates 4xx code from using the lowercase tcr macro
to the SPRN_TCR macro. Both macros have been defined in the past.
So one is to much and uppercase macros are much more common.

The lowercase macro conflicts with the upcoming
introduction of the ppc4xx_gpio struct and it's tcr field.

Doing more such migration and getting rid of many defines from
include/ppc405.h and include/ppc440.h should be put on
our TODO list.

patch v2: better use SPRN_TCR instead of TCR

Signed-off-by: Matthias Fuchs <matthias.fuchs at esd.eu>
---
 cpu/ppc4xx/cpu_init.c   |    4 ++--
 cpu/ppc4xx/interrupts.c |    8 ++++----
 cpu/ppc4xx/start.S      |    2 +-
 include/ppc405.h        |    1 -
 include/ppc440.h        |    1 -
 5 files changed, 7 insertions(+), 9 deletions(-)

diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index bbd795d..58b23a0 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -248,7 +248,7 @@ cpu_init_f (void)
 #endif
 
 #if defined(CONFIG_WATCHDOG)
-	val = mfspr(tcr);
+	val = mfspr(SPRN_TCR);
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 	val |= 0xb8000000;      /* generate system reset after 1.34 seconds */
 #elif defined(CONFIG_440EPX)
@@ -260,7 +260,7 @@ cpu_init_f (void)
 	val &= ~0x30000000;			/* clear WRC bits */
 	val |= CONFIG_SYS_4xx_RESET_TYPE << 28;	/* set board specific WRC type */
 #endif
-	mtspr(tcr, val);
+	mtspr(SPRN_TCR, val);
 
 	val = mfspr(tsr);
 	val |= 0x80000000;      /* enable watchdog timer */
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 494bd8c..9883903 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -102,9 +102,9 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	 * Init PIT
 	 */
 #if defined(CONFIG_440)
-	val = mfspr( tcr );
+	val = mfspr( SPRN_TCR );
 	val &= (~0x04400000);		/* clear DIS & ARE */
-	mtspr( tcr, val );
+	mtspr( SPRN_TCR, val );
 	mtspr( dec, 0 );		/* Prevent exception after TSR clear*/
 	mtspr( decar, 0 );		/* clear reload */
 	mtspr( tsr, 0x08000000 );	/* clear DEC status */
@@ -126,9 +126,9 @@ int interrupt_init_cpu (unsigned *decrementer_count)
 	/*
 	 * Enable PIT
 	 */
-	val = mfspr(tcr);
+	val = mfspr(SPRN_TCR);
 	val |= 0x04400000;
-	mtspr(tcr, val);
+	mtspr(SPRN_TCR, val);
 
 	/*
 	 * Set EVPR to 0
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index 582c781..0476b5e 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -626,7 +626,7 @@ _start:
 	mtspr	tbl,r0			/* prevent fit & wdt exceptions */
 	mtspr	tbu,r0
 	mtspr	tsr,r1			/* clear all timer exception status */
-	mtspr	tcr,r0			/* disable all */
+	mtspr	SPRN_TCR,r0			/* disable all */
 	mtspr	esr,r0			/* clear exception syndrome register */
 	mtxer	r0			/* clear integer exception register */
 
diff --git a/include/ppc405.h b/include/ppc405.h
index 917afec..50fc7be 100644
--- a/include/ppc405.h
+++ b/include/ppc405.h
@@ -61,7 +61,6 @@
 	#define  dear  0x3d5	  /* data exeption address register */
 	#define  evpr  0x3d6	  /* exeption vector prefix register */
 	#define  tsr   0x3d8	  /* timer status register */
-	#define  tcr   0x3da	  /* timer control register */
 	#define  pit   0x3db	  /* programmable interval timer */
 	#define  sgr   0x3b9	  /* storage guarded reg      */
 	#define  dcwr  0x3ba	  /* data cache write-thru reg*/
diff --git a/include/ppc440.h b/include/ppc440.h
index 01f6eaf..df78eea 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -90,7 +90,6 @@
 #define	 dvc1	0x13e	/* data value compare 1 */
 #define	 dvc2	0x13f	/* data value compare 2 */
 #define	 tsr	0x150	/* timer status register */
-#define	 tcr	0x154	/* timer control register */
 #define	 ivor0	0x190	/* interrupt vector offset register 0 */
 #define	 ivor1	0x191	/* interrupt vector offset register 1 */
 #define	 ivor2	0x192	/* interrupt vector offset register 2 */
-- 
1.6.1