[U-Boot] MPC8360ERDK - DDR Controller and DDR2 Memory initialization/configuration

[cmfairfa at rockwellcollins.com]

Hi,
For the MPC8360ERDK, U-Boot configures the Micron DDR2 chips (in 
MPC8360ERDK.h) inconsistently with the chip's data sheet specifications 
(e.g., for the -3 speed grade part, the CAS Latency is specified to be 5, 
but the software uses 3).

I'm looking for any information/input as to how the DDR controller and 
DDR2 chip settings were derived since most of the settings don't match the 
chip's specifications. I notice that a lot of the U-Boot settings are 2 
clock cycles less than what is specified for the chip. Is this merely a 
coincedence or is there an "inherent" 2 clock cycle delay in the hardware?

Any help is greatly appreciated.


Thanks.



Christopher M. Fairfax
Sr. Software Engineer
Rockwell Collins
+1 540-428-3344
+1 540-428-3301
cmfairfa at rockwellcollins.com
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