[U-Boot] [PATCH] Added P1020 Processor Support.

[Wolfgang Denk]

Dear Poonam Aggrwal,

In message <1248963409-27098-1-git-send-email-poonam.aggrwal at freescale.com> you wrote:
> P1020 is another member of QorIQ series of processors which falls in ULE
> category.
> It is a scaled down version of P2020 with following differences from P2020:
> - 533MHz - 800MHz core frequency.
> - 256Kbyte L2 cache
> - Ethernet controllers with classification capabilities.
> Also the SOC is pin compatible with P2020
...
> diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
> index 8809302..eb52f55 100644
> --- a/cpu/mpc85xx/Makefile
> +++ b/cpu/mpc85xx/Makefile
> @@ -49,6 +49,7 @@ COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
>  COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
>  COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
>  COBJS-$(CONFIG_P2020)	+= ddr-gen3.o
> +COBJS-$(CONFIG_P1020)	+= ddr-gen3.o
>  COBJS-$(CONFIG_MPC8569)	+= ddr-gen3.o

Please keep this list sorted (and fix the P2020 misplacement, too).

> --- a/cpu/mpc8xxx/cpu.c
> +++ b/cpu/mpc8xxx/cpu.c
> @@ -66,6 +66,8 @@ struct cpu_type cpu_type_list [] = {
>  	CPU_TYPE_ENTRY(8572, 8572_E, 2),
>  	CPU_TYPE_ENTRY(P2020, P2020, 2),
>  	CPU_TYPE_ENTRY(P2020, P2020_E, 2),
> +	CPU_TYPE_ENTRY(P1020, P1020, 2),
> +	CPU_TYPE_ENTRY(P1020, P1020_E, 2),

Please keep sorted here, too.

> --- a/drivers/misc/fsl_law.c
> +++ b/drivers/misc/fsl_law.c
> @@ -39,7 +39,7 @@ DECLARE_GLOBAL_DATA_PTR;
>        defined(CONFIG_MPC8641) || defined(CONFIG_MPC8610)
>  #define FSL_HW_NUM_LAWS 10
>  #elif defined(CONFIG_MPC8536) || defined(CONFIG_MPC8572) || \
> -      defined(CONFIG_P2020)
> +      defined(CONFIG_P2020) || defined(P1020)

Ditto here.

> --- a/include/asm-ppc/processor.h
> +++ b/include/asm-ppc/processor.h
> @@ -963,6 +963,8 @@
>  #define SVR_8572_E	0x80E800
>  #define SVR_P2020	0x80E200
>  #define SVR_P2020_E	0x80EA00
> +#define SVR_P1020	0x80E400
> +#define SVR_P1020_E	0x80EC00

And here again.

Thanks.

Best regards,

Wolfgang Denk

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