[U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

[Bin Meng]

Hi Dipen,

On Thu, Oct 1, 2009 at 12:48 PM, Dudhat Dipen-B09055
<Dipen.Dudhat at freescale.com> wrote:
>
> Hi Bin,
>
> We can know the block transfer complete using IRQSTAT(Transfer
> Complete).
> But reading & writing in PIO mode takes time for byte by byte transfers
> and there is no way to poll that transfer, that's why I have added delay
> there.
>

Yes, I understand there is no such a register in Freescale eSDHC that
provides status check for PIO mode.
I am just wondering where the delay value 100 us comes from. Is it the
required minimum value?

> I can add comment like,
> \* Wait before last byte transfer complete *\
> Is that ok ??
>

Sure, adding a comment line would help a lot.

Regards,
Bin Meng