[U-Boot] [PATCH 1/5 v2] OMAP3: Fix SDRC init

[Nishanth Menon]

Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits

Signed-off-by: Nishanth Menon <nm at ti.com>
Cc: David B <david-b at pacbell.net>
Cc: Vikram Pandita <vikram.pandita at ti.com>
Cc: Richard Woodruff <r-woodruff2 at ti.com>
Cc: Sandeep Paulraj <s-paulraj at ti.com>
Cc: Tom Rix <tom.rix at windriver.com>
Cc: Dirk Behme <dirk.behme at googlemail.com>
---
 cpu/arm_cortexa8/omap3/mem.c     |    3 ++-
 include/asm-arm/arch-omap3/cpu.h |    1 +
 include/asm-arm/arch-omap3/mem.h |    8 ++++----
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 079c848..8731c9d 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -164,7 +164,8 @@ void do_sdrc_init(u32 cs, u32 early)
 		writel(SDP_SDRC_SHARING, &sdrc_base->sharing);
 
 		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
-		writel(SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
+		writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH,
+				&sdrc_base->power);
 
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h
index 8ab2e39..e51c4f3 100644
--- a/include/asm-arm/arch-omap3/cpu.h
+++ b/include/asm-arm/arch-omap3/cpu.h
@@ -222,6 +222,7 @@ struct sdrc {
 
 #define PAGEPOLICY_HIGH		(0x1 << 0)
 #define SRFRONRESET		(0x1 << 7)
+#define PWDNEN			(0x1 << 2)
 #define WAKEUPPROC		(0x1 << 26)
 
 #define DDR_SDRAM		(0x1 << 0)
diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h
index 5b9ac75..31cbdef 100644
--- a/include/asm-arm/arch-omap3/mem.h
+++ b/include/asm-arm/arch-omap3/mem.h
@@ -78,16 +78,16 @@ enum {
 #define TRP_165		3
 #define TRAS_165	7
 #define TRC_165		10
-#define TRFC_165	21
+#define TRFC_165	12
 #define V_ACTIMA_165	((TRFC_165 << 27) | (TRC_165 << 22) | \
 			(TRAS_165 << 18) | (TRP_165 << 15) |  \
 			(TRCD_165 << 12) | (TRRD_165 << 9) |  \
 			(TDPL_165 << 6) | (TDAL_165))
 
 #define TWTR_165	1
-#define TCKE_165	1
-#define TXP_165		5
-#define XSR_165		23
+#define TCKE_165	2
+#define TXP_165		2
+#define XSR_165		20
 #define V_ACTIMB_165	(((TCKE_165 << 12) | (XSR_165 << 0)) |	\
 			(TXP_165 << 8) | (TWTR_165 << 16))
 
-- 
1.6.0.4