[U-Boot] [PATCH] Add mpc5125ads board and processor to the mpc512x family

Martha Stan mmarx at silicontkx.com
Thu Oct 8 09:40:57 CEST 2009


Signed-off-by: Martha Stan <mmarx at silicontkx.com>
---
 MAINTAINERS                             |    5 +
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 board/freescale/mpc5125ads/Makefile     |   53 ++++
 board/freescale/mpc5125ads/config.mk    |   23 ++
 board/freescale/mpc5125ads/cpld.h       |   50 ++++
 board/freescale/mpc5125ads/mpc5125ads.c |  415 ++++++++++++++++++++++++++
 cpu/mpc512x/asm-offsets.h               |    6 +
 cpu/mpc512x/cpu.c                       |    3 +
 cpu/mpc512x/fixed_sdram.c               |    6 +
 cpu/mpc512x/iopin.c                     |   22 ++
 cpu/mpc512x/serial.c                    |   17 +-
 cpu/mpc512x/start.S                     |   15 +
 drivers/net/mpc512x_fec.c               |   51 +++-
 include/asm-ppc/immap_512x.h            |  285 +++++++++++++++++-
 include/configs/mpc5125ads.h            |  486 +++++++++++++++++++++++++++++++
 16 files changed, 1418 insertions(+), 23 deletions(-)
 create mode 100644 board/freescale/mpc5125ads/Makefile
 create mode 100644 board/freescale/mpc5125ads/config.mk
 create mode 100644 board/freescale/mpc5125ads/cpld.h
 create mode 100644 board/freescale/mpc5125ads/mpc5125ads.c
 create mode 100644 include/configs/mpc5125ads.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f42c8f0..b2eaa8d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -424,6 +424,11 @@ Jon Smirl <jonsmirl at gmail.com>
 
 	pcm030		MPC5200
 
+Martha Marx Stan <mmarx at silicontkx.com>
+
+	mpc5121ads	MPC5121E
+	mpc5125ads	MPC5125
+
 Timur Tabi <timur at freescale.com>
 
 	MPC8349E-mITX	MPC8349
diff --git a/MAKEALL b/MAKEALL
index 8ff6987..3e84356 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -91,6 +91,7 @@ LIST_512x="		\
 	aria		\
 	mecp5123	\
 	mpc5121ads	\
+	mpc5125ads	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 5857b52..a4ad8e7 100644
--- a/Makefile
+++ b/Makefile
@@ -844,6 +844,9 @@ mpc5121ads_rev2_config	\
 	fi
 	@$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale
 
+mpc5125ads_config:	unconfig
+	@$(MKCONFIG) -a mpc5125ads ppc mpc512x mpc5125ads freescale
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
diff --git a/board/freescale/mpc5125ads/Makefile b/board/freescale/mpc5125ads/Makefile
new file mode 100644
index 0000000..20fbf6e
--- /dev/null
+++ b/board/freescale/mpc5125ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc5125ads/config.mk b/board/freescale/mpc5125ads/config.mk
new file mode 100644
index 0000000..14998f4
--- /dev/null
+++ b/board/freescale/mpc5125ads/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2007 DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/board/freescale/mpc5125ads/cpld.h b/board/freescale/mpc5125ads/cpld.h
new file mode 100644
index 0000000..60578db
--- /dev/null
+++ b/board/freescale/mpc5125ads/cpld.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2009 Silicon Turnkey Express, Inc.
+ * Martha Marx Stan <mmarx at silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * MPC5125ADS CPLD Registers
+ */
+typedef struct mpc5125ads_cpld {
+	u16 board_id;
+	u8 cpld_rev[2];
+	u8 reset_cfg_word[4];
+	u8 nor_flash_ctl;
+	u8 nand_can_gpio_ctl;
+	u8 res1[3];
+	u8 int_mask;
+	u8 int_satus;
+	u8 misc_ctl;
+	u8 video_ctl;
+	u8 user_led;
+	u8 res2;
+	u8 cfg_switch;
+} mpc5125ads_cpld_t;
+
+/*
+ * MPC5125ADS CPLD Constants
+ */
+#define CPLD_CFG1		0x80
+#define CPLD_MAIN_FLASH_ACTIVE	0x04
+#define CPLD_MAIN_FLASH_WP_OFF	0xc1
+#define CPLD_BKUP_FLASH_WP_OFF	0x32
diff --git a/board/freescale/mpc5125ads/mpc5125ads.c b/board/freescale/mpc5125ads/mpc5125ads.c
new file mode 100644
index 0000000..76f419a
--- /dev/null
+++ b/board/freescale/mpc5125ads/mpc5125ads.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2009 Silicon Turnkey Express, Inc.
+ * Martha Marx Stan <mmarx at silicontkx.com>
+ *
+ * This file is based on mpc5121ads.c
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mpc512x.h>
+#include <fdt_support.h>
+#include "cpld.h"
+
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#include <flash.h>
+extern flash_info_t flash_info[];
+ulong flash_get_size(ulong addr, flash_info_t *info);
+#endif
+
+/* Clocks in use all configurations */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE2)|	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_I2C_EN |		\
+			 CLOCK_SCCR2_SDHC_EN)
+
+/* Configuration Option Set 0 Clocks */
+#define SCCR2_CFG0_CLOCKS_EN (CLOCK_SCCR2_USB1_EN |	\
+			      CLOCK_SCCR2_DIU_EN)
+
+/* Configuration Option Set 1 Clocks */
+#define SCCR1_CFG1_CLOCKS_EN (CLOCK_SCCR1_FEC2_EN)
+
+#define SCCR2_CFG1_CLOCKS_EN (CLOCK_SCCR2_USB1_EN |	\
+			      CLOCK_SCCR2_USB2_EN)
+
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+static iopin5125_t ioregs_common_init[] = {
+	/*
+	 * Note: io pin init for LPC_CS2 is done in start.S
+	 * also, DDR io pin init is done in fixed_sdram()
+	 *
+	 * FUNC1=PSC9_3 Sets Next 2 to PSC9 pads x4f & x50
+	 */
+	{
+		offsetof(struct ioctrl5125, io_control_i2c1_scl), 2, 0,
+		IO_PIN5125_FMUX(1) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO14 Sets 1 pad */
+	{
+		offsetof(struct ioctrl5125, io_control_psc_mclk_in), 1, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=IRQ0 Sets 1 pad */
+	{
+		offsetof(struct ioctrl5125, io_control_psc1_1), 1, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=CKSTP_OUT Sets 1 pad */
+	{
+		offsetof(struct ioctrl5125, io_control_psc1_4), 1, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=I2C1_SCL Sets Next 2 to I2C1 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_j1850_tx), 2, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* ORs all pads to highest slew rate*/
+	{
+		offsetof(struct ioctrl5125, io_control_lpc_clk),
+		offsetof(struct ioctrl5125, io_control_psc1_4) -
+		offsetof(struct ioctrl5125, io_control_lpc_clk) + 1, 1,
+		IO_PIN5125_FMUX(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+static  iopin5125_t ioregs_cfg0_init[] = {
+	/* FUNC2=DIU_LD00 Sets Next 2 to DIU pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld00), 2, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_LD08 Sets Next 2 to DIU pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld08), 2, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_LD16 Sets Next 2 to DIU pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld16), 2, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+static iopin5125_t ioregs_cfg1_init[] = {
+	/* FUNC2=USB1_DATA0 Sets Next 4 to USB1 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_clk), 4, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO32 Sets 1 (2 ??) pad */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld00), 2, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=USB1_DATA4 Sets Next 6 to USB1 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld02), 6, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=GPIO37 Sets 2 to GPIO pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld08), 2, 0,
+		IO_PIN5125_FMUX(3) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=USB1_NEXT Sets Next 6 to USB1 and USB2 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld10), 6, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=I2C3_SCL Sets Next 2 to I2C3 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld16), 8, 0,
+		IO_PIN5125_FMUX(1) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=USB2_DATA4 Sets Next 8 to USB2 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_diu_ld18), 8, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=FEC2_RXD_1 Sets Next 12 to FEC2 pads */
+	{
+		offsetof(struct ioctrl5125, io_control_usb1_data0), 12, 0,
+		IO_PIN5125_FMUX(2) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+int board_early_init_f (void)
+{
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	mpc5125ads_cpld_t *cpld = ( mpc5125ads_cpld_t *)CONFIG_SYS_CPLD_BASE;
+	/*
+	 * Initialize Local Window for the CPLD registers access (CS2 selects
+	 * the CPLD chip)
+	 */
+	out_be32(&im->sysconf.lpcs2aw, CSAW_START(CONFIG_SYS_CPLD_BASE) |
+		CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE));
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	sync_law(&im->sysconf.lpcs2aw);
+
+	/*
+	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+	 *
+	 * Without this the flash id routine fails, as it needs to issue
+	 * write commands in order to establish the device ID.
+	 */
+
+	if (in_8(&cpld->nor_flash_ctl) & CPLD_MAIN_FLASH_ACTIVE) {
+		out_8(&cpld->nor_flash_ctl, CPLD_MAIN_FLASH_WP_OFF);
+	} else {
+		/* running from Backup flash */
+		out_8(&cpld->nor_flash_ctl, CPLD_BKUP_FLASH_WP_OFF);
+	}
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+	out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	if (in_8(&cpld->cfg_switch) & CPLD_CFG1) {
+		out_be32(&im->clk.sccr[0],
+			SCCR1_CLOCKS_EN | SCCR1_CFG1_CLOCKS_EN);
+		out_be32(&im->clk.sccr[1],
+			SCCR2_CLOCKS_EN | SCCR2_CFG1_CLOCKS_EN);
+	} else {
+		out_be32(&im->clk.sccr[0],
+			SCCR1_CLOCKS_EN);
+		out_be32(&im->clk.sccr[1],
+			SCCR2_CLOCKS_EN | SCCR2_CFG0_CLOCKS_EN);
+	}
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	out_be32(&im->clk.sccr[1],
+		in_be32(&im->clk.sccr[1])| CLOCK_SCCR2_IIM_EN);
+#endif
+	/*
+	 * initialize function mux & slew rate for all IO pins
+	 * there are two peripheral options controlled by switch no 8
+	 */
+	if (in_8(&cpld->cfg_switch) & CPLD_CFG1) {
+		iopin5125_initialize(ioregs_cfg1_init,
+			sizeof(ioregs_cfg1_init)/sizeof(ioregs_cfg1_init[0]));
+	} else {
+		iopin5125_initialize(ioregs_cfg0_init,
+			sizeof(ioregs_cfg0_init)/sizeof(ioregs_cfg0_init[0]));
+	}
+
+	iopin5125_initialize(ioregs_common_init,
+		sizeof(ioregs_common_init)/sizeof(ioregs_common_init[0]));
+
+	/* enable default pins */
+	out_8(&im->io_ctrl.io_control_gbobe, IOCTRL_GBOBE_ON);
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	/* Elpida init sequence is an alternative to the default for Micron */
+
+	u32 elpida_init_sequence[] = {
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_EM2,
+		CONFIG_SYS_DDRCMD_EM3,
+		CONFIG_SYS_DDRCMD_EN_DLL,
+		CONFIG_SYS_ELPIDA_RES_DLL,
+		CONFIG_SYS_DDRCMD_PCHG_ALL,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_DDRCMD_RFSH,
+		CONFIG_SYS_ELPIDA_INIT_DEV_OP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_ELPIDA_OCD_DEFAULT,
+		CONFIG_SYS_ELPIDA_OCD_EXIT,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP,
+		CONFIG_SYS_DDRCMD_NOP
+	};
+
+	u32 msize;
+
+	msize = fixed_sdram(0, elpida_init_sequence,
+				sizeof(elpida_init_sequence)/sizeof(u32));
+
+	return msize;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 tmp_val;
+
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	mpc5125ads_cpld_t *cpld = (mpc5125ads_cpld_t *)CONFIG_SYS_CPLD_BASE;
+
+	u32 bkup_size = flash_info[0].size;
+	u32 bkup_start = 0xffffffff - bkup_size + 1;
+
+	if (bkup_size == CONFIG_SYS_BKUP_FLASH_SIZE) {
+
+		/*
+		 * Running from the smaller sized Backup flash
+		 * must remap flash so that the env maps same as main flash
+		 */
+		debug("Remap backup flash to start at 0x%08lx \n", bkup_start);
+		out_be32(&im->sysconf.lpcs0aw, CSAW_START(bkup_start) |
+			CSAW_STOP(bkup_start, bkup_size));
+		/*
+		 * According to MPC5121e RM, configuring local access windows
+		 * should be followed by a dummy read of the config register
+		 * that was modified last and an isync
+		 */
+		sync_law(&im->sysconf.lpcs0aw);
+		flash_get_size(bkup_start, 0);
+	}
+
+	if (in_8(&cpld->cfg_switch) & CPLD_CFG1) /* no diu in CFG1 */
+		return 0;
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+	/*
+	 * DIU init before the driver in linux takes over
+	 * Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+	i2c_set_bus_num(1);
+	tmp_val = 0xBF;
+	if (i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)) != 0)
+		goto i2c_err;
+
+	/* Verify if enabled */
+	if (i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)) != 0)
+		goto i2c_err;
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+	tmp_val = 0x10;
+	if (i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)) != 0)
+		goto i2c_err;
+
+	/* Verify if enabled */
+	if (i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)) != 0)
+		goto i2c_err;
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+#endif
+#ifdef CONFIG_FSL_DIU_FB
+#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+	mpc5121_diu_init();
+#endif
+#endif
+	return 0;
+i2c_err:
+	printf("i2c operation failed, bus 1, address 0x38\n");
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+int checkboard (void)
+{
+	mpc5125ads_cpld_t *cpld = (mpc5125ads_cpld_t *)CONFIG_SYS_CPLD_BASE;
+
+	printf ("Board: MPC5125ADS rev. 0x%04x (CPLD rev. 0x%02x",
+		in_be16(&cpld->board_id), in_8(&cpld->cpld_rev[0]));
+
+	if (in_8(&cpld->cpld_rev[1]) != 0)
+		printf (".%02x-BETA)", in_8(&cpld->cpld_rev[1]));
+
+	printf("\nPeripheral Option Set %d\n",
+		(in_8(&cpld->cfg_switch) & CPLD_CFG1));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h
index 4b14778..b79c656 100644
--- a/cpu/mpc512x/asm-offsets.h
+++ b/cpu/mpc512x/asm-offsets.h
@@ -11,5 +11,11 @@
 #define CS_CTRL			0x00020
 #define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
 
+/* needed for pin muxing in MPC5125 */
+#define IOCTRL_OFFSET	0xA000
+#define IOCTRL_LPC_AX03	0x09
+#define IOCTRL_I2C1_SCL	0x4f
+#define IOCTRL_I2C1_SDA	0x50
+
 #define EXC_OFF_SYS_RESET	0x0100
 #define	_START_OFFSET		EXC_OFF_SYS_RESET
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index 42ccd81..6d9a5ec 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -53,6 +53,9 @@ int checkcpu (void)
 	case SPR_5121E:
 		puts ("MPC5121e ");
 		break;
+	case SPR_5125:
+		puts ("MPC5125 ");
+		break;
 	default:
 		printf ("Unknown part ID %08x ", spridr & 0xffff0000);
 	}
diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c
index 673d61e..09985e7 100644
--- a/cpu/mpc512x/fixed_sdram.c
+++ b/cpu/mpc512x/fixed_sdram.c
@@ -36,6 +36,7 @@ u32 default_mddrc_config[4] = {
 };
 
 u32 default_init_seq[] = {
+#ifndef CONFIG_SYS_DDR_OVRIDE_DEF /* makes it unnecessary to declare these */
 	CONFIG_SYS_DDRCMD_NOP,
 	CONFIG_SYS_DDRCMD_NOP,
 	CONFIG_SYS_DDRCMD_NOP,
@@ -67,6 +68,7 @@ u32 default_init_seq[] = {
 	CONFIG_SYS_DDRCMD_OCD_DEFAULT,
 	CONFIG_SYS_DDRCMD_PCHG_ALL,
 	CONFIG_SYS_DDRCMD_NOP
+#endif
 };
 
 /*
@@ -90,7 +92,11 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
 	}
 
 	/* Initialize IO Control */
+#ifdef CONFIG_MPC5125
+	out_8(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+#else
 	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+#endif
 
 	/* Initialize DDR Local Window */
 	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
index be20947..d923e1d 100644
--- a/cpu/mpc512x/iopin.c
+++ b/cpu/mpc512x/iopin.c
@@ -47,3 +47,25 @@ void iopin_initialize(iopin_t *ioregs_init, int len)
 	}
 	return;
 }
+
+void iopin5125_initialize(iopin5125_t *ioregs_init, int len)
+{
+	short i, j, p;
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	u8 *reg = (u8 *)&(im->io_ctrl);
+
+	if (sizeof(ioregs_init) == 0)
+		return;
+
+	for (i = 0; i < len; i++) {
+		for (p = 0, j = ioregs_init[i].p_offset;
+			p < ioregs_init[i].nr_pins; p++, j++) {
+			if (ioregs_init[i].bit_or)
+				setbits_8(&(reg[j]), ioregs_init[i].val);
+			else
+				out_8(&reg[j], ioregs_init[i].val);
+		}
+	}
+	return;
+}
diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c
index 4fc4693..89fa139 100644
--- a/cpu/mpc512x/serial.c
+++ b/cpu/mpc512x/serial.c
@@ -80,7 +80,7 @@ int serial_init(void)
 	volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE];
 
 	fifo_init (psc);
-
+#ifndef CONFIG_MPC5125
 	/* set MR register to point to MR1 */
 	out_8(&psc->command, PSC_SEL_MODE_REG_1);
 
@@ -93,12 +93,25 @@ int serial_init(void)
 	/* switch to UART mode */
 	out_be32(&psc->sicr, 0);
 
-	/* mode register points to mr1 */
 	/* configure parity, bit length and so on in mode register 1*/
+	/* mode register points to mr1 */
 	out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
 	/* now, mode register points to mr2 */
 	out_8(&psc->mode, PSC_MODE_1_STOPBIT);
+#else
+	/* disable Tx/Rx */
+	out_8(&psc->command, PSC_TX_DISABLE | PSC_RX_DISABLE);
+
+	/* choose the prescaler	the Tx/Rx clock generation */
+	out_8(&psc->psc_clock_select, 0xdd);
+
+	/* switch to UART mode */
+	out_be32(&psc->sicr, 0);
 
+	/* configure parity, bit length and so on in mode registers */
+	out_8(&psc->mr1, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+	out_8(&psc->mr2, PSC_MODE_1_STOPBIT);
+#endif
 	/* set baudrate */
 	serial_setbrg();
 
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 2e3f645..205208f 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -243,6 +243,21 @@ boot_cold:
 	lis     r4, CONFIG_SYS_CS0_CFG at h
 	ori     r4, r4, CONFIG_SYS_CS0_CFG at l
 	stw     r4, CS0_CONFIG(r3)
+#ifdef CONFIG_MPC5125
+	/* CS2 FUNC MUX must be done before CS is enabled */
+	lis     r5, (CONFIG_SYS_IMMR + IOCTRL_OFFSET)@h
+	ori     r5, r5, (CONFIG_SYS_IMMR + IOCTRL_OFFSET)@l
+
+	li	r4, CONFIG_SYS_IOCTRL_MUX_CS2
+	stb	r4, IOCTRL_LPC_AX03(r5)
+
+	/* change the pin muxing on PSC9 if it is being used as console */
+#if (CONFIG_PSC_CONSOLE == 9)
+	li	r4, CONFIG_SYS_IOCTRL_MUX_PSC9
+	stb	r4, IOCTRL_I2C1_SCL(r5)
+	stb	r4, IOCTRL_I2C1_SDA(r5)
+#endif
+#endif
 
 	/* Master enable all CS's */
 	lis	r4, CS_CTRL_ME at h
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index fb2c19a..9f839a1 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -41,7 +41,12 @@ static int rx_buff_idx = 0;
 static void mpc512x_fec_phydump (char *devname)
 {
 	u16 phyStatus, i;
-	u8 phyAddr = CONFIG_PHY_ADDR;
+#ifdef CONFIG_MPC5125
+	uint8 phyAddr = ((devname[3] == '2') ? CONFIG_PHY2_ADDR :
+				CONFIG_PHY_ADDR);
+#else
+	uint8 phyAddr = CONFIG_PHY_ADDR;
+#endif
 	u8 reg_mask[] = {
 		/* regs to print: 0...8, 21,27,31 */
 		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
@@ -242,9 +247,17 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 	/* Set Opcode/Pause Duration Register */
 	out_be32(&fec->eth->op_pause, 0x00010020);
 
+#ifdef CONFIG_MPC5125
+	/* RMII Mode */
+	if (dev->name[3] == '2')
+		out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x124);	
+	else
+	/* Frame length=1522; MII mode */
+		out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
+#else
 	/* Frame length=1522; MII mode */
 	out_be32(&fec->eth->r_cntrl, (FEC_MAX_FRAME_LEN << 16) | 0x24);
-
+#endif
 	/* Half-duplex, heartbeat disabled */
 	out_be32(&fec->eth->x_cntrl, 0x00000000);
 
@@ -286,7 +299,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 	u16 phyStatus;
 
 #if (DEBUG & 0x1)
-	printf ("mpc512x_fec_init_phy... Begin\n");
+	printf ("mpc512x_fec_init_phy... with dev %s Begin\n", dev->name);
 #endif
 
 	/*
@@ -618,12 +631,17 @@ int mpc512x_fec_initialize (bd_t * bis)
 	int i;
 	char *tmp, *end, env_enetaddr[6];
 	void * bd;
+	volatile fec512x_t *cur_fec;
 
+	cur_fec = &(im->fec);
+#ifdef CONFIG_MPC5125
+fec_init_start:
+#endif
 	fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
 	dev = (struct eth_device *) malloc (sizeof(*dev));
 	memset (dev, 0, sizeof *dev);
 
-	fec->eth = &im->fec;
+	fec->eth = cur_fec;
 
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
@@ -637,7 +655,11 @@ int mpc512x_fec_initialize (bd_t * bis)
 	dev->send = mpc512x_fec_send;
 	dev->recv = mpc512x_fec_recv;
 
-	sprintf (dev->name, "FEC ETHERNET");
+	if (cur_fec == &(im->fec))
+		sprintf (dev->name, "FEC ETHERNET");
+	else
+		sprintf (dev->name, "FEC2 ETHERNET");
+
 	eth_register (dev);
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
@@ -646,8 +668,8 @@ int mpc512x_fec_initialize (bd_t * bis)
 #endif
 
 	/* Clean up space FEC's MIB and FIFO RAM ...*/
-	memset ((void *)&im->fec.mib,  0x00, sizeof(im->fec.mib));
-	memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
+	memset ((void *)cur_fec->mib,  0x00, sizeof(im->fec.mib));
+	memset ((void *)cur_fec->fifo, 0x00, sizeof(im->fec.fifo));
 
 	/*
 	 * Malloc space for BDs  (must be quad word-aligned)
@@ -672,7 +694,11 @@ int mpc512x_fec_initialize (bd_t * bis)
 	 * a garbage after reset. When not using fec for booting
 	 * the Linux fec driver will try to work with this garbage.
 	 */
-	tmp = getenv ("ethaddr");
+	if (cur_fec == &(im->fec))
+		tmp = getenv ("ethaddr");
+	else
+		tmp = getenv ("eth1addr");
+
 	if (tmp) {
 		for (i=0; i<6; i++) {
 			env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
@@ -685,7 +711,14 @@ int mpc512x_fec_initialize (bd_t * bis)
 	}
 
 	mpc512x_fec_init_phy (dev, bis);
-
+#ifdef CONFIG_MPC5125
+	/* 2nd fec may not be in use */
+	if (cur_fec == &(im->fec) &&
+		(in_be32(&im->clk.sccr[0]) & CLOCK_SCCR1_FEC2_EN)) {
+		cur_fec = &(im->fec2);
+		goto fec_init_start;
+	}
+#endif
 	return 1;
 }
 
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 79cdd80..1c1d235 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -36,6 +36,7 @@
 #define	_START_OFFSET		EXC_OFF_SYS_RESET
 
 #define SPR_5121E		0x80180000
+#define SPR_5125		0x80190000
 
 /*
  * IMMRBAR - Internal Memory Register Base Address
@@ -210,21 +211,24 @@ typedef struct clk512x {
 #define CLOCK_SCCR1_TPR_EN		0x00001000
 #define CLOCK_SCCR1_PCI_EN		0x00000800
 #define CLOCK_SCCR1_DDR_EN		0x00000400
+#define CLOCK_SCCR1_FEC2_EN		0x00000200
 
 /* System Clock Control Register 2 commands */
 #define CLOCK_SCCR2_DIU_EN		0x80000000
 #define CLOCK_SCCR2_AXE_EN		0x40000000
 #define CLOCK_SCCR2_MEM_EN		0x20000000
-#define CLOCK_SCCR2_USB2_EN		0x10000000
-#define CLOCK_SCCR2_USB1_EN		0x08000000
+#define CLOCK_SCCR2_USB1_EN		0x10000000
+#define CLOCK_SCCR2_USB2_EN		0x08000000
 #define CLOCK_SCCR2_I2C_EN		0x04000000
 #define CLOCK_SCCR2_BDLC_EN		0x02000000
+#define CLOCK_SCCR2_AUTO_EN		0x02000000
 #define CLOCK_SCCR2_SDHC_EN		0x01000000
 #define CLOCK_SCCR2_SPDIF_EN		0x00800000
 #define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
 #define CLOCK_SCCR2_MBX_EN		0x00200000
 #define CLOCK_SCCR2_MBX_3D_EN		0x00100000
 #define CLOCK_SCCR2_IIM_EN		0x00080000
+#define CLOCK_SCCR2_SDHC2_EN		0x00020000
 
 /* SCFR1 System Clock Frequency Register 1 */
 #define SCFR1_IPS_DIV		0x3
@@ -838,11 +842,150 @@ typedef struct ioctrl512x {
 	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
 } ioctrl512x_t;
 
+/*
+ * MPC5125 IO Control
+ */
+typedef struct ioctrl5125 {
+	u8 	io_control_mem;		/* offset 0x00 mem io pad ctl	    */
+	u8 	io_control_gbobe;	/* offset 0x01 gbobe io pad ctl     */
+	u8	res1[2];
+	u8 	io_control_lpc_clk;	/* offset 0x04 lpc_clk io pad ctl    */
+	u8 	io_control_lpc_oe_b;	/* offset 0x05 lpc_oe_b io pad ctl   */
+	u8 	io_control_lpc_rwb;	/* offset 0x06 lpc_rwb io pad ctl    */
+	u8 	io_control_lpc_cs0_b;	/* offset 0x07 lpc_cs0_io pad ctrl   */
+	u8 	io_control_lpc_ack_b;	/* offset 0x08 lpc_ack_b io pad ctl  */
+	u8 	io_control_lpc_ax03;	/* offset 0x09 lpc_ax03 io pad ctl   */
+	u8 	io_control_emb_ax02;	/* offset 0x0a emb_ax02 io pad ctl   */
+	u8 	io_control_emb_ax01;	/* offset 0x0b emb_ax01 io pad ctl   */
+	u8 	io_control_emb_ax00;	/* offset 0x0c emb_ax00 io pad ctl   */
+	u8 	io_control_emb_ad31;	/* offset 0x0d emb_ad31 io pad ctl   */
+	u8 	io_control_emb_ad30;	/* offset 0x0e emb_ad30 io pad ctl   */
+	u8 	io_control_emb_ad29;	/* offset 0x0f emb_ad29 io pad ctl   */
+	u8 	io_control_emb_ad28;	/* offset 0x10 emb_ad28 io pad ctl   */
+	u8 	io_control_emb_ad27;	/* offset 0x11 emb_ad27 io pad ctl   */
+	u8 	io_control_emb_ad26;	/* offset 0x12 emb_ad26 io pad ctl   */
+	u8 	io_control_emb_ad25;	/* offset 0x13 emb_ad25 io pad ctl   */
+	u8 	io_control_emb_ad24;	/* offset 0x14 emb_ad24 io pad ctl   */
+	u8 	io_control_emb_ad23;	/* offset 0x15 emb_ad23 io pad ctl   */
+	u8 	io_control_emb_ad22;	/* offset 0x16 emb_ad22 io pad ctl   */
+	u8 	io_control_emb_ad21;	/* offset 0x17 emb_ad21 io pad ctl   */
+	u8 	io_control_emb_ad20;	/* offset 0x18 emb_ad20 io pad ctl   */
+	u8 	io_control_emb_ad19;	/* offset 0x19 emb_ad19 io pad ctl   */
+	u8 	io_control_emb_ad18;	/* offset 0x1a emb_ad18 io pad ctl   */
+	u8 	io_control_emb_ad17;	/* offset 0x1b emb_ad17 io pad ctl   */
+	u8 	io_control_emb_ad16;	/* offset 0x1c emb_ad16 io pad ctl   */
+	u8 	io_control_emb_ad15;	/* offset 0x1d emb_ad15 io pad ctl   */
+	u8 	io_control_emb_ad14;	/* offset 0x1e emb_ad14 io pad ctl   */
+	u8 	io_control_emb_ad13;	/* offset 0x1f emb_ad13 io pad ctl   */
+	u8 	io_control_emb_ad12;	/* offset 0x20 emb_ad12 io pad ctl   */
+	u8 	io_control_emb_ad11;	/* offset 0x21 emb_ad11 io pad ctl   */
+	u8 	io_control_emb_ad10;	/* offset 0x22 emb_ad10 io pad ctl   */
+	u8 	io_control_emb_ad09;	/* offset 0x23 emb_ad09 io pad ctl   */
+	u8 	io_control_emb_ad08;	/* offset 0x24 emb_ad08 io pad ctl   */
+	u8 	io_control_emb_ad07;	/* offset 0x25 emb_ad07 io pad ctl   */
+	u8 	io_control_emb_ad06;	/* offset 0x26 emb_ad06 io pad ctl   */
+	u8 	io_control_emb_ad05;	/* offset 0x27 emb_ad05 io pad ctl   */
+	u8 	io_control_emb_ad04;	/* offset 0x28 emb_ad04 io pad ctl   */
+	u8 	io_control_emb_ad03;	/* offset 0x29 emb_ad03 io pad ctl   */
+	u8 	io_control_emb_ad02;	/* offset 0x2a emb_ad02 io pad ctl   */
+	u8 	io_control_emb_ad01;	/* offset 0x2b emb_ad01 io pad ctl   */
+	u8 	io_control_emb_ad00;	/* offset 0x2c emb_ad00 io pad ctl   */
+	u8 	io_control_nfc_ce0_b;	/* offset 0x2d nfc_ce0_b io pad	ctrl */
+	u8 	io_control_nfc_rb;	/* offset 0x2e nfc_rb io pad ctl     */
+	u8 	io_control_diu_clk;	/* offset 0x2f diu_clk io pad ctl    */
+	u8 	io_control_diu_de;	/* offset 0x30 diu_de io pad ctl     */
+	u8 	io_control_diu_hsync;	/* offset 0x31 diu_hsync io pad ctl  */
+	u8 	io_control_diu_vsync;	/* offset 0x32 diu_vsync io pad ctl  */
+	u8 	io_control_diu_ld00;	/* offset 0x33 diu_ld00 io pad ctl   */
+	u8 	io_control_diu_ld01;	/* offset 0x34 diu_ld01 io pad ctl   */
+	u8 	io_control_diu_ld02;	/* offset 0x35 diu_ld02 io pad ctl   */
+	u8 	io_control_diu_ld03;	/* offset 0x36 diu_ld03 io pad ctl   */
+	u8 	io_control_diu_ld04;	/* offset 0x37 diu_ld04 io pad ctl   */
+	u8 	io_control_diu_ld05;	/* offset 0x38 diu_ld05 io pad ctl   */
+	u8 	io_control_diu_ld06;	/* offset 0x39 diu_ld06 io pad ctl   */
+	u8 	io_control_diu_ld07;	/* offset 0x3a diu_ld07 io pad ctl   */
+	u8 	io_control_diu_ld08;	/* offset 0x3b diu_ld08 io pad ctl   */
+	u8 	io_control_diu_ld09;	/* offset 0x3c diu_ld09 io pad ctl   */
+	u8 	io_control_diu_ld10;	/* offset 0x3d diu_ld10 io pad ctl   */
+	u8 	io_control_diu_ld11;	/* offset 0x3e diu_ld11 io pad ctl   */
+	u8 	io_control_diu_ld12;	/* offset 0x3f diu_ld12 io pad ctl   */
+	u8 	io_control_diu_ld13;	/* offset 0x40 diu_ld13 io pad ctl   */
+	u8 	io_control_diu_ld14;	/* offset 0x41 diu_ld14 io pad ctl   */
+	u8 	io_control_diu_ld15;	/* offset 0x42 diu_ld15 io pad ctl   */
+	u8 	io_control_diu_ld16;	/* offset 0x43 diu_ld16 io pad ctl   */
+	u8 	io_control_diu_ld17;	/* offset 0x44 diu_ld17 io pad ctl   */
+	u8 	io_control_diu_ld18;	/* offset 0x45 diu_ld18 io pad ctl   */
+	u8 	io_control_diu_ld19;	/* offset 0x46 diu_ld19 io pad ctl   */
+	u8 	io_control_diu_ld20;	/* offset 0x47 diu_ld20 io pad ctl   */
+	u8 	io_control_diu_ld21;	/* offset 0x48 diu_ld21 io pad ctl   */
+	u8 	io_control_diu_ld22;	/* offset 0x49 diu_ld22 io pad ctl   */
+	u8 	io_control_diu_ld23;	/* offset 0x4a diu_ld23 io pad ctl   */
+	u8 	io_control_can4_rx;	/* offset 0x4b can4_rx io pad ctl    */
+	u8 	io_control_can4_tx;	/* offset 0x4c can4_tx io pad ctl    */
+	u8 	io_control_can1_tx;	/* offset 0x4d can1_tx io pad ctl    */
+	u8 	io_control_can2_tx;	/* offset 0x4e can2_tx io pad ctl    */
+	u8 	io_control_i2c1_scl;	/* offset 0x4f i2c1_scl io pad ctl   */
+	u8 	io_control_i2c1_sda;	/* offset 0x50 i2c1_sda io pad ctl   */
+	u8 	io_control_fec1_txd_2;	/* offset 0x51 fec1_txd_2 io pad ctl */
+	u8 	io_control_fec1_txd_3;	/* offset 0x52 fec1_txd_3 io pad ctl */
+	u8 	io_control_fec1_rxd_2;	/* offset 0x53 fec1_rxd_2 io pad ctl */
+	u8 	io_control_fec1_rxd_3;	/* offset 0x54 fec1_rxd_3 io pad ctl */
+	u8 	io_control_fec1_crs;	/* offset 0x55 fec1_crs io pad ctl   */
+	u8 	io_control_fec1_tx_er;	/* offset 0x56 fec1_tx_er io pad ctl */
+	u8 	io_control_fec1_rxd_1;	/* offset 0x57 fec1_rxd_1 io pad ctl */
+	u8 	io_control_fec1_txd_1;	/* offset 0x58 fec1_txd_1 io pad ctl */
+	u8 	io_control_fec1_mdc;	/* offset 0x59 fec1_mdc io pad ctl   */
+	u8 	io_control_fec1_rx_er;	/* offset 0x5a fec1_rx_er io pad ctl */
+	u8 	io_control_fec1_mdio;	/* offset 0x5b fec1_mdio io pad ctl  */
+	u8 	io_control_fec1_rxd_0;	/* offset 0x5c fec1_rxd_0 io pad ctl */
+	u8 	io_control_fec1_txd_0;	/* offset 0x5d fec1_txd_0 io pad ctl */
+	u8 	io_control_fec1_tx_clk;	/* offset 0x5e fec1_tx_clk iopad ctl */
+	u8 	io_control_fec1_rx_clk;	/* offset 0x5f fec1_rx_clk iopad ctl */
+	u8 	io_control_fec1_rx_dv;	/* offset 0x60 fec1_rx_dv io pad ctl */
+	u8 	io_control_fec1_tx_en;	/* offset 0x61 fec1_tx_en io pad ctl */
+	u8 	io_control_fec1_col;	/* offset 0x62 fec1_col io pad ctl   */
+	u8 	io_control_usb1_data0;	/* offset 0x63 usb1_data0 io pad ctl */
+	u8 	io_control_usb1_data1;	/* offset 0x64 usb1_data1 io pad ctl */
+	u8 	io_control_usb1_data2;	/* offset 0x65 usb1_data2 io pad ctl */
+	u8 	io_control_usb1_data3;	/* offset 0x66 usb1_data3 io pad ctl */
+	u8 	io_control_usb1_data4;	/* offset 0x67 usb1_data4 io pad ctl */
+	u8 	io_control_usb1_data5;	/* offset 0x68 usb1_data5 io pad ctl */
+	u8 	io_control_usb1_data6;	/* offset 0x69 usb1_data6 io pad ctl */
+	u8 	io_control_usb1_data7;	/* offset 0x6a usb1_data7 io pad ctl */
+	u8 	io_control_usb1_stop;	/* offset 0x6b usb1_stop io pad ctl  */
+	u8 	io_control_usb1_clk;	/* offset 0x6c usb1_clk io pad ctl   */
+	u8 	io_control_usb1_next;	/* offset 0x6d usb1_next io pad ctl  */
+	u8 	io_control_usb1_dir;	/* offset 0x6e usb1_dir io pad ctl   */
+	u8 	io_control_sdhc1_clk;	/* offset 0x6f sdhc1_clk io pad ctl  */
+	u8 	io_control_sdhc1_cmd;	/* offset 0x70 sdhc1_cmd io pad ctl  */
+	u8 	io_control_sdhc1_d0;	/* offset 0x71 sdhc1_d0 io pad ctl   */
+	u8 	io_control_sdhc1_d1;	/* offset 0x72 sdhc1_d1 io pad ctl   */
+	u8 	io_control_sdhc1_d2;	/* offset 0x73 sdhc1_d2 io pad ctl   */
+	u8 	io_control_sdhc1_d3;	/* offset 0x74 sdhc1_d3 io pad ctl   */
+	u8 	io_control_psc_mclk_in;	/* offset 0x75 psc_mclk_in io pad    */
+	u8 	io_control_psc0_0;	/* offset 0x76 psc0_0 io pad ctl     */
+	u8 	io_control_psc0_1;	/* offset 0x77 psc0_1 io pad ctl     */
+	u8 	io_control_psc0_2;	/* offset 0x78 psc0_2 io pad ctl     */
+	u8 	io_control_psc0_3;	/* offset 0x79 psc0_3 io pad ctl     */
+	u8 	io_control_psc0_4;	/* offset 0x7a psc0_4 io pad ctl     */
+	u8 	io_control_psc1_0;	/* offset 0x7b psc1_0 io pad ctl     */
+	u8 	io_control_psc1_1;	/* offset 0x7c psc1_1 io pad ctl     */
+	u8 	io_control_psc1_2;	/* offset 0x7d psc1_2 io pad ctl     */
+	u8 	io_control_psc1_3;	/* offset 0x7e psc1_3 io pad ctl     */
+	u8 	io_control_psc1_4;	/* offset 0x7f psc1_4 io pad ctl     */
+	u8 	io_control_j1850_tx;	/* offset 0x80 j1850_tx io pad ctl   */
+	u8 	io_control_j1850_rx;	/* offset 0x81 j1850_rx io pad ctl   */
+	u8	reserved[0x1000 - 0x82];/* fill to 4096 bytes size 	  */
+} ioctrl5125_t;
+
 /* Indexes in regs array */
 /* Set for DDR */
 #define IOCTRL_MUX_DDR		0x00000036
+#define IOCTRL_GBOBE_ON		0x01
 
 /* IO pin fields */
+
+#define IO_PIN5125_FMUX(v) ((v) << 5)	/* pin function */
 #define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
 #define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
 #define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
@@ -857,7 +1000,15 @@ typedef struct iopin_t {
 	u_long val;		/* value to write or or */
 }iopin_t;
 
+typedef struct iopin5125_t {
+	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
+	int nr_pins;		/* number of pins to set this way */
+	int bit_or;		/* or in the value instead of overwrite */
+	u8  val;
+} iopin5125_t;
+
 void iopin_initialize(iopin_t *,int);
+void iopin5125_initialize(iopin5125_t *, int);
 
 /*
  * IIM
@@ -948,8 +1099,16 @@ typedef struct pata512x {
 	u32 res3[0x09];
 } pata512x_t;
 
+#ifndef CONFIG_MPC5125
 /*
- * PSC
+ * MPC5121 PSC
+ * note: MPC5121e register overloading is handled by unions with #defines to
+ * reference the reg seemlessly these #defines must not exist for MPC5125 code
+ * since it does not have this overloading. Since the register naming is the
+ * same as the MPC5125 Reference Manual and this naming is exactly the reg names
+ * used in the init code (which is nearly identical) it causes compile errors to
+ * leave in and must be #ifdef'ed out.  It also helps to share code to have the
+ * same structure for both MPC5121 and MPC5125
  */
 typedef struct psc512x {
 	volatile u8	mode;		/* PSC + 0x00 */
@@ -1039,6 +1198,92 @@ typedef struct psc512x {
 #define rfdata_16	rfdata_buffer.buffer_16
 #define rfdata_32	rfdata_buffer.buffer_32
 } psc512x_t;
+#else
+/*
+ * PSC for the mpc5125
+ */
+typedef struct psc512x {
+	volatile u8	mr1;		/* PSC + 0x00 */
+	volatile u8	res1[3];
+	volatile u8	mr2;		/* PSC + 0x04 */
+	volatile u8	res2[3];
+	volatile u16	psc_status;	/* PSC + 0x08 */
+	volatile u16	res3;
+	volatile u8	psc_clock_select;/* PSC + 0x0C */
+	volatile u8	res4[3];
+	volatile u8	command;	/* PSC + 0x10 */
+	volatile u8	res5[3];
+	union {			/* PSC + 0x14 */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} buffer;
+#define psc_buffer_8	buffer.buffer_8
+#define psc_buffer_16	buffer.buffer_16
+#define psc_buffer_32	buffer.buffer_32
+	volatile u8	psc_ipcr;	/* PSC + 0x18 */
+	volatile u8	res6[3];
+	volatile u8	psc_acr;	/* PSC + 0x1C */
+	volatile u8	res7[3];
+	volatile u16	psc_isr;	/* PSC + 0x20 */
+	volatile u16	res8;
+	volatile u16	psc_imr;	/* PSC + 0x24 */
+	volatile u16	res9;
+	volatile u8	ctur;		/* PSC + 0x28 */
+	volatile u8	res10[3];
+	volatile u8	ctlr;		/* PSC + 0x2c */
+	volatile u8	res11[3];
+	volatile u32	ccr;		/* PSC + 0x30 */
+	volatile u8	res12[12];
+	volatile u8	ivr;		/* PSC + 0x40 */
+	volatile u8	res13[3];
+	volatile u8	ip;		/* PSC + 0x44 */
+	volatile u8	res14[3];
+	volatile u8	op1;		/* PSC + 0x48 */
+	volatile u8	res15[3];
+	volatile u8	op0;		/* PSC + 0x4c */
+	volatile u8	res16[3];
+	volatile u32	sicr;		/* PSC + 0x50 */
+	volatile u8	res17[44];
+	volatile u32	tfcmd;		/* PSC + 0x80 */
+	volatile u32	tfalarm;	/* PSC + 0x84 */
+	volatile u32	tfstat;		/* PSC + 0x88 */
+	volatile u32	tfintstat;	/* PSC + 0x8C */
+	volatile u32	tfintmask;	/* PSC + 0x90 */
+	volatile u32	tfcount;	/* PSC + 0x94 */
+	volatile u16	tfwptr;		/* PSC + 0x98 */
+	volatile u16	tfrptr;		/* PSC + 0x9A */
+	volatile u32	tfsize;		/* PSC + 0x9C */
+	volatile u8	res18[28];
+	union {			/* PSC + 0xBC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} tfdata_buffer;
+#define tfdata_8	tfdata_buffer.buffer_8
+#define tfdata_16	tfdata_buffer.buffer_16
+#define tfdata_32	tfdata_buffer.buffer_32
+
+	volatile u32	rfcmd;		/* PSC + 0xC0 */
+	volatile u32	rfalarm;	/* PSC + 0xC4 */
+	volatile u32	rfstat;		/* PSC + 0xC8 */
+	volatile u32	rfintstat;	/* PSC + 0xCC */
+	volatile u32	rfintmask;	/* PSC + 0xD0 */
+	volatile u32	rfcount;	/* PSC + 0xD4 */
+	volatile u16	rfwptr;		/* PSC + 0xD8 */
+	volatile u16	rfrptr;		/* PSC + 0xDA */
+	volatile u32	rfsize;		/* PSC + 0xDC */
+	volatile u8	res19[28];
+	union {			/* PSC + 0xFC */
+		volatile u8	buffer_8;
+		volatile u16	buffer_16;
+		volatile u32	buffer_32;
+	} rfdata_buffer;
+#define rfdata_8	rfdata_buffer.buffer_8
+#define rfdata_16	rfdata_buffer.buffer_16
+#define rfdata_32	rfdata_buffer.buffer_32
+} psc512x_t;
+#endif
 
 /* PSC FIFO Command values */
 #define PSC_FIFO_RESET_SLICE		0x80
@@ -1112,10 +1357,10 @@ typedef struct fifoc512x {
 #define FIFOC_PSC0_RX_SIZE	0x0
 #define FIFOC_PSC0_RX_ADDR	0x0
 
-#define FIFOC_PSC1_TX_SIZE	0x0
-#define FIFOC_PSC1_TX_ADDR	0x0
-#define FIFOC_PSC1_RX_SIZE	0x0
-#define FIFOC_PSC1_RX_ADDR	0x0
+#define FIFOC_PSC1_TX_SIZE	0x4
+#define FIFOC_PSC1_TX_ADDR	0x20
+#define FIFOC_PSC1_RX_SIZE	0x4
+#define FIFOC_PSC1_RX_ADDR	0x30
 
 #define FIFOC_PSC2_TX_SIZE	0x0
 #define FIFOC_PSC2_TX_ADDR	0x0
@@ -1152,10 +1397,10 @@ typedef struct fifoc512x {
 #define FIFOC_PSC8_RX_SIZE	0x0
 #define FIFOC_PSC8_RX_ADDR	0x0
 
-#define FIFOC_PSC9_TX_SIZE	0x0
-#define FIFOC_PSC9_TX_ADDR	0x0
-#define FIFOC_PSC9_RX_SIZE	0x0
-#define FIFOC_PSC9_RX_ADDR	0x0
+#define FIFOC_PSC9_TX_SIZE	0x4
+#define FIFOC_PSC9_TX_ADDR	0x40
+#define FIFOC_PSC9_RX_SIZE	0x4
+#define FIFOC_PSC9_RX_ADDR	0x50
 
 #define FIFOC_PSC10_TX_SIZE	0x0
 #define FIFOC_PSC10_TX_ADDR	0x0
@@ -1200,23 +1445,39 @@ typedef struct immap {
 	fec512x_t		fec;		/* Fast Ethernet Controller */
 	ulpi512x_t		ulpi;		/* USB ULPI */
 	u8			res4[0xa00];
+#ifdef CONFIG_MPC5125
+	ulpi512x_t		ulpi2;		/* USB ULPI */
+	u8			res5[0x200];
+	fec512x_t		fec2;		/* 2nd Fast Eth Controller */
+	gpt512x_t		gpt2;		/* 2nd General Purpose Timer */
+	sdhc512x_t		sdhc2;		/* 2nd SDHC */
+	u8			res6[0x3e00];
+	ddr512x_t		mddrc;		/* DDR Memory Controller */
+	ioctrl5125_t		io_ctrl;	/* IO Control */
+#else
 	utmi512x_t		utmi;		/* USB UTMI */
 	u8			res5[0x1000];
 	pcidma512x_t		pci_dma;	/* PCI DMA */
 	pciconf512x_t		pci_conf;	/* PCI Configuration */
 	u8			res6[0x80];
 	ios512x_t		ios;		/* PCI Sequencer */
-	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control and Status */
+	pcictrl512x_t		pci_ctrl;	/* PCI Controller Control */
 	u8			res7[0xa00];
 	ddr512x_t		mddrc;		/* Multi-port DDR Memory Controller */
 	ioctrl512x_t		io_ctrl;	/* IO Control */
+#endif
 	iim512x_t		iim;		/* IC Identification module */
 	u8			res8[0x4000];
 	lpc512x_t		lpc;		/* LocalPlus Controller */
 	pata512x_t		pata;		/* Parallel ATA */
 	u8			res9[0xd00];
+#ifdef CONFIG_MPC5125
+	psc512x_t		psc[10];	/* PSCs */
+	u8			res10[0x500];
+#else
 	psc512x_t		psc[12];	/* PSCs */
 	u8			res10[0x300];
+#endif
 	fifoc512x_t		fifoc;		/* FIFO Controller */
 	u8			res11[0x2000];
 	dma512x_t		dma;		/* DMA */
diff --git a/include/configs/mpc5125ads.h b/include/configs/mpc5125ads.h
new file mode 100644
index 0000000..6126b7a
--- /dev/null
+++ b/include/configs/mpc5125ads.h
@@ -0,0 +1,486 @@
+/*
+ * Copyright 2009 Silicon Turnkey Express, Inc.
+ * Martha Marx Stan <mmarx at silicontkx.com>
+ *
+ * This file is based on mpc5121ads.h
+ * (C) Copyright 2007-2009 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * MPC5125ADS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC5125ADS 	/* MPC5125 Reference Board 		*/
+#define CONFIG_MPC5125		/* MPC5125 processor 			*/
+
+/*
+ * Memory map for the MPC5125ADS board:
+ *
+ * 0x0000_0000 - 0x00FF_FFFF	DDR RAM (16 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x4000_0000 - 0x400F_FFFF	NAND FLASH CONTROLLER
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR			0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+
+/* Runtime MDDRC Commands */
+#define CONFIG_SYS_MDDRC_SYS_CFG		0xea802bc0
+#define CONFIG_SYS_MDDRC_TIME_CFG0		0x06183D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG1		0x690e1189
+#define CONFIG_SYS_MDDRC_TIME_CFG2		0x34a90864
+
+/* Not using the mpc512x Default DDR init sequence */
+#define CONFIG_SYS_DDR_OVRIDE_DEF
+
+/* DRAM Commands */
+#define CONFIG_SYS_DDRCMD_NOP		0x01380000
+#define CONFIG_SYS_DDRCMD_PCHG_ALL	0x01100400
+#define CONFIG_SYS_DDRCMD_EM2		0x01020000
+#define CONFIG_SYS_DDRCMD_EM3		0x01030000
+#define CONFIG_SYS_DDRCMD_EN_DLL	0x01010000
+#define CONFIG_SYS_DDRCMD_RFSH		0x01080000
+
+#define DDRCMD_EMR_OCD(pr, ohm) ( \
+	(1 << 24)	   | /* MDDRC Command Request	*/ \
+	(1 << 16)	   | /* MODE Reg BA[2:0] 	*/ \
+	(0 << 12)	   | /* Outputs 0=Enabled	*/ \
+	(0 << 11)	   | /* RDQS 			*/ \
+	(1 << 10)	   | /* DQS# 			*/ \
+	(pr <<  7)	   | /* OCD prog 7=deflt,0=exit	*/ \
+		    /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
+	((ohm & 0x2) <<  5)| /* Rtt1			*/ \
+	(0 <<  3)	   | /* additive posted CAS#	*/ \
+	((ohm & 0x1) <<  2)| /* Rtt0			*/ \
+	(0 <<  0)	   | /* Output Drive Strength	*/ \
+	(0 <<  0))	     /* DLL Enable 0=Normal	*/
+
+/* ODT must be set to 50 Ohm */
+#define CONFIG_SYS_ELPIDA_OCD_DEFAULT	DDRCMD_EMR_OCD(7, 2)
+#define CONFIG_SYS_ELPIDA_OCD_EXIT	DDRCMD_EMR_OCD(0, 2)
+
+#define DDR_CMD_MODE_REG(cas, wr) ( \
+	(1 << 24)    | /* MDDRC Command Request			*/ \
+	(0 << 16)    | /* MODE Reg BA[2:0] 			*/ \
+	((wr-1) << 9)| /* Write Recovery 			*/ \
+	(cas << 4)   | /* CAS 					*/ \
+	(0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved	*/ \
+	(2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8	*/
+
+#define CONFIG_SYS_ELPIDA_INIT_DEV_OP	DDR_CMD_MODE_REG(4, 4)
+#define CONFIG_SYS_ELPIDA_RES_DLL	(DDR_CMD_MODE_REG(4, 4) | (1 << 8))
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x2000000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * CPLD registers area is really only 32 bytes in size,
+ * but the smallest possible LP window is 64KB
+ */
+#define CONFIG_SYS_CPLD_BASE		0x82000000
+#define CONFIG_SYS_CPLD_SIZE		0x00010000 /* 64 KB */
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00008000 /* 32 KB */
+
+#define CONFIG_SYS_CS0_CFG		0x05059110 /* ALE low, 16-bit data */
+#define CONFIG_SYS_CS2_CFG		0x05059010 /* ALE low, 8-bit data  */
+#define CONFIG_SYS_CS_ALETIMING		0x00000005 /* Use alt CS timing    */
+
+/* Special IO Pin Muxing done in Start.S */
+#define CONFIG_SYS_IOCTRL_MUX_CS2	0x43	/* pin mux for CS2 */
+#define CONFIG_IOCTRL_MUX_PSC9		0x23	/* pin mux for PSC9 console */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* RAM start  */
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE /* RAM size   */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END -\
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE    /* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024) /* 512 kB for Mon	 */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* 6M malloc   */
+#define CONFIG_SYS_SPLASH_SIZE		(2 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
+#define CONFIG_PSC_CONSOLE2	9	/* other console is on PSC9 */
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#if (CONFIG_PSC_CONSOLE == 1)
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC1_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC1_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC1_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC1_RX_ADDR
+#elif (CONFIG_PSC_CONSOLE2 == 9)
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC9_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC9_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC9_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC9_RX_ADDR
+#else
+#error CONFIG_PSC_CONSOLE must be 1 or 9
+#endif
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C				/* I2C with hardware support */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed & slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2    /* 16-bit EEPROM addr   */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50 /* Atmel AT24C32A-10TQ  */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5    /* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5    /* 32byte Pg Write Mode */
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68	 */
+
+#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_PHY2_ADDR	0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+
+
+/*
+ * Environment
+ */
+#define CONFIG_SYS_BKUP_FLASH_SIZE 0x400000 /* bkup flash is 4M */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		 0x20000
+#define CONFIG_ENV_SECT_SIZE	 0x20000	/* one sector (128K) for env */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_FUSE
+
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#endif
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5125e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x4000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+			sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max no. of command args   */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size    */
+#define CONFIG_SYS_HZ		1000		  /* decr freq: 1ms ticks    */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Mem map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5 /*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		mpc5125ads
+#define CONFIG_BOOTFILE		mpc5125ads/uImage
+#define CONFIG_ROOTPATH		/opt/eldk/pcc_6xx
+
+#define CONFIG_LOADADDR		400000	/* deflt location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=300000\0"					\
+	"fdt_addr_r=400000\0"						\
+	"ramdisk_addr_r=500000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FC040000\0"					\
+	"fdt_addr=FC2C0000\0"						\
+	"ramdisk_addr=FC300000\0"					\
+	"ramdiskfile=mpc5125ads/uRamdisk\0"				\
+	"fdtfile=mpc5125ads/mpc5125ads.dtb\0"				\
+	"u-boot=mpc5125ads/u-boot.bin\0"				\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	""
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5125 at 0"
+#define OF_SOC_COMPAT		"fsl,mpc5125-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc at 80000000/serial at 11300"
+
+#endif	/* __CONFIG_H */
-- 
1.6.0.2



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