[U-Boot] [PATCH 1/1] ppc/85xx/pci: fsl_pci_init: pcie agent mode support

[Mahajan Vivek-B08308]

> [mailto:u-boot-bounces at lists.denx.de] On Behalf Of Ed Swarthout
> Sent: Thursday, October 29, 2009 12:59 PM
> > +++ b/board/freescale/mpc8572ds/mpc8572ds.c
> > @@ -199,7 +199,7 @@ void pci_init_board(void)
> >  		first_free_busno = fsl_pci_init_port(&pci_info[num++],
> > -					&pcie3_hose, first_free_busno);
> > +				&pcie3_hose, first_free_busno, pcie_ep);
> 
> Why pass this new parameter when the common code already 
> determines it from the PI field?

pcie_ep does not represent the regular PCIe EP; rather this is a
special case when the PCIe controller on the 85xx based board is 
configured as a PCIe EP.

> 
> ...
> 
> > +++ b/drivers/pci/fsl_pci_init.c
> > 
> >  int fsl_pci_init_port(struct fsl_pci_info *pci_info,
> > -			struct pci_controller *hose, int busno)
> > +			struct pci_controller *hose, int busno, 
> int pcie_ep)
>  
> > +	if (pcie_ep) {
> > +		pit_t *pi = &pci->pit[2];
> > +
> > +		pci_setup_indirect(hose, (u32) &pci->cfg_addr,
> > +		out_be32(&pi->pitar, 0);
> > +		out_be32(&pi->piwbar, 0);
> > +		out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
> > +			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | 
> PIWAR_IWS_4K);
> 
> Why is this the right size for every board that calls this function?

Inbound memory window does support multiple sizes and we have to 
feed some size in it. May be we can have a board specifc config to 
drive this window size.

> 
> > +
> > +		fsl_pci_config_unlock(hose);
> > +		return 0;
> 
> This is wrong.  It must return the first free busno.

Correct.

> 
> But it shouldn't return here, because some of the initialization in
> fsl_pci_init() is still needed for an end-point.
> 
> And a busno needs to be allocated to an end-point for config 
> transactions.

Isn't PCIe host bridge init will take care of allocation of bus nos for
the 
config transaction to succceed. 

> 
> -EdS
> 
> 

Thanks,
Vivek

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