[U-Boot] [PATCH 3/5 v3] nios2: add Altera EP3C120 board

[Michal Simek]

Thomas Chou wrote:
> This patch supports the Altera CycloneIII Nios dev board using
> the example FPGA design at http://nioswiki.com/Linux.
> 
> This board servers as a configuration template for nios2-generic
> approach. Since each fpga board can have different designs, we
> will refer them as designs rather than boards. All designs can
> share the same nios2-generic board directory.

First of all. This patch is nicer than previous one.

Some my other comments below.

> 
> To support a new design,
> 1. add a configuration file based on EP3C120.h.
> 2. include the fpga header file
> 3. add an entry to the NIOS2_GENERIC list in the top Makefile
> 
> Signed-off-by: Thomas Chou <thomas at wytron.com.tw>
> ---
> trim down fpga header.
> merge timer patch from Scott.
> disable altera_tse to cut the dependency.
> change mtdparts device name.
> 
> After nios2 next merged, this patch is only depended on
> 1. nios2: Fix outx/writex parameter order in io.h (from Scott)
> 2. nios2: add nios2-generic board (patch 1/5 in this series)
> 
>  MAINTAINERS                              |    1 +
>  MAKEALL                                  |    1 +
>  Makefile                                 |    6 +
>  board/altera/nios2-generic/default_mmu.h |  131 +++++++++++
>  include/configs/EP3C120.h                |  376 ++++++++++++++++++++++++++++++
>  5 files changed, 515 insertions(+), 0 deletions(-)
>  create mode 100644 board/altera/nios2-generic/default_mmu.h
>  create mode 100644 include/configs/EP3C120.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bb03f17..b26aa22 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -850,6 +850,7 @@ Scott McNutt <smcnutt at psyent.com>
>  	EP1C20		Nios-II
>  	EP1S10		Nios-II
>  	EP1S40		Nios-II
> +	EP3C120	Nios-II
>  
>  #########################################################################
>  # MicroBlaze Systems:							#
> diff --git a/MAKEALL b/MAKEALL
> index a88c31e..01a4d2f 100755
> --- a/MAKEALL
> +++ b/MAKEALL
> @@ -823,6 +823,7 @@ LIST_nios2="		\
>  	EP1S40		\
>  	PCI5441		\
>  	PK1C20		\
> +	EP3C120	\
>  "
>  
>  #########################################################################
> diff --git a/Makefile b/Makefile
> index 4532550..2139333 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -3533,6 +3533,12 @@ PK1C20_config : unconfig
>  PCI5441_config : unconfig
>  	@$(MKCONFIG)  PCI5441 nios2 nios2 pci5441 psyent
>  
> +# nios2 generic boards
> +NIOS2_GENERIC = EP3C120
> +
> +$(NIOS2_GENERIC:%=%_config) : unconfig
> +	@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
> +
>  #========================================================================
>  ## Microblaze
>  #========================================================================
> diff --git a/board/altera/nios2-generic/default_mmu.h b/board/altera/nios2-generic/default_mmu.h

IMHO this name is confusing but I am OK if make sense in altera world.

> new file mode 100644
> index 0000000..5637ae4
> --- /dev/null
> +++ b/board/altera/nios2-generic/default_mmu.h
> @@ -0,0 +1,131 @@
> +#ifndef _ALTERA_LINUX_CPU_H_
> +#define _ALTERA_LINUX_CPU_H_

Is it any reason why should be LINUX here? I expect that you will boot 
Linux but U-BOOT is not just about LINUX. IMHO _ALTERA_DEFAULT_MMU_H_ is 
better.

> +
> +/*
> + * This file was automatically generated by the swinfo2header utility.

Can you explain me how is this file generated?
Is there any connection with HW design?
What is the input for that swinfo2header utility?
Is it program which you can change?

I created for Microblaze one BSP which is directly called from design 
tools which generates unified names which are used in U-BOOT. This is 
IMHO the best way how to handle it.

> + *
> + * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
> + * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
> + */

As you wrote above your configuration depends on hw design which is the 
same problem as we faced for Microblaze and PPC.
If you connect board with any HW design, you will have troubles when you 
have to upgrade it. You will do upgrade and then you will send patch to 
U-BOOT. If you do it properly right now, you won't send any patch to U-BOOT.

> +
> +/*
> + * Macros for module 'linux_cpu', class 'altera_nios2'.
> + * The macros have no prefix.
> + */
> +#define CPU_IMPLEMENTATION "fast"

Is it use somewhere?

> +#define CPU_FREQ 125000000u
> +#define ICACHE_LINE_SIZE 32
> +#define ICACHE_SIZE 32768
> +#define DCACHE_LINE_SIZE 32
> +#define DCACHE_SIZE 32768
> +#define MMU_PRESENT

the same? Do you use MMU for U-BOOT or not?

> +#define KERNEL_REGION_BASE 0xc0000000

This parameter name is confusing.

> +#define IO_REGION_BASE 0xe0000000
> +#define EXCEPTION_ADDR 0xd0000020
> +#define RESET_ADDR 0xc2800000
> +#define BREAK_ADDR 0xc7fff820

the same

> +
> +/*
> + * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
> + * The macros are prefixed with 'CFI_FLASH_64M_'.
> + * The prefix is the slave descriptor.
> + */
> +#define CFI_FLASH_64M_BASE 0x0
> +#define CFI_FLASH_64M_SPAN 67108864u

How will look like parameters for 128M flash?
Will be good to use unified names.


> +
> +/*
> + * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
> + * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
> + * The prefix is the slave descriptor.
> + */
> +#define DESCRIPTOR_MEMORY_BASE 0x8002000
> +#define DESCRIPTOR_MEMORY_SPAN 8192u
> +
> +/*
> + * Macros for device 'tse_mac', class 'triple_speed_ethernet'
> + * The macros are prefixed with 'TSE_MAC_'.
> + * The prefix is the slave descriptor.
> + */
> +#define TSE_MAC_BASE 0x8004000
> +#define TSE_MAC_SPAN 1024u
> +#define TSE_MAC_TRANSMIT "sgdma_tx"
> +#define TSE_MAC_RECEIVE "sgdma_rx"

Is it use anywhere?

> +#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
> +#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
> +
> +/*
> + * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
> + * The macros are prefixed with 'SGDMA_RX_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SGDMA_RX_BASE 0x8004400
> +#define SGDMA_RX_SPAN 1024u
> +#define SGDMA_RX_IRQ 2

Do you use network driver with IRQ or polled mode?

> +
> +/*
> + * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
> + * The macros are prefixed with 'SGDMA_TX_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SGDMA_TX_BASE 0x8004800
> +#define SGDMA_TX_SPAN 1024u
> +#define SGDMA_TX_IRQ 3
> +
> +/*
> + * Macros for device 'uart', class 'altera_avalon_uart'
> + * The macros are prefixed with 'UART_'.
> + * The prefix is the slave descriptor.
> + */
> +#define UART_BASE 0x8004c80
> +#define UART_SPAN 32u
> +#define UART_IRQ 10

The same here. Do you use uart driver with IRQ support?

> +#define UART_BAUD 115200
> +#define UART_FREQ 62500000u
> +
> +/*
> + * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
> + * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
> + * The prefix is the slave descriptor.
> + */
> +#define USER_LED_PIO_8OUT_BASE 0x8004cc0
> +#define USER_LED_PIO_8OUT_SPAN 16u

IMHO unified name - what about name for 16 outputs?


> +
> +/*
> + * Macros for device 'sysid', class 'altera_avalon_sysid'
> + * The macros are prefixed with 'SYSID_'.
> + * The prefix is the slave descriptor.
> + */
> +#define SYSID_BASE 0x8004d40
> +#define SYSID_SPAN 8u
> +#define SYSID_ID 1174346794u
> +#define SYSID_TIMESTAMP 1233287581u
> +
> +/*
> + * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
> + * The macros are prefixed with 'JTAG_UART_'.
> + * The prefix is the slave descriptor.
> + */
> +#define JTAG_UART_BASE 0x8004d50
> +#define JTAG_UART_SPAN 8u
> +#define JTAG_UART_IRQ 1
> +
> +/*
> + * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
> + * The macros are prefixed with 'LINUX_TIMER_1MS_'.
> + * The prefix is the slave descriptor.
> + */
> +#define LINUX_TIMER_1MS_BASE 0x8400000
> +#define LINUX_TIMER_1MS_SPAN 32u
> +#define LINUX_TIMER_1MS_IRQ 11
> +#define LINUX_TIMER_1MS_FREQ 125000000u

Unified name TIMER_BASE will be nice. I think that the name of timer is 
LINUX_TIMER_1MS and the tool generate this nice name. If someone change 
that name then have to change U-BOOT config file too.

> +
> +/*
> + * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
> + * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
> + * The prefix is the slave descriptor.
> + */
> +#define DDR2_LO_LATENCY_128M_BASE 0x10000000
> +#define DDR2_LO_LATENCY_128M_SPAN 134217728

MEMORY_BASE?

> +
> +
> +#endif /* _ALTERA_LINUX_CPU_H_ */
> diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
> new file mode 100644
> index 0000000..83f9e09
> --- /dev/null
> +++ b/include/configs/EP3C120.h
> @@ -0,0 +1,376 @@
> +/*
> + * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
> + * Scott McNutt <smcnutt at psyent.com>
> + * (C) Copyright 2010, Thomas Chou <thomas at wytron.com.tw>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#ifndef __CONFIG_H
> +#define __CONFIG_H
> +
> +/*
> + * BOARD/CPU
> + */
> +#include "../board/altera/nios2-generic/default_mmu.h"
> +#define CONFIG_BOARD_NAME "EP3C120"
> +#define CONFIG_EP3C120

Is it use anywhere?

> +
> +#define CONFIG_SYS_CLK_FREQ		CPU_FREQ
> +#define CONFIG_SYS_RESET_ADDR		RESET_ADDR
> +#define CONFIG_SYS_EXCEPTION_ADDR	EXCEPTION_ADDR
> +#define CONFIG_BOARD_EARLY_INIT_F	/* enable early board-spec. init */
> +#define CONFIG_BOARD_LATE_INIT		/* enable late board-spec. init */
> +
> +#ifndef KERNEL_REGION_BASE
> +# define KERNEL_REGION_BASE		0		/* NOMMU */
> +#endif
> +
> +#ifndef IO_REGION_BASE
> +# define IO_REGION_BASE		0x80000000	/* NOMMU */
> +#endif

What does it mean? Do you use MMU for U-BOOT or not?
I am not sure about all CPU but I think that most of them not using MMU.

> +
> +/*
> + * CACHE -- the following will support II/s and II/f. The II/s does not
> + * have dcache, so the cache instructions will behave as NOPs.
> + */
> +#define CONFIG_SYS_ICACHE_SIZE		ICACHE_SIZE
> +#define CONFIG_SYS_ICACHELINE_SIZE	ICACHE_LINE_SIZE
> +#define CONFIG_SYS_DCACHE_SIZE		DCACHE_SIZE
> +#define CONFIG_SYS_DCACHELINE_SIZE	DCACHE_LINE_SIZE
> +
> +/*
> + * MEMORY BASE ADDRESSES
> + */
> +#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
> +#define CONFIG_SYS_SDRAM_SIZE		(DDR2_LO_LATENCY_128M_SPAN)
> +
> +/*
> + * GPIO
> + */
> +#define CONFIG_SYS_GPIO_BASE		(GPIO_BASE | IO_REGION_BASE)
> +#ifdef CONFIG_SYS_GPIO_BASE
> +# define CONFIG_SYS_GPIO_NRB 2
> +# define CONFIG_SYS_GPIO_HBT 3
> +#endif
> +
> +/*
> + * Flash Settings
> + */
> +/* #define CONFIG_SYS_NO_FLASH */
> +#define CONFIG_FLASH_CFI_DRIVER
> +#define CONFIG_FLASH_CFI_MTD
> +
> +#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
> +#define CONFIG_SYS_FLASH_BASE		(CFI_FLASH_64M_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_SYS_FLASH_PROTECTION
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1
> +#define CONFIG_SYS_MAX_FLASH_SECT	512
> +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> +
> +/*
> + * SPI FLash,EPCS Settings
> + */
> +/* #define CONFIG_CMD_SPI */
> +/* #define CONFIG_CMD_SF */
> +/* #define CONFIG_SPI_FLASH */
> +/* #define CONFIG_ALTERA_SPI */
> +
> +#define CONFIG_ENV_SPI_MAX_HZ		30000000
> +#define CONFIG_SF_DEFAULT_SPEED	30000000
> +#define CONFIG_SPI_FLASH_STMICRO
> +#define CONFIG_SYS_SPI_BASE		((EPCS_CONTROLLER_BASE + \
> +					  EPCS_CONTROLLER_REGISTER_OFFSET) \
> +					 | IO_REGION_BASE)
> +
> +/*
> + * NAND Flash
> + */
> +/* #define CONFIG_CMD_NAND */
> +/* #define CONFIG_NAND_PLAT */
> +
> +#define CONFIG_SYS_MAX_NAND_DEVICE	1
> +#define CONFIG_SYS_NAND_BASE		(NAND_FLASH_BASE | IO_REGION_BASE)
> +#define NIOS2_NAND_PLAT_CLE		2
> +#define NIOS2_NAND_PLAT_ALE		3
> +#define NAND_PLAT_WRITE_CMD(chip, cmd) \
> +	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
> +	       (1 << NIOS2_NAND_PLAT_CLE))
> +#define NAND_PLAT_WRITE_ADR(chip, cmd) \
> +	writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
> +	       (1 << NIOS2_NAND_PLAT_ALE))
> +#define NAND_PLAT_INIT() {}
> +#ifdef CONFIG_SYS_GPIO_NRB
> +# define NAND_PLAT_DEV_READY(chip) \
> +	readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
> +#endif
> +
> +/*
> + * SERIAL
> + */
> +/* #define CONFIG_ALTERA_UART */
> +#define CONFIG_ALTERA_JTAG_UART
> +
> +#if defined(CONFIG_ALTERA_JTAG_UART)
> +#define CONFIG_SYS_NIOS_CONSOLE	(JTAG_UART_BASE | IO_REGION_BASE)
> +#else
> +#define CONFIG_SYS_NIOS_CONSOLE	(UART_BASE | IO_REGION_BASE)
> +#endif
> +
> +#define CONFIG_ALTERA_JTAG_UART_BYPASS
> +#define CONFIG_SYS_UART_FREQ		UART_FREQ
> +#define CONFIG_BAUDRATE		UART_BAUD	/* Initial baudrate */
> +#define CONFIG_SYS_BAUDRATE_TABLE	{UART_BAUD}
> +#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* Suppress console info */
> +
> +/*
> + * SYSID
> + */
> +#define CONFIG_SYS_NIOS_SYSID_BASE	(SYSID_BASE | IO_REGION_BASE)
> +
> +/*
> + * TIMER
> + */
> +#define CONFIG_SYS_NIOS_TMRBASE	(LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_NIOS_TMRIRQ		LINUX_TIMER_1MS_IRQ
> +#define CONFIG_SYS_HZ			1000	/* Always 1000 */
> +#define CONFIG_SYS_NIOS_TMRMS		1	/* Desired period (msec)*/
> +#define CONFIG_SYS_NIOS_TMRCNT \
> +	(CONFIG_SYS_NIOS_TMRMS * (LINUX_TIMER_1MS_FREQ / 1000) - 1)
> +
> +/*
> + * STATUS LED
> + */
> +#define CONFIG_STATUS_LED		/* Enable status driver */
> +#define CONFIG_EPLED			/* Enable LED PIO driver */
> +#define CONFIG_SYS_LEDPIO_ADDR		(USER_LED_PIO_8OUT_BASE | \
> +					 IO_REGION_BASE)
> +/* #define CONFIG_GPIOLED */
> +
> +#define STATUS_LED_BIT			1	/* Bit-0 on PIO */
> +#define STATUS_LED_STATE		1	/* Blinking */
> +#define STATUS_LED_PERIOD	(500 / CONFIG_SYS_NIOS_TMRMS) /* 500 msec */
> +
> +/*
> + * IDE support
> + */
> +/* #define CONFIG_CMD_IDE */
> +
> +#define CONFIG_SYS_PIO_MODE		1
> +#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
> +#define CONFIG_SYS_IDE_MAXDEVICE	1
> +#define CONFIG_SYS_ATA_BASE_ADDR	(CF_IDE_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ATA_STRIDE		4	/* 1bit shift */
> +#define CONFIG_SYS_ATA_DATA_OFFSET	0x0	/* data reg offset */
> +#define CONFIG_SYS_ATA_REG_OFFSET	0x0	/* reg offset */
> +#define CONFIG_SYS_ATA_ALT_OFFSET	0x20	/* alternate register offset */
> +#define CONFIG_SYS_CF_CTL_BASE		(CF_CTL_BASE | IO_REGION_BASE)
> +#define CONFIG_IDE_RESET
> +
> +/*
> + * ETHERNET
> + */
> +/* #define CONFIG_SMC91111 */
> +#define CONFIG_SMC91111_BASE	((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
> +				 | IO_REGION_BASE) /* Base addr	*/
> +#undef	CONFIG_SMC91111_EXT_PHY		/* Internal PHY	*/
> +#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
> +
> +/* #define CONFIG_DRIVER_DM9000 */
> +#define CONFIG_DM9000_BASE		(DM9000_BASE | IO_REGION_BASE)
> +#define DM9000_IO			CONFIG_DM9000_BASE
> +#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
> +#define CONFIG_DM9000_USE_16BIT	1
> +#define CONFIG_DM9000_NO_SROM		1
> +/* #define CONFIG_NET_RETRY_COUNT		20 */
> +/* #define CONFIG_RESET_PHY_R		1 */
> +
> +/* #define CONFIG_ALTERA_TSE */
> +/* #define CONFIG_MII		1 */
> +/* #define CONFIG_CMD_MII */
> +/* #define CONFIG_ETHPRIME "tse0" */
> +#undef  CONFIG_PCI
> +
> +#define CONFIG_SYS_NUM_TSE_MACS			1
> +#define CONFIG_SYS_ALTERA_TSE_0_NAME		"tse0"
> +#define CONFIG_SYS_ALTERA_TSE_0_BASE		(TSE_MAC_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE	(SGDMA_RX_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE	(SGDMA_TX_BASE | IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ	SGDMA_RX_IRQ
> +#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ	SGDMA_TX_IRQ
> +#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM	0
> +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE	(DESCRIPTOR_MEMORY_BASE | \
> +						 IO_REGION_BASE)
> +#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	DESCRIPTOR_MEMORY_SPAN
> +#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	TSE_MAC_RECEIVE_FIFO_DEPTH
> +#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	TSE_MAC_TRANSMIT_FIFO_DEPTH
 > +#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR	18

This is nice example. Why don't move these values to default_mmu.h and
directly fill that values?

For example:
/* TSE: <IP name> */
#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN	0xXXXXXXX
#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH	2048
#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH	2048

Look more straight forward and none have to look for it.

I briefly look at the rest. There are the same thing as above.

Regards,
Michal


> +
> +/* TSE Supported modes */
> +/* GMII/MII	= 0 */
> +/* RGMII	= 1 */
> +/* RGMII_ID	= 2 */
> +/* RGMII_TXID	= 3 */
> +/* RGMII_RXID	= 4 */
> +/* SGMII	= 5 */
> +#define CONFIG_SYS_ALTERA_TSE_0_FLAGS		0x0
> +
> +/* #define CONFIG_ETHOC */
> +#define CONFIG_SYS_ETHOC_BASE		(IGOR_MAC_BASE | IO_REGION_BASE)
> +
> +#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
> +#define CONFIG_NETMASK		255.255.255.0
> +#define CONFIG_IPADDR		192.168.1.10
> +#define CONFIG_GWADDR		192.168.1.1
> +#define CONFIG_SERVERIP	192.168.1.1
> +#define CONFIG_BOOTDELAY	5
> +
> +/*
> + * Command line configuration.
> + */
> +#include <config_cmd_default.h>
> +#undef CONFIG_CMD_BOOTD
> +#undef CONFIG_CMD_FPGA
> +#undef CONFIG_CMD_IMLS
> +#undef CONFIG_CMD_ITEST
> +#undef CONFIG_CMD_NFS
> +#undef CONFIG_CMD_SETGETDCR
> +#undef CONFIG_CMD_XIMG
> +
> +#ifdef CONFIG_CMD_NET
> +# define CONFIG_NET_MULTI
> +# define CONFIG_CMD_DHCP
> +# define CONFIG_CMD_PING
> +#endif
> +
> +#define CONFIG_CMD_SAVES
> +#define CONFIG_CMD_JFFS2
> +#define CONFIG_JFFS2_CMDLINE
> +/* #define CONFIG_CMD_FAT */
> +/* #define CONFIG_DOS_PARTITION */
> +/* #define CONFIG_CMD_UBI */
> +/* #define CONFIG_CMD_UBIFS */
> +/* #define CONFIG_RBTREE */
> +#define CONFIG_MTD_DEVICE
> +#define CONFIG_MTD_PARTITIONS
> +#define CONFIG_CMD_MTDPARTS
> +/* #define CONFIG_LZO */
> +
> +/*
> + * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
> + * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
> + * reset address, no? This will keep the environment in user region
> + * of flash. NOTE: the monitor length must be multiple of sector size
> + * (which is common practice).
> + */
> +#define CONFIG_ENV_IS_IN_FLASH
> +/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
> +/* #define CONFIG_ENV_IS_IN_NAND */
> +
> +#if defined(CONFIG_ENV_IS_IN_FLASH)
> +# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
> +# define CONFIG_ENV_OVERWRITE		/* Serial change Ok	*/
> +# define CONFIG_ENV_ADDR		((CONFIG_SYS_RESET_ADDR + \
> +					  CONFIG_SYS_MONITOR_LEN) | \
> +					 IO_REGION_BASE)
> +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
> +# define CONFIG_ENV_OFFSET		0x7e0000	/* last sector */
> +# define CONFIG_ENV_SIZE		0x20000	/* 1 sector */
> +# define CONFIG_ENV_SECT_SIZE		0x20000
> +# define CONFIG_ENV_SPI_BUS		0
> +# define CONFIG_ENV_SPI_CS		0
> +# define CONFIG_ENV_SPI_MAX_HZ		30000000	/*30Mhz */
> +#elif defined(CONFIG_ENV_IS_IN_NAND)
> +# define CONFIG_ENV_OFFSET		0x40000
> +# define CONFIG_ENV_SIZE		0x40000	/* 1 sector */
> +#else
> +# define CONFIG_ENV_IS_NOWHERE		1	/* if env in SDRAM */
> +# define CONFIG_ENV_SIZE		0x20000
> +#endif
> +
> +/*
> + * MEMORY ORGANIZATION
> + *	-Monitor at top of sdram.
> + *	-The heap is placed below the monitor
> + *	-Global data is placed below the heap.
> + *	-The stack is placed below global data (&grows down).
> + */
> +#define CONFIG_MONITOR_IS_IN_RAM
> +#ifdef CONFIG_CMD_UBI
> +# define CONFIG_SYS_MONITOR_LEN	0x80000	/* Reserve 512k */
> +#else
> +# define CONFIG_SYS_MONITOR_LEN	0x40000	/* Reserve 256k */
> +#endif
> +#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_SDRAM_BASE + \
> +					 CONFIG_SYS_SDRAM_SIZE - \
> +					 CONFIG_SYS_MONITOR_LEN)
> +#define CONFIG_SYS_GBL_DATA_SIZE	256	/* Global data size rsvd */
> +#ifdef CONFIG_CMD_UBI			/* UBI needs >512KB malloc */
> +# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x100000)
> +#else
> +# define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 0x20000)
> +#endif
> +#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - \
> +					 CONFIG_SYS_MALLOC_LEN)
> +#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - \
> +					 CONFIG_SYS_GBL_DATA_SIZE)
> +#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
> +
> +/*
> + * MISC
> + */
> +#define CONFIG_SYS_LONGHELP		/* Provide extended help */
> +#define CONFIG_SYS_PROMPT		"==> "	/* Command prompt	*/
> +#define CONFIG_SYS_CBSIZE		256	/* Console I/O buf size */
> +#define CONFIG_SYS_MAXARGS		16	/* Max command args	*/
> +#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Bootarg buf size */
> +#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
> +					sizeof(CONFIG_SYS_PROMPT) + \
> +					 16)	/* Print buf size */
> +#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_INIT_SP - 0x20000)
> +
> +#if defined(CONFIG_NAND_PLAT)
> +# define MTD_ENV_SETTINGS \
> +	"mtdids=nand0=nand0\0"						\
> +	"mtdparts=mtdparts=nand0:-(data)\0"
> +#elif defined(CONFIG_FLASH_CFI_DRIVER)
> +# define MTD_ENV_SETTINGS \
> +	"mtdids=nor0=physmap-flash.0\0"				\
> +	"mtdparts=mtdparts=physmap-flash.0:40m(JFFS),1M(U-Boot),4m(uImage1)," \
> +	"4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
> +	"3584k(USER_IMAGE),512k(options-bits)\0"
> +#else
> +# define MTD_ENV_SETTINGS
> +#endif
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +	MTD_ENV_SETTINGS
> +
> +#define CONFIG_CMDLINE_EDITING
> +
> +/* Use the HUSH parser */
> +#define CONFIG_SYS_HUSH_PARSER
> +#ifdef CONFIG_SYS_HUSH_PARSER
> +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
> +#endif
> +
> +#endif /* __CONFIG_H */


-- 
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian