[U-Boot] [PATCH] fsl-ddr: Add extra cycle to turnaround times

[Kumar Gala]

From: Dave Liu <daveliu at freescale.com>

Add an extra cycle turnaround time to read->write to ensure stability
at high DDR frequencies.

Signed-off-by: Dave Liu <daveliu at freescale.com>
---
 cpu/mpc8xxx/ddr/ctrl_regs.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 03f9c43..4a282bc 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
 	pre_pd_exit_mclk = act_pd_exit_mclk;
 	taxpd_mclk = 8;
 	tmrd_mclk = 4;
+	/* set the turnaround time */
+	trwt_mclk = 1;
 #else /* CONFIG_FSL_DDR2 */
 	/*
 	 * (tXARD and tXARDS). Empirical?
-- 
1.6.0.6