[U-Boot] [PATCH] POST: Added ECC memory test for mpc83xx.

[Michael Zaidman]

On Sat, Apr 17, 2010 at 12:20 PM, Joakim Tjernlund
<joakim.tjernlund at transmode.se> wrote:
>>
>> Michael Zaidman <michael.zaidman at gmail.com> wrote on 2010/04/16 18:44:12:
>> >
>> > On Fri, Apr 16, 2010 at 1:25 AM, Kim Phillips
>> > <kim.phillips at freescale.com> wrote:
>> > > On Thu, 8 Apr 2010 10:37:08 +0200
>> > > Joakim Tjernlund <joakim.tjernlund at transmode.se> wrote:
>> > >
>> > >> Kim Phillips <kim.phillips at freescale.com> wrote on 2010-04-08 10:27:03:
>> >
>> > I also agree with Joakim regarding the routine call overhead and
>> > replacing it by inline macro. Please review this code.
>> >
>> > From 5a64a5c4f480dcea89bc8f13f8464b96b888b73c Mon Sep 17 00:00:00 2001
>> > From: Michael Zaidman <michael.zaidman at gmail.com>
>> > Date: Fri, 16 Apr 2010 18:50:43 +0300
>> > Subject: [U-Boot][PATCH] asm-ppc/io.h - added 64bits I/O accessors for ppc32.
>> >
>> > Suggested-by: Joakim Tjernlund <joakim.tjernlund at transmode.se>
>> > Signed-off-by: Michael Zaidman <michael.zaidman at gmail.com>
>> > ---
>> >  include/asm-ppc/io.h |   49 +++++++++++++++++++++++++++++++++++++++++++++++++
>> >  1 files changed, 49 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
>> > index 4ddad26..0d5e125 100644
>> > --- a/include/asm-ppc/io.h
>> > +++ b/include/asm-ppc/io.h
>> > @@ -231,6 +231,31 @@ extern inline unsigned in_be32(const volatile
>> > unsigned __iomem *addr)
>> >     return ret;
>> >  }
>> >
>> > +/* 64 bits I/O read accessor for ppc32 */
>> > +extern inline void in_be64(volatile unsigned __iomem *addr, volatile
>> > unsigned __iomem *ret)
>> > +{
>> > +/* FIXME: Add other CPUs without FPU here... */
>> > +#if defined(CONFIG_MPC832x)
>> > +   __asm__ __volatile__(
>> > +         "sync\n"
>> > +         "lwz%U0%X0 0,%0\n"
>> > +         "stw%U1%X1 0,%1\n"
>> > +         "lwz%U0%X0 0,4+%0\n"
>> > +         "stw%U1%X1 0,4+%1\n"
>> > +         "isync"
>> > +         :"=m" (*ret)
>> > +         :"m"  (*addr), "r" (addr), "r" (ret));
>>
>> To emulate FP better you should do 2 loads first and then 2 stores.
>> It is also faster.
>
> Forgot, you can add the MPC8xx CPU's too. These are also without FPU.
>
>
Ok, thanks, the code below does this. I did not succeed however to
force the compiler to assign register for temporary storage and used
r5 explicitly.

/* 64 bits I/O read accessor for ppc32 */
extern inline void in_be64(volatile unsigned __iomem *addr, volatile
unsigned __iomem *ret)
{
/* FIXME: Add other CPUs without FPU here... */
#if defined(CONFIG_MPC832x) || defined(CONFIG_MPC8xx)
       __asm__ __volatile__(
				"sync\n"
				"lwz%U0%X0 0,%0\n"
				"lwz%U0%X0 5,4+%0\n"
				"sync\n"
				"stw%U1%X1 0,%1\n"
				"stw%U1%X1 5,4+%1\n"
				"isync"
				:"=m" (*ret)
				:"m"  (*addr), "r" (addr), "r" (ret)
				:"r0", "r5"
				);
#else
       __asm__ __volatile__(
				"sync\n"
				"lfd%U0%X0  1,%0\n"
				"stfd%U1%X1 1,%1\n"
				"isync"
				:"=m" (*ret)
				:"m"  (*addr), "r" (addr), "r" (ret));
#endif
}

/* 64 bits I/O write accessor for ppc32 */
extern inline void out_be64(volatile unsigned __iomem *addr, volatile
unsigned __iomem *val)
{
/* FIXME: Add other CPUs without FPU here... */
#if defined(CONFIG_MPC832x) || defined(CONFIG_MPC8xx)
       __asm__ __volatile__(
				"sync\n"
				"lwz%U0%X0 0,%0\n"
				"lwz%U0%X0 5,4+%0\n"
				"sync\n"
				"stw%U1%X1 0,%1\n"
				"stw%U1%X1 5,4+%1\n"
				:"=m" (*addr)
				:"m"  (*val), "r" (addr), "r" (val)
				:"r0", "r5"
				);
#else
       __asm__ __volatile__(
				"sync\n"
				"lfd%U1%X1  1,%1\n"
				"stfd%U0%X0 1,%0"
				:"=m" (*addr)
				:"m"  (*val), "r" (addr), "r" (val));
#endif
}

-michael